K3-2KL band decoder suitable for GAL16V8. (This code is under review.)

k3-2kl-banddec.vhd

-- A K3-2KL band decoder suitable for GAL16V8.
-- (C) 2011 B1Z.
-- Currently, nothing about licensing is considered.
-- Author: BD1ES.


-- Define a chip independent kernel.
library ieee;
use ieee.std_logic_1164.all;

entity k3_2kl is
port(
    key_out_lp: in std_logic;
    k3_on:      in std_logic;
    band:       in std_logic_vector(3 downto 0);

    en_2kl:     out std_logic;
    da_out:     out std_logic_vector(6 downto 0)
    );
end;

architecture rtl of k3_2kl is
signal en_temp: std_logic;
signal da_temp: std_logic_vector(6 downto 0);
begin
    da_out <= da_temp;

en: process(k3_on, key_out_lp, en_temp)
    begin
        if (k3_on = '1') and (key_out_lp = '0') and (en_temp = '1') then
            en_2kl <= '1';
        else
            en_2kl <= '0';
        end if;
    end process en;

chk:process(band)
    begin
        case band is
            when "0001" => en_temp <= '1';
            when "0010" => en_temp <= '1';
            when "0011" => en_temp <= '1';
            when "0100" => en_temp <= '1';
            when "0101" => en_temp <= '1';
            when "0110" => en_temp <= '1';
            when "0111" => en_temp <= '1';
            when "1000" => en_temp <= '1';
            when "1001" => en_temp <= '1';
            when others => en_temp <= '0';
        end case;
    end process chk;

-- For 8V reference,
-- Vout = (DAout/128)*Vref*(1+Rf/Ra), and
-- DAout = 128*Vout*Ra/(Vref*(Ra+Rf))
-- Since Rf = 10k, Ra = 10k, VRef = 3.9V,
-- da_temp = 16.41 * Voltage

dec:process(band)
    begin
        case band is
            when "0001" => da_temp <= "1111011";    -- 1.8M,   7.5V
            when "0010" => da_temp <= "1100111";    -- 3.5M,   6.25V
            when "0011" => da_temp <= "1010110";    -- 7M,     5.25V
            when "0100" => da_temp <= "0001010";    -- 10M,    0.6V
            when "0101" => da_temp <= "1000110";    -- 14M,    4.25V
            when "0110" => da_temp <= "0110101";    -- 18-21M, 3.25V
            when "0111" => da_temp <= "0110101";    -- 18-21M, 3.25V
            when "1000" => da_temp <= "0100101";    -- 24-28M, 2.25V
            when "1001" => da_temp <= "0100101";    -- 24-28M, 2.25V
            when others => da_temp <= "0100101";    -- 24-28M, 2.25V
        end case;
    end process dec;
end rtl;


-- Integrate the kernel into 16V8
library ieee;
use ieee.std_logic_1164.all;

entity k3_2kl_16v8 is
port(
    key_out_lp: in std_logic;
    k3_on:      in std_logic;
    band:       in std_logic_vector(3 downto 0);

    en_2kl:     out std_logic;
    da_out:     out std_logic_vector(6 downto 0)
    );

-- Define P16V8R constrains for a PDIP 20 Package
attribute LOC:                  string;
attribute LOC of key_out_lp:    signal is "P4";
attribute LOC of k3_on:         signal is "P5";
attribute LOC of band:          signal is "P6 P7 P8 P9";
attribute LOC of en_2kl:        signal is "P19";
attribute LOC of da_out:        signal is "P18 P17 P16 P15 P14 P13 P12 ";
end;

architecture impl of k3_2kl_16v8 is
component k3_2kl
port(
    key_out_lp: in std_logic;
    k3_on:      in std_logic;
    band:       in std_logic_vector(3 downto 0);

    en_2kl:     out std_logic;
    da_out:     out std_logic_vector(6 downto 0)
    );
end component;
begin
u1: k3_2kl port map(
        key_out_lp => key_out_lp,
        k3_on => k3_on,
        band => band,
        en_2kl => en_2kl,
        da_out => da_out);
end impl;