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beholdnec/test2 out.txt

Created September 30, 2021 01:51
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Output of compiling test2.cpp with Clang on ldstk-clobber-y branch
Raw
test2 out.txt
Args: clang (LLVM option parsing) -force-precise-rotation-cost -jump-inst-cost=6 -phi-node-folding-threshold=0 -two-entry-phi-node-folding-threshold=0 -align-large-globals=false -disable-spill-hoist -debug
Args: clang
Features:
CPU:mos6502
TuneCPU:mos6502
Features:
CPU:mos6502
TuneCPU:mos6502
SROA function: _Z11testIndCallc
SROA alloca: %b = alloca %class.Base*, align 1
Rewriting FCA loads and stores...
Slices of alloca: %b = alloca %class.Base*, align 1
[0,2) slice #0
used by: store %class.Base* %4, %class.Base** %b, align 1, !tbaa !5
[0,2) slice #1
used by: store %class.Base* %7, %class.Base** %b, align 1, !tbaa !5
[0,2) slice #2
used by: %8 = load %class.Base*, %class.Base** %b, align 1, !tbaa !5
[0,2) slice #3
used by: %11 = load %class.Base*, %class.Base** %b, align 1, !tbaa !5
[0,2) slice #4 (splittable)
used by: call void @llvm.lifetime.start.p0i8(i64 2, i8* %0) #9
[0,2) slice #5 (splittable)
used by: call void @llvm.lifetime.end.p0i8(i64 2, i8* %14) #9
Pre-splitting loads and stores
Searching for candidate loads and stores
Rewriting alloca partition [0,2) to: %b = alloca %class.Base*, align 1
rewriting [0,2) slice #0
original: store %class.Base* %4, %class.Base** %b, align 1, !tbaa !5
to: store %class.Base* %4, %class.Base** %b, align 1, !tbaa !5
rewriting [0,2) slice #1
original: store %class.Base* %7, %class.Base** %b, align 1, !tbaa !5
to: store %class.Base* %7, %class.Base** %b, align 1, !tbaa !5
rewriting [0,2) slice #2
original: %8 = load %class.Base*, %class.Base** %b, align 1, !tbaa !5
to: %b.0. = load %class.Base*, %class.Base** %b, align 1, !tbaa !5
rewriting [0,2) slice #3
original: %11 = load %class.Base*, %class.Base** %b, align 1, !tbaa !5
to: %b.0.4 = load %class.Base*, %class.Base** %b, align 1, !tbaa !5
rewriting [0,2) slice #4 (splittable)
original: call void @llvm.lifetime.start.p0i8(i64 2, i8* %0) #9
to: call void @llvm.lifetime.start.p0i8(i64 2, i8* %b.0..sroa_cast)
rewriting [0,2) slice #5 (splittable)
original: call void @llvm.lifetime.end.p0i8(i64 2, i8* %14) #9
to: call void @llvm.lifetime.end.p0i8(i64 2, i8* %b.0..sroa_cast5)
Speculating PHIs
Speculating Selects
Deleting dead instruction: call void @llvm.lifetime.end.p0i8(i64 2, i8* %14) #9
Deleting dead instruction: %14 = bitcast %class.Base** %b to i8*
Deleting dead instruction: call void @llvm.lifetime.start.p0i8(i64 2, i8* %0) #9
Deleting dead instruction: %0 = bitcast %class.Base** %b to i8*
Deleting dead instruction: %10 = load %class.Base*, %class.Base** %b, align 1, !tbaa !5
Deleting dead instruction: %7 = load %class.Base*, %class.Base** %b, align 1, !tbaa !5
Deleting dead instruction: store %class.Base* %6, %class.Base** %b, align 1, !tbaa !5
Deleting dead instruction: store %class.Base* %3, %class.Base** %b, align 1, !tbaa !5
SROA alloca: %sel.addr = alloca i8, align 1
Rewriting FCA loads and stores...
Slices of alloca: %sel.addr = alloca i8, align 1
[0,1) slice #0 (splittable)
used by: store i8 %sel, i8* %sel.addr, align 1, !tbaa !2
[0,1) slice #1 (splittable)
used by: %0 = load i8, i8* %sel.addr, align 1, !tbaa !2
Pre-splitting loads and stores
Searching for candidate loads and stores
Rewriting alloca partition [0,1) to: %sel.addr = alloca i8, align 1
rewriting [0,1) slice #0 (splittable)
original: store i8 %sel, i8* %sel.addr, align 1, !tbaa !2
to: store i8 %sel, i8* %sel.addr, align 1, !tbaa !2
rewriting [0,1) slice #1 (splittable)
original: %0 = load i8, i8* %sel.addr, align 1, !tbaa !2
to: %sel.addr.0.load = load i8, i8* %sel.addr, align 1
Speculating PHIs
Speculating Selects
Deleting dead instruction: %0 = load i8, i8* %sel.addr, align 1, !tbaa !2
Deleting dead instruction: store i8 %sel, i8* %sel.addr, align 1, !tbaa !2
Promoting allocas with mem2reg...
EarlyCSE CVP: Add conditional value for 'tobool' as i1 true in if.then
EarlyCSE Simplify: %1 = bitcast %class.SubA* %0 to i8* to: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #9
EarlyCSE Simplify: %isnull = icmp eq %class.Base* %b.0, null to: i1 false
EarlyCSE CSE: %7 = bitcast %class.Base* %b.0 to void (%class.Base*)*** to: %5 = bitcast %class.Base* %b.0 to void (%class.Base*)***
EarlyCSE CVP: Add conditional value for 'tobool' as i1 false in if.else
EarlyCSE Simplify: %3 = bitcast %class.SubB* %2 to i8* to: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #9
SROA function: _ZN4SubAC2Ev
SROA alloca: %this.addr = alloca %class.SubA*, align 1
Rewriting FCA loads and stores...
Slices of alloca: %this.addr = alloca %class.SubA*, align 1
[0,2) slice #0
used by: store %class.SubA* %this, %class.SubA** %this.addr, align 1, !tbaa !2
[0,2) slice #1
used by: %this1 = load %class.SubA*, %class.SubA** %this.addr, align 1
Pre-splitting loads and stores
Searching for candidate loads and stores
Rewriting alloca partition [0,2) to: %this.addr = alloca %class.SubA*, align 1
rewriting [0,2) slice #0
original: store %class.SubA* %this, %class.SubA** %this.addr, align 1, !tbaa !2
to: store %class.SubA* %this, %class.SubA** %this.addr, align 1, !tbaa !2
rewriting [0,2) slice #1
original: %this1 = load %class.SubA*, %class.SubA** %this.addr, align 1
to: %this.addr.0.this1 = load %class.SubA*, %class.SubA** %this.addr, align 1
Speculating PHIs
Speculating Selects
Deleting dead instruction: %this1 = load %class.SubA*, %class.SubA** %this.addr, align 1
Deleting dead instruction: store %class.SubA* %this, %class.SubA** %this.addr, align 1, !tbaa !2
Promoting allocas with mem2reg...
SROA function: _ZN4SubBC2Ev
SROA alloca: %this.addr = alloca %class.SubB*, align 1
Rewriting FCA loads and stores...
Slices of alloca: %this.addr = alloca %class.SubB*, align 1
[0,2) slice #0
used by: store %class.SubB* %this, %class.SubB** %this.addr, align 1, !tbaa !2
[0,2) slice #1
used by: %this1 = load %class.SubB*, %class.SubB** %this.addr, align 1
Pre-splitting loads and stores
Searching for candidate loads and stores
Rewriting alloca partition [0,2) to: %this.addr = alloca %class.SubB*, align 1
rewriting [0,2) slice #0
original: store %class.SubB* %this, %class.SubB** %this.addr, align 1, !tbaa !2
to: store %class.SubB* %this, %class.SubB** %this.addr, align 1, !tbaa !2
rewriting [0,2) slice #1
original: %this1 = load %class.SubB*, %class.SubB** %this.addr, align 1
to: %this.addr.0.this1 = load %class.SubB*, %class.SubB** %this.addr, align 1
Speculating PHIs
Speculating Selects
Deleting dead instruction: %this1 = load %class.SubB*, %class.SubB** %this.addr, align 1
Deleting dead instruction: store %class.SubB* %this, %class.SubB** %this.addr, align 1, !tbaa !2
Promoting allocas with mem2reg...
SROA function: _ZN4BaseC2Ev
SROA alloca: %this.addr = alloca %class.Base*, align 1
Rewriting FCA loads and stores...
Slices of alloca: %this.addr = alloca %class.Base*, align 1
[0,2) slice #0
used by: store %class.Base* %this, %class.Base** %this.addr, align 1, !tbaa !2
[0,2) slice #1
used by: %this1 = load %class.Base*, %class.Base** %this.addr, align 1
Pre-splitting loads and stores
Searching for candidate loads and stores
Rewriting alloca partition [0,2) to: %this.addr = alloca %class.Base*, align 1
rewriting [0,2) slice #0
original: store %class.Base* %this, %class.Base** %this.addr, align 1, !tbaa !2
to: store %class.Base* %this, %class.Base** %this.addr, align 1, !tbaa !2
rewriting [0,2) slice #1
original: %this1 = load %class.Base*, %class.Base** %this.addr, align 1
to: %this.addr.0.this1 = load %class.Base*, %class.Base** %this.addr, align 1
Speculating PHIs
Speculating Selects
Deleting dead instruction: %this1 = load %class.Base*, %class.Base** %this.addr, align 1
Deleting dead instruction: store %class.Base* %this, %class.Base** %this.addr, align 1, !tbaa !2
Promoting allocas with mem2reg...
SROA function: _ZN4SubAD0Ev
SROA alloca: %this.addr = alloca %class.SubA*, align 1
Rewriting FCA loads and stores...
Slices of alloca: %this.addr = alloca %class.SubA*, align 1
[0,2) slice #0
used by: store %class.SubA* %this, %class.SubA** %this.addr, align 1, !tbaa !2
[0,2) slice #1
used by: %this1 = load %class.SubA*, %class.SubA** %this.addr, align 1
Pre-splitting loads and stores
Searching for candidate loads and stores
Rewriting alloca partition [0,2) to: %this.addr = alloca %class.SubA*, align 1
rewriting [0,2) slice #0
original: store %class.SubA* %this, %class.SubA** %this.addr, align 1, !tbaa !2
to: store %class.SubA* %this, %class.SubA** %this.addr, align 1, !tbaa !2
rewriting [0,2) slice #1
original: %this1 = load %class.SubA*, %class.SubA** %this.addr, align 1
to: %this.addr.0.this1 = load %class.SubA*, %class.SubA** %this.addr, align 1
Speculating PHIs
Speculating Selects
Deleting dead instruction: %this1 = load %class.SubA*, %class.SubA** %this.addr, align 1
Deleting dead instruction: store %class.SubA* %this, %class.SubA** %this.addr, align 1, !tbaa !2
Promoting allocas with mem2reg...
SROA function: _ZN4SubA2fnEv
SROA alloca: %this.addr = alloca %class.SubA*, align 1
Rewriting FCA loads and stores...
Slices of alloca: %this.addr = alloca %class.SubA*, align 1
[0,2) slice #0
used by: store %class.SubA* %this, %class.SubA** %this.addr, align 1, !tbaa !2
[0,2) slice #1
used by: %this1 = load %class.SubA*, %class.SubA** %this.addr, align 1
Pre-splitting loads and stores
Searching for candidate loads and stores
Rewriting alloca partition [0,2) to: %this.addr = alloca %class.SubA*, align 1
rewriting [0,2) slice #0
original: store %class.SubA* %this, %class.SubA** %this.addr, align 1, !tbaa !2
to: store %class.SubA* %this, %class.SubA** %this.addr, align 1, !tbaa !2
rewriting [0,2) slice #1
original: %this1 = load %class.SubA*, %class.SubA** %this.addr, align 1
to: %this.addr.0.this1 = load %class.SubA*, %class.SubA** %this.addr, align 1
Speculating PHIs
Speculating Selects
Deleting dead instruction: %this1 = load %class.SubA*, %class.SubA** %this.addr, align 1
Deleting dead instruction: store %class.SubA* %this, %class.SubA** %this.addr, align 1, !tbaa !2
Promoting allocas with mem2reg...
SROA function: _ZN4BaseD0Ev
SROA alloca: %this.addr = alloca %class.Base*, align 1
Rewriting FCA loads and stores...
Slices of alloca: %this.addr = alloca %class.Base*, align 1
[0,2) slice #0
used by: store %class.Base* %this, %class.Base** %this.addr, align 1, !tbaa !2
[0,2) slice #1
used by: %this1 = load %class.Base*, %class.Base** %this.addr, align 1
Pre-splitting loads and stores
Searching for candidate loads and stores
Rewriting alloca partition [0,2) to: %this.addr = alloca %class.Base*, align 1
rewriting [0,2) slice #0
original: store %class.Base* %this, %class.Base** %this.addr, align 1, !tbaa !2
to: store %class.Base* %this, %class.Base** %this.addr, align 1, !tbaa !2
rewriting [0,2) slice #1
original: %this1 = load %class.Base*, %class.Base** %this.addr, align 1
to: %this.addr.0.this1 = load %class.Base*, %class.Base** %this.addr, align 1
Speculating PHIs
Speculating Selects
Deleting dead instruction: %this1 = load %class.Base*, %class.Base** %this.addr, align 1
Deleting dead instruction: store %class.Base* %this, %class.Base** %this.addr, align 1, !tbaa !2
Promoting allocas with mem2reg...
SROA function: _ZN4BaseD2Ev
SROA alloca: %this.addr = alloca %class.Base*, align 1
Rewriting FCA loads and stores...
Slices of alloca: %this.addr = alloca %class.Base*, align 1
[0,2) slice #0
used by: store %class.Base* %this, %class.Base** %this.addr, align 1, !tbaa !2
[0,2) slice #1
used by: %this1 = load %class.Base*, %class.Base** %this.addr, align 1
Pre-splitting loads and stores
Searching for candidate loads and stores
Rewriting alloca partition [0,2) to: %this.addr = alloca %class.Base*, align 1
rewriting [0,2) slice #0
original: store %class.Base* %this, %class.Base** %this.addr, align 1, !tbaa !2
to: store %class.Base* %this, %class.Base** %this.addr, align 1, !tbaa !2
rewriting [0,2) slice #1
original: %this1 = load %class.Base*, %class.Base** %this.addr, align 1
to: %this.addr.0.this1 = load %class.Base*, %class.Base** %this.addr, align 1
Speculating PHIs
Speculating Selects
Deleting dead instruction: %this1 = load %class.Base*, %class.Base** %this.addr, align 1
Deleting dead instruction: store %class.Base* %this, %class.Base** %this.addr, align 1, !tbaa !2
Promoting allocas with mem2reg...
SROA function: _ZN4SubBD0Ev
SROA alloca: %this.addr = alloca %class.SubB*, align 1
Rewriting FCA loads and stores...
Slices of alloca: %this.addr = alloca %class.SubB*, align 1
[0,2) slice #0
used by: store %class.SubB* %this, %class.SubB** %this.addr, align 1, !tbaa !2
[0,2) slice #1
used by: %this1 = load %class.SubB*, %class.SubB** %this.addr, align 1
Pre-splitting loads and stores
Searching for candidate loads and stores
Rewriting alloca partition [0,2) to: %this.addr = alloca %class.SubB*, align 1
rewriting [0,2) slice #0
original: store %class.SubB* %this, %class.SubB** %this.addr, align 1, !tbaa !2
to: store %class.SubB* %this, %class.SubB** %this.addr, align 1, !tbaa !2
rewriting [0,2) slice #1
original: %this1 = load %class.SubB*, %class.SubB** %this.addr, align 1
to: %this.addr.0.this1 = load %class.SubB*, %class.SubB** %this.addr, align 1
Speculating PHIs
Speculating Selects
Deleting dead instruction: %this1 = load %class.SubB*, %class.SubB** %this.addr, align 1
Deleting dead instruction: store %class.SubB* %this, %class.SubB** %this.addr, align 1, !tbaa !2
Promoting allocas with mem2reg...
SROA function: _ZN4SubB2fnEv
SROA alloca: %this.addr = alloca %class.SubB*, align 1
Rewriting FCA loads and stores...
Slices of alloca: %this.addr = alloca %class.SubB*, align 1
[0,2) slice #0
used by: store %class.SubB* %this, %class.SubB** %this.addr, align 1, !tbaa !2
[0,2) slice #1
used by: %this1 = load %class.SubB*, %class.SubB** %this.addr, align 1
Pre-splitting loads and stores
Searching for candidate loads and stores
Rewriting alloca partition [0,2) to: %this.addr = alloca %class.SubB*, align 1
rewriting [0,2) slice #0
original: store %class.SubB* %this, %class.SubB** %this.addr, align 1, !tbaa !2
to: store %class.SubB* %this, %class.SubB** %this.addr, align 1, !tbaa !2
rewriting [0,2) slice #1
original: %this1 = load %class.SubB*, %class.SubB** %this.addr, align 1
to: %this.addr.0.this1 = load %class.SubB*, %class.SubB** %this.addr, align 1
Speculating PHIs
Speculating Selects
Deleting dead instruction: %this1 = load %class.SubB*, %class.SubB** %this.addr, align 1
Deleting dead instruction: store %class.SubB* %this, %class.SubB** %this.addr, align 1, !tbaa !2
Promoting allocas with mem2reg...
Marking Block Executable: entry
markOverdefined: i8 %sel
Marking Block Executable: entry
markOverdefined: %class.SubA* %this
Marking Block Executable: entry
markOverdefined: %class.SubB* %this
Marking Block Executable: entry
markOverdefined: %class.Base* %this
Marking Block Executable: entry
markOverdefined: %class.SubA* %this
Marking Block Executable: entry
markOverdefined: %class.SubA* %this
Marking Block Executable: entry
markOverdefined: %class.Base* %this
Marking Block Executable: entry
markOverdefined: %class.Base* %this
Marking Block Executable: entry
markOverdefined: %class.SubB* %this
Marking Block Executable: entry
markOverdefined: %class.SubB* %this
Popped off OI-WL: %class.SubB* %this
Popped off OI-WL: %class.SubB* %this
markOverdefined: %0 = bitcast %class.SubB* %this to i8*
Popped off OI-WL: %0 = bitcast %class.SubB* %this to i8*
Popped off OI-WL: %class.Base* %this
Popped off OI-WL: %class.Base* %this
Popped off OI-WL: %class.SubA* %this
Popped off OI-WL: %class.SubA* %this
markOverdefined: %0 = bitcast %class.SubA* %this to i8*
Popped off OI-WL: %0 = bitcast %class.SubA* %this to i8*
Popped off OI-WL: %class.Base* %this
markOverdefined: %0 = bitcast %class.Base* %this to i32 (...)***
Popped off OI-WL: %0 = bitcast %class.Base* %this to i32 (...)***
Popped off OI-WL: %class.SubB* %this
markOverdefined: %1 = bitcast %class.SubB* %this to i32 (...)***
markOverdefined: %0 = bitcast %class.SubB* %this to %class.Base*
Popped off OI-WL: %0 = bitcast %class.SubB* %this to %class.Base*
Popped off OI-WL: %1 = bitcast %class.SubB* %this to i32 (...)***
Popped off OI-WL: %class.SubA* %this
markOverdefined: %1 = bitcast %class.SubA* %this to i32 (...)***
markOverdefined: %0 = bitcast %class.SubA* %this to %class.Base*
Popped off OI-WL: %0 = bitcast %class.SubA* %this to %class.Base*
Popped off OI-WL: %1 = bitcast %class.SubA* %this to i32 (...)***
Popped off OI-WL: i8 %sel
markOverdefined: %tobool = icmp ne i8 %sel, 0
Popped off OI-WL: %tobool = icmp ne i8 %sel, 0
Marking Block Executable: if.then
Marking Block Executable: if.else
Popped off BBWL:
if.else: ; preds = %entry
%call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #9
%2 = bitcast i8* %call1 to %class.SubB*
call void @llvm.memset.p0i8.i16(i8* align 2 %call1, i8 0, i16 2, i1 false)
call void @_ZN4SubBC2Ev(%class.SubB* nonnull dereferenceable(2) %2) #10
%3 = bitcast %class.SubB* %2 to %class.Base*
br label %if.end
Merged overdefined into %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #9 : overdefined
markOverdefined: %2 = bitcast i8* %call1 to %class.SubB*
markOverdefined: %3 = bitcast %class.SubB* %2 to %class.Base*
Marking Block Executable: if.end
Popped off BBWL:
if.end: ; preds = %if.else, %if.then
%b.0 = phi %class.Base* [ %1, %if.then ], [ %3, %if.else ]
%4 = bitcast %class.Base* %b.0 to void (%class.Base*)***
%vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
%vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i64 2
%5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
br i1 false, label %delete.end, label %delete.notnull
Merged overdefined into %b.0 = phi %class.Base* [ %1, %if.then ], [ %3, %if.else ] : overdefined
markOverdefined: %4 = bitcast %class.Base* %b.0 to void (%class.Base*)***
Merged overdefined into %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2 : overdefined
markOverdefined: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i64 2
Merged overdefined into %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1 : overdefined
Marking Block Executable: delete.notnull
Popped off BBWL:
delete.notnull: ; preds = %if.end
%vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
%vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i64 1
%6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
call void %6(%class.Base* nonnull dereferenceable(2) %b.0) #10
br label %delete.end
Merged overdefined into %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2 : overdefined
markOverdefined: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i64 1
Merged overdefined into %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1 : overdefined
Marking Block Executable: delete.end
Popped off BBWL:
delete.end: ; preds = %delete.notnull, %if.end
ret void
Popped off BBWL:
if.then: ; preds = %entry
%call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #9
%0 = bitcast i8* %call to %class.SubA*
call void @llvm.memset.p0i8.i16(i8* align 2 %call, i8 0, i16 2, i1 false)
call void @_ZN4SubAC2Ev(%class.SubA* nonnull dereferenceable(2) %0) #10
%1 = bitcast %class.SubA* %0 to %class.Base*
br label %if.end
Merged overdefined into %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #9 : overdefined
markOverdefined: %0 = bitcast i8* %call to %class.SubA*
markOverdefined: %1 = bitcast %class.SubA* %0 to %class.Base*
Marking Edge Executable: if.then -> if.end
Popped off BBWL:
entry:
ret void
Popped off BBWL:
entry:
call void bitcast (void (%class.Base*)* @_ZN4BaseD2Ev to void (%class.SubB*)*)(%class.SubB* nonnull dereferenceable(2) %this) #9
%0 = bitcast %class.SubB* %this to i8*
call void @_ZdlPv(i8* %0) #10
ret void
Popped off BBWL:
entry:
ret void
Popped off BBWL:
entry:
call void @llvm.trap() #9
unreachable
Popped off BBWL:
entry:
ret void
Popped off BBWL:
entry:
call void bitcast (void (%class.Base*)* @_ZN4BaseD2Ev to void (%class.SubA*)*)(%class.SubA* nonnull dereferenceable(2) %this) #9
%0 = bitcast %class.SubA* %this to i8*
call void @_ZdlPv(i8* %0) #10
ret void
Popped off BBWL:
entry:
%0 = bitcast %class.Base* %this to i32 (...)***
store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i32 0, inrange i32 0, i32 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
ret void
Popped off BBWL:
entry:
%0 = bitcast %class.SubB* %this to %class.Base*
call void @_ZN4BaseC2Ev(%class.Base* nonnull dereferenceable(2) %0) #9
%1 = bitcast %class.SubB* %this to i32 (...)***
store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i32 0, inrange i32 0, i32 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
ret void
Popped off BBWL:
entry:
%0 = bitcast %class.SubA* %this to %class.Base*
call void @_ZN4BaseC2Ev(%class.Base* nonnull dereferenceable(2) %0) #9
%1 = bitcast %class.SubA* %this to i32 (...)***
store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i32 0, inrange i32 0, i32 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
ret void
Popped off BBWL:
entry:
%tobool = icmp ne i8 %sel, 0
br i1 %tobool, label %if.then, label %if.else
Popped off OI-WL: %1 = bitcast %class.SubA* %0 to %class.Base*
Popped off OI-WL: %0 = bitcast i8* %call to %class.SubA*
Popped off OI-WL: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #9
Popped off OI-WL: %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
Popped off OI-WL: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i64 1
Popped off OI-WL: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
Popped off OI-WL: %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
Popped off OI-WL: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i64 2
Popped off OI-WL: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
Popped off OI-WL: %4 = bitcast %class.Base* %b.0 to void (%class.Base*)***
Popped off OI-WL: %b.0 = phi %class.Base* [ %1, %if.then ], [ %3, %if.else ]
Popped off OI-WL: %3 = bitcast %class.SubB* %2 to %class.Base*
Popped off OI-WL: %2 = bitcast i8* %call1 to %class.SubB*
Popped off OI-WL: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #9
RESOLVING UNDEFS
Deleting edge %if.end -> %delete.end
NCD %if.end, ToIDom %if.end
IsReachableFromIDom %delete.end
Pred %delete.notnull
Support %if.end
%delete.end is reachable from support %if.end
Deleting reachable %if.end -> %delete.end
Rebuilding subtree
Top of subtree: %if.end
Running Semi-NCA
Marking Block Executable: entry
Marking Block Executable: entry
Marking Block Executable: entry
Marking Block Executable: entry
Marking Block Executable: entry
Marking Block Executable: entry
Marking Block Executable: entry
Marking Block Executable: entry
Marking Block Executable: entry
Marking Block Executable: entry
Popped off BBWL:
entry:
ret void
Popped off BBWL:
entry:
call void bitcast (void (%class.Base*)* @_ZN4BaseD2Ev to void (%class.SubB*)*)(%class.SubB* nonnull dereferenceable(2) %this) #9
%0 = bitcast %class.SubB* %this to i8*
call void @_ZdlPv(i8* %0) #10
ret void
Popped off BBWL:
entry:
ret void
Popped off BBWL:
entry:
call void @llvm.trap() #9
unreachable
Popped off BBWL:
entry:
ret void
Popped off BBWL:
entry:
call void bitcast (void (%class.Base*)* @_ZN4BaseD2Ev to void (%class.SubA*)*)(%class.SubA* nonnull dereferenceable(2) %this) #9
%0 = bitcast %class.SubA* %this to i8*
call void @_ZdlPv(i8* %0) #10
ret void
Popped off BBWL:
entry:
%0 = bitcast %class.Base* %this to i32 (...)***
store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i32 0, inrange i32 0, i32 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
ret void
Popped off BBWL:
entry:
%0 = bitcast %class.SubB* %this to %class.Base*
call void @_ZN4BaseC2Ev(%class.Base* nonnull dereferenceable(2) %0) #9
%1 = bitcast %class.SubB* %this to i32 (...)***
store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i32 0, inrange i32 0, i32 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
ret void
Popped off BBWL:
entry:
%0 = bitcast %class.SubA* %this to %class.Base*
call void @_ZN4BaseC2Ev(%class.Base* nonnull dereferenceable(2) %0) #9
%1 = bitcast %class.SubA* %this to i32 (...)***
store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i32 0, inrange i32 0, i32 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
ret void
Popped off BBWL:
entry:
%tobool = icmp ne i8 %sel, 0
br i1 %tobool, label %if.then, label %if.else
Marking Edge Executable: entry -> if.then
Marking Block Executable: if.then
Marking Edge Executable: entry -> if.else
Marking Block Executable: if.else
Popped off BBWL:
if.else: ; preds = %entry
%call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #9
%2 = bitcast i8* %call1 to %class.SubB*
call void @llvm.memset.p0i8.i16(i8* align 2 %call1, i8 0, i16 2, i1 false)
call void @_ZN4SubBC2Ev(%class.SubB* nonnull dereferenceable(2) %2) #10
%3 = bitcast %class.SubB* %2 to %class.Base*
br label %if.end
Marking Edge Executable: if.else -> if.end
Marking Block Executable: if.end
Popped off BBWL:
if.end: ; preds = %if.else, %if.then
%b.0 = phi %class.Base* [ %1, %if.then ], [ %3, %if.else ]
%4 = bitcast %class.Base* %b.0 to void (%class.Base*)***
%vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
%vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i64 2
%5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
br label %delete.notnull
Marking Edge Executable: if.end -> delete.notnull
Marking Block Executable: delete.notnull
Popped off BBWL:
delete.notnull: ; preds = %if.end
%vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
%vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i64 1
%6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
call void %6(%class.Base* nonnull dereferenceable(2) %b.0) #10
br label %delete.end
Marking Edge Executable: delete.notnull -> delete.end
Marking Block Executable: delete.end
Popped off BBWL:
delete.end: ; preds = %delete.notnull
ret void
Popped off BBWL:
if.then: ; preds = %entry
%call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #9
%0 = bitcast i8* %call to %class.SubA*
call void @llvm.memset.p0i8.i16(i8* align 2 %call, i8 0, i16 2, i1 false)
call void @_ZN4SubAC2Ev(%class.SubA* nonnull dereferenceable(2) %0) #10
%1 = bitcast %class.SubA* %0 to %class.Base*
br label %if.end
Marking Edge Executable: if.then -> if.end
Popped off V-WL: %1 = bitcast %class.SubA* %0 to %class.Base*
Popped off V-WL: %0 = bitcast i8* %call to %class.SubA*
Popped off V-WL: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #9
Popped off V-WL: %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
Popped off V-WL: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i64 1
Popped off V-WL: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
Popped off V-WL: %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
Popped off V-WL: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i64 2
Popped off V-WL: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
Popped off V-WL: %4 = bitcast %class.Base* %b.0 to void (%class.Base*)***
Popped off V-WL: %b.0 = phi %class.Base* [ %1, %if.then ], [ %3, %if.else ]
Popped off V-WL: %3 = bitcast %class.SubB* %2 to %class.Base*
Popped off V-WL: %2 = bitcast i8* %call1 to %class.SubB*
Popped off V-WL: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #9
Popped off V-WL: %tobool = icmp ne i8 %sel, 0
Popped off V-WL: %1 = bitcast %class.SubA* %this to i32 (...)***
Popped off V-WL: %0 = bitcast %class.SubA* %this to %class.Base*
Popped off V-WL: %1 = bitcast %class.SubB* %this to i32 (...)***
Popped off V-WL: %0 = bitcast %class.SubB* %this to %class.Base*
Popped off V-WL: %0 = bitcast %class.Base* %this to i32 (...)***
Popped off V-WL: %0 = bitcast %class.SubA* %this to i8*
Popped off V-WL: %0 = bitcast %class.SubB* %this to i8*
GLOBAL DEAD: ; Function Attrs: argmemonly nofree nosync nounwind willreturn
declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1
GLOBAL DEAD: ; Function Attrs: argmemonly nofree nosync nounwind willreturn
declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #4
DeadArgumentEliminationPass - Deleting dead varargs
DeadArgumentEliminationPass - Determining liveness
DeadArgumentEliminationPass - Intrinsically live fn: _Z11testIndCallc
DeadArgumentEliminationPass - Intrinsically live fn: _Znwt
DeadArgumentEliminationPass - Intrinsically live fn: llvm.memset.p0i8.i16
DeadArgumentEliminationPass - Intrinsically live fn: _ZN4SubAC2Ev
DeadArgumentEliminationPass - Intrinsically live fn: _ZN4SubBC2Ev
DeadArgumentEliminationPass - Intrinsically live fn: _ZN4BaseC2Ev
DeadArgumentEliminationPass - Intrinsically live fn: _ZN4SubAD0Ev
DeadArgumentEliminationPass - Intrinsically live fn: _ZN4SubA2fnEv
DeadArgumentEliminationPass - Intrinsically live fn: _ZN4BaseD0Ev
DeadArgumentEliminationPass - Intrinsically live fn: __cxa_pure_virtual
DeadArgumentEliminationPass - Intrinsically live fn: llvm.trap
DeadArgumentEliminationPass - Intrinsically live fn: _ZdlPv
DeadArgumentEliminationPass - Intrinsically live fn: _ZN4BaseD2Ev
DeadArgumentEliminationPass - Intrinsically live fn: _ZN4SubBD0Ev
DeadArgumentEliminationPass - Intrinsically live fn: _ZN4SubB2fnEv
INSTCOMBINE ITERATION #1 on _Z11testIndCallc
IC: ADD: br label %if.end
IC: ADD: %1 = bitcast %class.SubA* %0 to %class.Base*
IC: ADD: call void @_ZN4SubAC2Ev(%class.SubA* nonnull dereferenceable(2) %0) #9
IC: ADD: call void @llvm.memset.p0i8.i16(i8* align 2 %call, i8 0, i16 2, i1 false)
IC: ADD: %0 = bitcast i8* %call to %class.SubA*
IC: ADD: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: ADD: ret void
IC: ADD: br label %delete.end
IC: ADD: call void %6(%class.Base* nonnull dereferenceable(2) %b.0) #9
IC: ADD: %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: ADD: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i64 1
IC: ADD: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: ADD: br label %delete.notnull
IC: ADD: call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
IC: ADD: %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: ADD: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i64 2
IC: ADD: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: ADD: %4 = bitcast %class.Base* %b.0 to void (%class.Base*)***
IC: ADD: %b.0 = phi %class.Base* [ %1, %if.then ], [ %3, %if.else ]
IC: ADD: br label %if.end
IC: ADD: %3 = bitcast %class.SubB* %2 to %class.Base*
IC: ADD: call void @_ZN4SubBC2Ev(%class.SubB* nonnull dereferenceable(2) %2) #9
IC: ADD: call void @llvm.memset.p0i8.i16(i8* align 2 %call1, i8 0, i16 2, i1 false)
IC: ADD: %2 = bitcast i8* %call1 to %class.SubB*
IC: ADD: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: ADD: br i1 %tobool, label %if.then, label %if.else
IC: ADD: %tobool = icmp ne i8 %sel, 0
IC: Visiting: %tobool = icmp ne i8 %sel, 0
IC: Mod = %tobool = icmp ne i8 %sel, 0
New = %tobool.not = icmp eq i8 %sel, 0
IC: ADD: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: br i1 %tobool.not, label %if.else, label %if.then
IC: Visiting: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: Visiting: %2 = bitcast i8* %call1 to %class.SubB*
IC: Visiting: call void @llvm.memset.p0i8.i16(i8* align 2 %call1, i8 0, i16 2, i1 false)
IC: ADD DEFERRED: %3 = bitcast i8* %call1 to i16*
IC: ADD DEFERRED: store i16 0, i16* %3, align 1
IC: Mod = call void @llvm.memset.p0i8.i16(i8* align 2 %call1, i8 0, i16 2, i1 false)
New = call void @llvm.memset.p0i8.i16(i8* align 2 %call1, i8 0, i16 0, i1 false)
IC: ADD: call void @llvm.memset.p0i8.i16(i8* align 2 %call1, i8 0, i16 0, i1 false)
IC: ADD: store i16 0, i16* %3, align 2
IC: ADD: %3 = bitcast i8* %call1 to i16*
IC: Visiting: %3 = bitcast i8* %call1 to i16*
IC: Visiting: store i16 0, i16* %3, align 2
IC: Visiting: call void @llvm.memset.p0i8.i16(i8* align 2 %call1, i8 0, i16 0, i1 false)
IC: ERASE call void @llvm.memset.p0i8.i16(i8* align 2 %call1, i8 0, i16 0, i1 false)
IC: ADD DEFERRED: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: ADD: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: Visiting: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: Visiting: call void @_ZN4SubBC2Ev(%class.SubB* nonnull dereferenceable(2) %2) #9
IC: Visiting: %4 = bitcast %class.SubB* %2 to %class.Base*
IC: Old = %4 = bitcast %class.SubB* %2 to %class.Base*
New = <badref> = getelementptr %class.SubB, %class.SubB* %2, i32 0, i32 0
IC: ADD: %4 = getelementptr %class.SubB, %class.SubB* %2, i32 0, i32 0
IC: ERASE %5 = bitcast %class.SubB* %2 to %class.Base*
IC: ADD DEFERRED: %2 = bitcast i8* %call1 to %class.SubB*
IC: ADD: %2 = bitcast i8* %call1 to %class.SubB*
IC: Visiting: %2 = bitcast i8* %call1 to %class.SubB*
IC: Visiting: %4 = getelementptr %class.SubB, %class.SubB* %2, i32 0, i32 0
IC: Mod = %4 = getelementptr %class.SubB, %class.SubB* %2, i32 0, i32 0
New = %4 = getelementptr %class.SubB, %class.SubB* %2, i16 0, i32 0
IC: ADD: %4 = getelementptr %class.SubB, %class.SubB* %2, i16 0, i32 0
IC: Visiting: %4 = getelementptr %class.SubB, %class.SubB* %2, i16 0, i32 0
IC: Old = %4 = getelementptr %class.SubB, %class.SubB* %2, i16 0, i32 0
New = <badref> = bitcast i8* %call1 to %class.Base*
IC: ADD: %4 = bitcast i8* %call1 to %class.Base*
IC: ERASE %5 = getelementptr %class.SubB, %class.SubB* %2, i16 0, i32 0
IC: ADD DEFERRED: %2 = bitcast i8* %call1 to %class.SubB*
IC: ADD: %2 = bitcast i8* %call1 to %class.SubB*
IC: Visiting: %2 = bitcast i8* %call1 to %class.SubB*
IC: Visiting: %4 = bitcast i8* %call1 to %class.Base*
IC: Visiting: br label %if.end
IC: Visiting: %b.0 = phi %class.Base* [ %1, %if.then ], [ %4, %if.else ]
IC: Visiting: %5 = bitcast %class.Base* %b.0 to void (%class.Base*)***
IC: Visiting: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %5, align 1, !tbaa !2
IC: Visiting: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i64 2
IC: Mod = %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i64 2
New = %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
IC: ADD: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
IC: Visiting: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
IC: Visiting: %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: Visiting: call void %6(%class.Base* nonnull dereferenceable(2) %b.0)
IC: Visiting: br label %delete.notnull
IC: Visiting: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %5, align 1, !tbaa !2
IC: Visiting: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i64 1
IC: Mod = %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i64 1
New = %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: ADD: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: Visiting: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: Visiting: %7 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: Visiting: call void %7(%class.Base* nonnull dereferenceable(2) %b.0) #9
IC: Visiting: br label %delete.end
IC: Visiting: ret void
IC: Visiting: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: Visiting: %0 = bitcast i8* %call to %class.SubA*
IC: Visiting: call void @llvm.memset.p0i8.i16(i8* align 2 %call, i8 0, i16 2, i1 false)
IC: ADD DEFERRED: %1 = bitcast i8* %call to i16*
IC: ADD DEFERRED: store i16 0, i16* %1, align 1
IC: Mod = call void @llvm.memset.p0i8.i16(i8* align 2 %call, i8 0, i16 2, i1 false)
New = call void @llvm.memset.p0i8.i16(i8* align 2 %call, i8 0, i16 0, i1 false)
IC: ADD: call void @llvm.memset.p0i8.i16(i8* align 2 %call, i8 0, i16 0, i1 false)
IC: ADD: store i16 0, i16* %1, align 2
IC: ADD: %1 = bitcast i8* %call to i16*
IC: Visiting: %1 = bitcast i8* %call to i16*
IC: Visiting: store i16 0, i16* %1, align 2
IC: Visiting: call void @llvm.memset.p0i8.i16(i8* align 2 %call, i8 0, i16 0, i1 false)
IC: ERASE call void @llvm.memset.p0i8.i16(i8* align 2 %call, i8 0, i16 0, i1 false)
IC: ADD DEFERRED: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: ADD: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: Visiting: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: Visiting: call void @_ZN4SubAC2Ev(%class.SubA* nonnull dereferenceable(2) %0) #9
IC: Visiting: %2 = bitcast %class.SubA* %0 to %class.Base*
IC: Old = %2 = bitcast %class.SubA* %0 to %class.Base*
New = <badref> = getelementptr %class.SubA, %class.SubA* %0, i32 0, i32 0
IC: ADD: %b.0 = phi %class.Base* [ %2, %if.then ], [ %6, %if.else ]
IC: ADD: %2 = getelementptr %class.SubA, %class.SubA* %0, i32 0, i32 0
IC: ERASE %3 = bitcast %class.SubA* %0 to %class.Base*
IC: ADD DEFERRED: %0 = bitcast i8* %call to %class.SubA*
IC: ADD: %0 = bitcast i8* %call to %class.SubA*
IC: Visiting: %0 = bitcast i8* %call to %class.SubA*
IC: Visiting: %2 = getelementptr %class.SubA, %class.SubA* %0, i32 0, i32 0
IC: Mod = %2 = getelementptr %class.SubA, %class.SubA* %0, i32 0, i32 0
New = %2 = getelementptr %class.SubA, %class.SubA* %0, i16 0, i32 0
IC: ADD: %2 = getelementptr %class.SubA, %class.SubA* %0, i16 0, i32 0
IC: Visiting: %2 = getelementptr %class.SubA, %class.SubA* %0, i16 0, i32 0
IC: Old = %2 = getelementptr %class.SubA, %class.SubA* %0, i16 0, i32 0
New = <badref> = bitcast i8* %call to %class.Base*
IC: ADD: %2 = bitcast i8* %call to %class.Base*
IC: ERASE %3 = getelementptr %class.SubA, %class.SubA* %0, i16 0, i32 0
IC: ADD DEFERRED: %0 = bitcast i8* %call to %class.SubA*
IC: ADD: %0 = bitcast i8* %call to %class.SubA*
IC: Visiting: %0 = bitcast i8* %call to %class.SubA*
IC: Visiting: %2 = bitcast i8* %call to %class.Base*
IC: Visiting: %b.0 = phi %class.Base* [ %2, %if.then ], [ %5, %if.else ]
IC: ADD DEFERRED: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
IC: Old = %b.0 = phi %class.Base* [ %2, %if.then ], [ %5, %if.else ]
New = <badref> = bitcast i8* %b.0.in to %class.Base*
IC: ADD: %7 = bitcast %class.Base* %b.0 to void (%class.Base*)***
IC: ADD: call void %8(%class.Base* nonnull dereferenceable(2) %b.0)
IC: ADD: call void %9(%class.Base* nonnull dereferenceable(2) %b.0) #9
IC: ADD: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: ERASE %6 = phi %class.Base* [ %2, %if.then ], [ %5, %if.else ]
IC: ADD DEFERRED: %2 = bitcast i8* %call to %class.Base*
IC: ADD DEFERRED: %5 = bitcast i8* %call1 to %class.Base*
IC: ERASE %5 = bitcast i8* %call1 to %class.Base*
IC: ADD DEFERRED: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: ADD: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: ERASE %2 = bitcast i8* %call to %class.Base*
IC: ADD DEFERRED: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: ADD: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: ADD: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
IC: Visiting: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
IC: Visiting: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: Visiting: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: Visiting: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: Visiting: call void %6(%class.Base* nonnull dereferenceable(2) %b.0) #9
IC: Visiting: call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
IC: Visiting: %4 = bitcast %class.Base* %b.0 to void (%class.Base*)***
IC: Old = %4 = bitcast %class.Base* %b.0 to void (%class.Base*)***
New = <badref> = bitcast i8* %b.0.in to void (%class.Base*)***
IC: ADD: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: ADD: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: ADD: %4 = bitcast i8* %b.0.in to void (%class.Base*)***
IC: ERASE %5 = bitcast %class.Base* %b.0 to void (%class.Base*)***
IC: ADD DEFERRED: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: ADD: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: Visiting: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: Visiting: %4 = bitcast i8* %b.0.in to void (%class.Base*)***
IC: Visiting: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: Visiting: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: Visiting: br label %if.end
INSTCOMBINE ITERATION #2 on _Z11testIndCallc
IC: ADD: br label %if.end
IC: ADD: call void @_ZN4SubBC2Ev(%class.SubB* nonnull dereferenceable(2) %2) #9
IC: ADD: store i16 0, i16* %3, align 2
IC: ADD: %3 = bitcast i8* %call1 to i16*
IC: ADD: %2 = bitcast i8* %call1 to %class.SubB*
IC: ADD: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: ADD: ret void
IC: ADD: br label %delete.end
IC: ADD: call void %6(%class.Base* nonnull dereferenceable(2) %b.0) #9
IC: ADD: %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: ADD: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: ADD: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: ADD: br label %delete.notnull
IC: ADD: call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
IC: ADD: %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: ADD: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
IC: ADD: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: ADD: %4 = bitcast i8* %b.0.in to void (%class.Base*)***
IC: ADD: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: ADD: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
IC: ADD: br label %if.end
IC: ADD: call void @_ZN4SubAC2Ev(%class.SubA* nonnull dereferenceable(2) %0) #9
IC: ADD: store i16 0, i16* %1, align 2
IC: ADD: %1 = bitcast i8* %call to i16*
IC: ADD: %0 = bitcast i8* %call to %class.SubA*
IC: ADD: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: ADD: br i1 %tobool.not, label %if.else, label %if.then
IC: ADD: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: br i1 %tobool.not, label %if.else, label %if.then
IC: Visiting: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: Visiting: %0 = bitcast i8* %call to %class.SubA*
IC: Visiting: %1 = bitcast i8* %call to i16*
IC: Visiting: store i16 0, i16* %1, align 2
IC: Visiting: call void @_ZN4SubAC2Ev(%class.SubA* nonnull dereferenceable(2) %0) #9
IC: Visiting: br label %if.end
IC: Visiting: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
IC: Visiting: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: Visiting: %4 = bitcast i8* %b.0.in to void (%class.Base*)***
IC: Visiting: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: Visiting: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
IC: Visiting: %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: Visiting: call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
IC: Visiting: br label %delete.notnull
IC: Visiting: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: Visiting: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: Visiting: %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: Visiting: call void %6(%class.Base* nonnull dereferenceable(2) %b.0) #9
IC: Visiting: br label %delete.end
IC: Visiting: ret void
IC: Visiting: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #8
IC: Visiting: %2 = bitcast i8* %call1 to %class.SubB*
IC: Visiting: %3 = bitcast i8* %call1 to i16*
IC: Visiting: store i16 0, i16* %3, align 2
IC: Visiting: call void @_ZN4SubBC2Ev(%class.SubB* nonnull dereferenceable(2) %2) #9
IC: Visiting: br label %if.end
Merging: delete.notnull into if.end
Merging: delete.end into if.end
INSTCOMBINE ITERATION #1 on _ZN4SubAC2Ev
IC: ConstFold operand of: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i32 0, inrange i32 0, i32 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
Old = i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i32 0, inrange i32 0, i32 2) to i32 (...)**)
New = i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**)
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: ADD: %1 = bitcast %class.SubA* %this to i32 (...)***
IC: ADD: call void @_ZN4BaseC2Ev(%class.Base* nonnull dereferenceable(2) %0) #8
IC: ADD: %0 = bitcast %class.SubA* %this to %class.Base*
IC: Visiting: %0 = bitcast %class.SubA* %this to %class.Base*
IC: Old = %0 = bitcast %class.SubA* %this to %class.Base*
New = <badref> = getelementptr inbounds %class.SubA, %class.SubA* %this, i32 0, i32 0
IC: ADD: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i32 0, i32 0
IC: ERASE %1 = bitcast %class.SubA* %this to %class.Base*
IC: Visiting: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i32 0, i32 0
IC: Mod = %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i32 0, i32 0
New = %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0
IC: ADD: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0
IC: Visiting: call void @_ZN4BaseC2Ev(%class.Base* nonnull dereferenceable(2) %0) #8
IC: Visiting: %1 = bitcast %class.SubA* %this to i32 (...)***
IC: Old = %1 = bitcast %class.SubA* %this to i32 (...)***
New = <badref> = getelementptr inbounds %class.SubA, %class.SubA* %this, i32 0, i32 0, i32 0
IC: ADD: %1 = getelementptr inbounds %class.SubA, %class.SubA* %this, i32 0, i32 0, i32 0
IC: ERASE %2 = bitcast %class.SubA* %this to i32 (...)***
IC: Visiting: %1 = getelementptr inbounds %class.SubA, %class.SubA* %this, i32 0, i32 0, i32 0
IC: Mod = %1 = getelementptr inbounds %class.SubA, %class.SubA* %this, i32 0, i32 0, i32 0
New = %1 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: ADD: %1 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: Visiting: %1 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: Visiting: ret void
INSTCOMBINE ITERATION #2 on _ZN4SubAC2Ev
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: ADD: %1 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: ADD: call void @_ZN4BaseC2Ev(%class.Base* nonnull dereferenceable(2) %0) #8
IC: ADD: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0
IC: Visiting: call void @_ZN4BaseC2Ev(%class.Base* nonnull dereferenceable(2) %0) #8
IC: Visiting: %1 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: Visiting: ret void
INSTCOMBINE ITERATION #1 on _ZN4SubBC2Ev
IC: ConstFold operand of: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i32 0, inrange i32 0, i32 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
Old = i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i32 0, inrange i32 0, i32 2) to i32 (...)**)
New = i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**)
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: ADD: %1 = bitcast %class.SubB* %this to i32 (...)***
IC: ADD: call void @_ZN4BaseC2Ev(%class.Base* nonnull dereferenceable(2) %0) #8
IC: ADD: %0 = bitcast %class.SubB* %this to %class.Base*
IC: Visiting: %0 = bitcast %class.SubB* %this to %class.Base*
IC: Old = %0 = bitcast %class.SubB* %this to %class.Base*
New = <badref> = getelementptr inbounds %class.SubB, %class.SubB* %this, i32 0, i32 0
IC: ADD: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i32 0, i32 0
IC: ERASE %1 = bitcast %class.SubB* %this to %class.Base*
IC: Visiting: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i32 0, i32 0
IC: Mod = %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i32 0, i32 0
New = %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0
IC: ADD: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0
IC: Visiting: call void @_ZN4BaseC2Ev(%class.Base* nonnull dereferenceable(2) %0) #8
IC: Visiting: %1 = bitcast %class.SubB* %this to i32 (...)***
IC: Old = %1 = bitcast %class.SubB* %this to i32 (...)***
New = <badref> = getelementptr inbounds %class.SubB, %class.SubB* %this, i32 0, i32 0, i32 0
IC: ADD: %1 = getelementptr inbounds %class.SubB, %class.SubB* %this, i32 0, i32 0, i32 0
IC: ERASE %2 = bitcast %class.SubB* %this to i32 (...)***
IC: Visiting: %1 = getelementptr inbounds %class.SubB, %class.SubB* %this, i32 0, i32 0, i32 0
IC: Mod = %1 = getelementptr inbounds %class.SubB, %class.SubB* %this, i32 0, i32 0, i32 0
New = %1 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: ADD: %1 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: Visiting: %1 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: Visiting: ret void
INSTCOMBINE ITERATION #2 on _ZN4SubBC2Ev
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: ADD: %1 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: ADD: call void @_ZN4BaseC2Ev(%class.Base* nonnull dereferenceable(2) %0) #8
IC: ADD: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0
IC: Visiting: call void @_ZN4BaseC2Ev(%class.Base* nonnull dereferenceable(2) %0) #8
IC: Visiting: %1 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: Visiting: ret void
INSTCOMBINE ITERATION #1 on _ZN4BaseC2Ev
IC: ConstFold operand of: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i32 0, inrange i32 0, i32 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
Old = i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i32 0, inrange i32 0, i32 2) to i32 (...)**)
New = i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**)
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %0 = bitcast %class.Base* %this to i32 (...)***
IC: Visiting: %0 = bitcast %class.Base* %this to i32 (...)***
IC: Old = %0 = bitcast %class.Base* %this to i32 (...)***
New = <badref> = getelementptr inbounds %class.Base, %class.Base* %this, i32 0, i32 0
IC: ADD: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i32 0, i32 0
IC: ERASE %1 = bitcast %class.Base* %this to i32 (...)***
IC: Visiting: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i32 0, i32 0
IC: Mod = %0 = getelementptr inbounds %class.Base, %class.Base* %this, i32 0, i32 0
New = %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
IC: ADD: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: ret void
INSTCOMBINE ITERATION #2 on _ZN4BaseC2Ev
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: ret void
INSTCOMBINE ITERATION #1 on _ZN4SubAD0Ev
IC: ADD: ret void
IC: ADD: call void @_ZdlPv(i8* %0) #9
IC: ADD: %0 = bitcast %class.SubA* %this to i8*
IC: ADD: call void bitcast (void (%class.Base*)* @_ZN4BaseD2Ev to void (%class.SubA*)*)(%class.SubA* nonnull dereferenceable(2) %this) #8
IC: Visiting: call void bitcast (void (%class.Base*)* @_ZN4BaseD2Ev to void (%class.SubA*)*)(%class.SubA* nonnull dereferenceable(2) %this) #8
IC: ADD DEFERRED: %0 = bitcast %class.SubA* %this to %class.Base*
IC: ADD DEFERRED: call void @_ZN4BaseD2Ev(%class.Base* %0)
IC: ERASE call void bitcast (void (%class.Base*)* @_ZN4BaseD2Ev to void (%class.SubA*)*)(%class.SubA* nonnull dereferenceable(2) %this) #8
IC: ADD: call void @_ZN4BaseD2Ev(%class.Base* nonnull dereferenceable(2) %0) #8
IC: ADD: %0 = bitcast %class.SubA* %this to %class.Base*
IC: Visiting: %0 = bitcast %class.SubA* %this to %class.Base*
IC: Old = %0 = bitcast %class.SubA* %this to %class.Base*
New = <badref> = getelementptr inbounds %class.SubA, %class.SubA* %this, i32 0, i32 0
IC: ADD: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i32 0, i32 0
IC: ERASE %1 = bitcast %class.SubA* %this to %class.Base*
IC: Visiting: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i32 0, i32 0
IC: Mod = %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i32 0, i32 0
New = %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0
IC: ADD: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0
IC: Visiting: call void @_ZN4BaseD2Ev(%class.Base* nonnull dereferenceable(2) %0) #8
IC: Visiting: %1 = bitcast %class.SubA* %this to i8*
IC: Visiting: call void @_ZdlPv(i8* %1) #9
IC: Mod = call void @_ZdlPv(i8* %1) #9
New = call void @_ZdlPv(i8* nonnull %1) #9
IC: ADD: call void @_ZdlPv(i8* nonnull %1) #9
IC: Visiting: call void @_ZdlPv(i8* nonnull %1) #9
IC: Visiting: ret void
INSTCOMBINE ITERATION #2 on _ZN4SubAD0Ev
IC: ADD: ret void
IC: ADD: call void @_ZdlPv(i8* nonnull %1) #9
IC: ADD: %1 = bitcast %class.SubA* %this to i8*
IC: ADD: call void @_ZN4BaseD2Ev(%class.Base* nonnull dereferenceable(2) %0) #8
IC: ADD: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0
IC: Visiting: call void @_ZN4BaseD2Ev(%class.Base* nonnull dereferenceable(2) %0) #8
IC: Visiting: %1 = bitcast %class.SubA* %this to i8*
IC: Visiting: call void @_ZdlPv(i8* nonnull %1) #9
IC: Visiting: ret void
INSTCOMBINE ITERATION #1 on _ZN4SubA2fnEv
IC: ADD: ret void
IC: Visiting: ret void
INSTCOMBINE ITERATION #1 on _ZN4BaseD0Ev
IC: ADD: unreachable
IC: ADD: call void @llvm.trap() #8
IC: Visiting: call void @llvm.trap() #8
IC: Visiting: unreachable
INSTCOMBINE ITERATION #1 on _ZN4BaseD2Ev
IC: ADD: ret void
IC: Visiting: ret void
INSTCOMBINE ITERATION #1 on _ZN4SubBD0Ev
IC: ADD: ret void
IC: ADD: call void @_ZdlPv(i8* %0) #9
IC: ADD: %0 = bitcast %class.SubB* %this to i8*
IC: ADD: call void bitcast (void (%class.Base*)* @_ZN4BaseD2Ev to void (%class.SubB*)*)(%class.SubB* nonnull dereferenceable(2) %this) #8
IC: Visiting: call void bitcast (void (%class.Base*)* @_ZN4BaseD2Ev to void (%class.SubB*)*)(%class.SubB* nonnull dereferenceable(2) %this) #8
IC: ADD DEFERRED: %0 = bitcast %class.SubB* %this to %class.Base*
IC: ADD DEFERRED: call void @_ZN4BaseD2Ev(%class.Base* %0)
IC: ERASE call void bitcast (void (%class.Base*)* @_ZN4BaseD2Ev to void (%class.SubB*)*)(%class.SubB* nonnull dereferenceable(2) %this) #8
IC: ADD: call void @_ZN4BaseD2Ev(%class.Base* nonnull dereferenceable(2) %0) #8
IC: ADD: %0 = bitcast %class.SubB* %this to %class.Base*
IC: Visiting: %0 = bitcast %class.SubB* %this to %class.Base*
IC: Old = %0 = bitcast %class.SubB* %this to %class.Base*
New = <badref> = getelementptr inbounds %class.SubB, %class.SubB* %this, i32 0, i32 0
IC: ADD: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i32 0, i32 0
IC: ERASE %1 = bitcast %class.SubB* %this to %class.Base*
IC: Visiting: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i32 0, i32 0
IC: Mod = %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i32 0, i32 0
New = %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0
IC: ADD: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0
IC: Visiting: call void @_ZN4BaseD2Ev(%class.Base* nonnull dereferenceable(2) %0) #8
IC: Visiting: %1 = bitcast %class.SubB* %this to i8*
IC: Visiting: call void @_ZdlPv(i8* %1) #9
IC: Mod = call void @_ZdlPv(i8* %1) #9
New = call void @_ZdlPv(i8* nonnull %1) #9
IC: ADD: call void @_ZdlPv(i8* nonnull %1) #9
IC: Visiting: call void @_ZdlPv(i8* nonnull %1) #9
IC: Visiting: ret void
INSTCOMBINE ITERATION #2 on _ZN4SubBD0Ev
IC: ADD: ret void
IC: ADD: call void @_ZdlPv(i8* nonnull %1) #9
IC: ADD: %1 = bitcast %class.SubB* %this to i8*
IC: ADD: call void @_ZN4BaseD2Ev(%class.Base* nonnull dereferenceable(2) %0) #8
IC: ADD: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0
IC: Visiting: call void @_ZN4BaseD2Ev(%class.Base* nonnull dereferenceable(2) %0) #8
IC: Visiting: %1 = bitcast %class.SubB* %this to i8*
IC: Visiting: call void @_ZdlPv(i8* nonnull %1) #9
IC: Visiting: ret void
INSTCOMBINE ITERATION #1 on _ZN4SubB2fnEv
IC: ADD: ret void
IC: Visiting: ret void
Building CG for module: test2.cpp
Adding '_Z11testIndCallc' to entry set of the graph.
Added callable function: _Z11testIndCallc
Adding '_ZN4SubAC2Ev' to entry set of the graph.
Added callable function: _ZN4SubAC2Ev
Adding '_ZN4SubBC2Ev' to entry set of the graph.
Added callable function: _ZN4SubBC2Ev
Adding '_ZN4BaseC2Ev' to entry set of the graph.
Added callable function: _ZN4BaseC2Ev
Adding '_ZN4SubAD0Ev' to entry set of the graph.
Added callable function: _ZN4SubAD0Ev
Adding '_ZN4SubA2fnEv' to entry set of the graph.
Added callable function: _ZN4SubA2fnEv
Adding '_ZN4BaseD0Ev' to entry set of the graph.
Added callable function: _ZN4BaseD0Ev
Adding '_ZN4BaseD2Ev' to entry set of the graph.
Added callable function: _ZN4BaseD2Ev
Adding '_ZN4SubBD0Ev' to entry set of the graph.
Added callable function: _ZN4SubBD0Ev
Adding '_ZN4SubB2fnEv' to entry set of the graph.
Added callable function: _ZN4SubB2fnEv
Adding functions referenced by global initializers to the entry set.
Adding functions called by '_Z11testIndCallc' to the graph.
Added callable function: _ZN4SubAC2Ev
Added callable function: _ZN4SubBC2Ev
Adding functions called by '_ZN4SubAC2Ev' to the graph.
Added callable function: _ZN4BaseC2Ev
Added callable function: _ZN4SubA2fnEv
Added callable function: _ZN4SubAD0Ev
Added callable function: _ZN4BaseD2Ev
Adding functions called by '_ZN4BaseC2Ev' to the graph.
Added callable function: _ZN4BaseD0Ev
Added callable function: _ZN4BaseD2Ev
Adding functions called by '_ZN4BaseD0Ev' to the graph.
Adding functions called by '_ZN4BaseD2Ev' to the graph.
Adding functions called by '_ZN4SubA2fnEv' to the graph.
Adding functions called by '_ZN4SubAD0Ev' to the graph.
Added callable function: _ZN4BaseD2Ev
Adding functions called by '_ZN4SubBC2Ev' to the graph.
Added callable function: _ZN4BaseC2Ev
Added callable function: _ZN4SubB2fnEv
Added callable function: _ZN4SubBD0Ev
Added callable function: _ZN4BaseD2Ev
Adding functions called by '_ZN4SubB2fnEv' to the graph.
Adding functions called by '_ZN4SubBD0Ev' to the graph.
Added callable function: _ZN4BaseD2Ev
Running an SCC pass across the RefSCC: [(_ZN4BaseD0Ev)]
Running function passes across an SCC: (_ZN4BaseD0Ev)
SROA function: _ZN4BaseD0Ev
Not running SpeculativeExecution because TTI->hasBranchDivergence() is false.
Jump threading on function '_ZN4BaseD0Ev'
INSTCOMBINE ITERATION #1 on _ZN4BaseD0Ev
IC: ADD: unreachable
IC: ADD: call void @llvm.trap() #8
IC: Visiting: call void @llvm.trap() #8
IC: Visiting: unreachable
Marked as tail call candidate: call void @llvm.trap() #8
Calculated Rank[this] = 3
INSTCOMBINE ITERATION #1 on _ZN4BaseD0Ev
IC: ADD: unreachable
IC: ADD: tail call void @llvm.trap() #8
IC: Visiting: tail call void @llvm.trap() #8
IC: Visiting: unreachable
SROA function: _ZN4BaseD0Ev
Instruction Merger
GVN iteration: 0
SCCP on function '_ZN4BaseD0Ev'
Marking Block Executable: entry
markOverdefined: %class.Base* %this
Popped off OI-WL: %class.Base* %this
Popped off BBWL:
entry:
tail call void @llvm.trap() #8
unreachable
RESOLVING UNDEFs
DemandedBits: Root: tail call void @llvm.trap() #8
DemandedBits: Root: unreachable
INSTCOMBINE ITERATION #1 on _ZN4BaseD0Ev
IC: ADD: unreachable
IC: ADD: tail call void @llvm.trap() #8
IC: Visiting: tail call void @llvm.trap() #8
IC: Visiting: unreachable
Jump threading on function '_ZN4BaseD0Ev'
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
mark live: tail call void @llvm.trap() #8
mark block live: entry
mark live: unreachable
work live: unreachable
work live: tail call void @llvm.trap() #8
final dead terminator blocks:
Trying to eliminate MemoryDefs at the end of the function
INSTCOMBINE ITERATION #1 on _ZN4BaseD0Ev
IC: ADD: unreachable
IC: ADD: tail call void @llvm.trap() #8
IC: Visiting: tail call void @llvm.trap() #8
IC: Visiting: unreachable
Running an SCC pass across the RefSCC: [(_ZN4BaseD2Ev)]
Running function passes across an SCC: (_ZN4BaseD2Ev)
SROA function: _ZN4BaseD2Ev
Not running SpeculativeExecution because TTI->hasBranchDivergence() is false.
Jump threading on function '_ZN4BaseD2Ev'
INSTCOMBINE ITERATION #1 on _ZN4BaseD2Ev
IC: ADD: ret void
IC: Visiting: ret void
Calculated Rank[this] = 3
INSTCOMBINE ITERATION #1 on _ZN4BaseD2Ev
IC: ADD: ret void
IC: Visiting: ret void
SROA function: _ZN4BaseD2Ev
Instruction Merger
GVN iteration: 0
SCCP on function '_ZN4BaseD2Ev'
Marking Block Executable: entry
markOverdefined: %class.Base* %this
Popped off OI-WL: %class.Base* %this
Popped off BBWL:
entry:
ret void
RESOLVING UNDEFs
DemandedBits: Root: ret void
INSTCOMBINE ITERATION #1 on _ZN4BaseD2Ev
IC: ADD: ret void
IC: Visiting: ret void
Jump threading on function '_ZN4BaseD2Ev'
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
mark live: ret void
mark block live: entry
post-dom root child is a return: entry
work live: ret void
final dead terminator blocks:
Trying to eliminate MemoryDefs at the end of the function
INSTCOMBINE ITERATION #1 on _ZN4BaseD2Ev
IC: ADD: ret void
IC: Visiting: ret void
Running an SCC pass across the RefSCC: [(_ZN4BaseC2Ev)]
Running function passes across an SCC: (_ZN4BaseC2Ev)
SROA function: _ZN4BaseC2Ev
Not running SpeculativeExecution because TTI->hasBranchDivergence() is false.
Jump threading on function '_ZN4BaseC2Ev'
LVI Getting block end value %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0 at 'entry'
PUSH: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0 in entry
POP %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0 in entry = notconstant<i32 (...)*** null>
Result = notconstant<i32 (...)*** null>
INSTCOMBINE ITERATION #1 on _ZN4BaseC2Ev
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: ret void
Calculated Rank[this] = 3
INSTCOMBINE ITERATION #1 on _ZN4BaseC2Ev
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: ret void
SROA function: _ZN4BaseC2Ev
Instruction Merger
GVN iteration: 0
SCCP on function '_ZN4BaseC2Ev'
Marking Block Executable: entry
markOverdefined: %class.Base* %this
Popped off OI-WL: %class.Base* %this
markOverdefined: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
Popped off OI-WL: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
Popped off BBWL:
entry:
%0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
ret void
RESOLVING UNDEFs
DemandedBits: Root: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
DemandedBits: Root: ret void
DemandedBits: Visiting: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
INSTCOMBINE ITERATION #1 on _ZN4BaseC2Ev
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: ret void
Jump threading on function '_ZN4BaseC2Ev'
LVI Getting block end value %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0 at 'entry'
PUSH: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0 in entry
POP %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0 in entry = notconstant<i32 (...)*** null>
Result = notconstant<i32 (...)*** null>
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
mark live: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
mark block live: entry
mark live: ret void
post-dom root child is a return: entry
work live: ret void
work live: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
mark live: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
work live: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
final dead terminator blocks:
Trying to eliminate MemoryDefs killed by 1 = MemoryDef(liveOnEntry) ( store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2)
trying to get dominating access
visiting 0 = MemoryDef(liveOnEntry)
... found LiveOnEntryDef
finished walk
Trying to eliminate MemoryDefs at the end of the function
INSTCOMBINE ITERATION #1 on _ZN4BaseC2Ev
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: ret void
Running an SCC pass across the RefSCC: [(_ZN4SubA2fnEv)]
Running function passes across an SCC: (_ZN4SubA2fnEv)
SROA function: _ZN4SubA2fnEv
Not running SpeculativeExecution because TTI->hasBranchDivergence() is false.
Jump threading on function '_ZN4SubA2fnEv'
INSTCOMBINE ITERATION #1 on _ZN4SubA2fnEv
IC: ADD: ret void
IC: Visiting: ret void
Calculated Rank[this] = 3
INSTCOMBINE ITERATION #1 on _ZN4SubA2fnEv
IC: ADD: ret void
IC: Visiting: ret void
SROA function: _ZN4SubA2fnEv
Instruction Merger
GVN iteration: 0
SCCP on function '_ZN4SubA2fnEv'
Marking Block Executable: entry
markOverdefined: %class.SubA* %this
Popped off OI-WL: %class.SubA* %this
Popped off BBWL:
entry:
ret void
RESOLVING UNDEFs
DemandedBits: Root: ret void
INSTCOMBINE ITERATION #1 on _ZN4SubA2fnEv
IC: ADD: ret void
IC: Visiting: ret void
Jump threading on function '_ZN4SubA2fnEv'
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
mark live: ret void
mark block live: entry
post-dom root child is a return: entry
work live: ret void
final dead terminator blocks:
Trying to eliminate MemoryDefs at the end of the function
INSTCOMBINE ITERATION #1 on _ZN4SubA2fnEv
IC: ADD: ret void
IC: Visiting: ret void
Running an SCC pass across the RefSCC: [(_ZN4SubAD0Ev)]
Inlining calls in: _ZN4SubAD0Ev
Function size: 5
Inlining calls in: _ZN4SubAD0Ev
Function size: 5
Analyzing call of _ZN4BaseD2Ev... (caller:_ZN4SubAD0Ev)
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4SubAD0Ev ----
Computing probabilities for entry
block-frequency: _ZN4SubAD0Ev
=============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubAD0Ev
- entry: float = 1.0, int = 8
NumConstantArgs: 0
NumConstantOffsetPtrArgs: 1
NumAllocaArgs: 0
NumConstantPtrCmps: 0
NumConstantPtrDiffs: 0
NumInstructionsSimplified: 1
NumInstructions: 1
SROACostSavings: 0
SROACostSavingsLost: 0
LoadEliminationCost: 0
ContainsNoDuplicateCall: 0
Cost: -35
Threshold: 337
Inlining (cost=-35, threshold=337), Call: call void @_ZN4BaseD2Ev(%class.Base* nonnull dereferenceable(2) %0) #11
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4BaseD2Ev ----
Computing probabilities for entry
block-frequency: _ZN4BaseD2Ev
=============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4BaseD2Ev
- entry: float = 1.0, int = 8
Size after inlining: 4
Deleting outgoing edge from '_ZN4SubAD0Ev' to '_ZN4BaseD2Ev'
Updated inlining SCC: (_ZN4SubAD0Ev)
Running function passes across an SCC: (_ZN4SubAD0Ev)
SROA function: _ZN4SubAD0Ev
EarlyCSE DCE: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0
Not running SpeculativeExecution because TTI->hasBranchDivergence() is false.
Jump threading on function '_ZN4SubAD0Ev'
INSTCOMBINE ITERATION #1 on _ZN4SubAD0Ev
IC: ADD: ret void
IC: ADD: call void @_ZdlPv(i8* nonnull %0) #11
IC: ADD: %0 = bitcast %class.SubA* %this to i8*
IC: Visiting: %0 = bitcast %class.SubA* %this to i8*
IC: Visiting: call void @_ZdlPv(i8* nonnull %0) #11
IC: Visiting: ret void
Marked as tail call candidate: call void @_ZdlPv(i8* nonnull %0) #11
Calculated Rank[this] = 3
INSTCOMBINE ITERATION #1 on _ZN4SubAD0Ev
IC: ADD: ret void
IC: ADD: tail call void @_ZdlPv(i8* nonnull %0) #11
IC: ADD: %0 = bitcast %class.SubA* %this to i8*
IC: Visiting: %0 = bitcast %class.SubA* %this to i8*
IC: Visiting: tail call void @_ZdlPv(i8* nonnull %0) #11
IC: Visiting: ret void
SROA function: _ZN4SubAD0Ev
Instruction Merger
GVN iteration: 0
SCCP on function '_ZN4SubAD0Ev'
Marking Block Executable: entry
markOverdefined: %class.SubA* %this
Popped off OI-WL: %class.SubA* %this
markOverdefined: %0 = bitcast %class.SubA* %this to i8*
Popped off OI-WL: %0 = bitcast %class.SubA* %this to i8*
Popped off BBWL:
entry:
%0 = bitcast %class.SubA* %this to i8*
tail call void @_ZdlPv(i8* nonnull %0) #11
ret void
RESOLVING UNDEFs
DemandedBits: Root: tail call void @_ZdlPv(i8* nonnull %0) #11
DemandedBits: Root: ret void
DemandedBits: Visiting: %0 = bitcast %class.SubA* %this to i8*
INSTCOMBINE ITERATION #1 on _ZN4SubAD0Ev
IC: ADD: ret void
IC: ADD: tail call void @_ZdlPv(i8* nonnull %0) #11
IC: ADD: %0 = bitcast %class.SubA* %this to i8*
IC: Visiting: %0 = bitcast %class.SubA* %this to i8*
IC: Visiting: tail call void @_ZdlPv(i8* nonnull %0) #11
IC: Visiting: ret void
Jump threading on function '_ZN4SubAD0Ev'
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
mark live: tail call void @_ZdlPv(i8* nonnull %0) #11
mark block live: entry
mark live: ret void
post-dom root child is a return: entry
work live: ret void
work live: tail call void @_ZdlPv(i8* nonnull %0) #11
mark live: %0 = bitcast %class.SubA* %this to i8*
work live: %0 = bitcast %class.SubA* %this to i8*
final dead terminator blocks:
Trying to eliminate MemoryDefs at the end of the function
INSTCOMBINE ITERATION #1 on _ZN4SubAD0Ev
IC: ADD: ret void
IC: ADD: tail call void @_ZdlPv(i8* nonnull %0) #11
IC: ADD: %0 = bitcast %class.SubA* %this to i8*
IC: Visiting: %0 = bitcast %class.SubA* %this to i8*
IC: Visiting: tail call void @_ZdlPv(i8* nonnull %0) #11
IC: Visiting: ret void
Running an SCC pass across the RefSCC: [(_ZN4SubAC2Ev)]
Inlining calls in: _ZN4SubAC2Ev
Function size: 5
Inlining calls in: _ZN4SubAC2Ev
Function size: 5
Analyzing call of _ZN4BaseC2Ev... (caller:_ZN4SubAC2Ev)
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4SubAC2Ev ----
Computing probabilities for entry
block-frequency: _ZN4SubAC2Ev
=============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubAC2Ev
- entry: float = 1.0, int = 8
NumConstantArgs: 0
NumConstantOffsetPtrArgs: 1
NumAllocaArgs: 0
NumConstantPtrCmps: 0
NumConstantPtrDiffs: 0
NumInstructionsSimplified: 2
NumInstructions: 3
SROACostSavings: 0
SROACostSavingsLost: 0
LoadEliminationCost: 0
ContainsNoDuplicateCall: 0
Cost: -30
Threshold: 487
Inlining (cost=-30, threshold=487), Call: call void @_ZN4BaseC2Ev(%class.Base* nonnull dereferenceable(2) %0) #11
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4BaseC2Ev ----
Computing probabilities for entry
block-frequency: _ZN4BaseC2Ev
=============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4BaseC2Ev
- entry: float = 1.0, int = 8
Size after inlining: 6
Deleting outgoing edge from '_ZN4SubAC2Ev' to '_ZN4BaseC2Ev'
Updated inlining SCC: (_ZN4SubAC2Ev)
Running function passes across an SCC: (_ZN4SubAC2Ev)
SROA function: _ZN4SubAC2Ev
Not running SpeculativeExecution because TTI->hasBranchDivergence() is false.
Jump threading on function '_ZN4SubAC2Ev'
LVI Getting block end value %1 = getelementptr inbounds %class.Base, %class.Base* %0, i16 0, i32 0 at 'entry'
PUSH: %1 = getelementptr inbounds %class.Base, %class.Base* %0, i16 0, i32 0 in entry
POP %1 = getelementptr inbounds %class.Base, %class.Base* %0, i16 0, i32 0 in entry = notconstant<i32 (...)*** null>
Result = notconstant<i32 (...)*** null>
LVI Getting block end value %2 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0 at 'entry'
PUSH: %2 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0 in entry
POP %2 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0 in entry = notconstant<i32 (...)*** null>
Result = notconstant<i32 (...)*** null>
INSTCOMBINE ITERATION #1 on _ZN4SubAC2Ev
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %2, align 1, !tbaa !2
IC: ADD: %2 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: ADD: %1 = getelementptr inbounds %class.Base, %class.Base* %0, i16 0, i32 0
IC: ADD: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0
IC: Visiting: %1 = getelementptr inbounds %class.Base, %class.Base* %0, i16 0, i32 0
IC: Old = %1 = getelementptr inbounds %class.Base, %class.Base* %0, i16 0, i32 0
New = <badref> = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: ADD: %1 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: ERASE %2 = getelementptr inbounds %class.Base, %class.Base* %0, i16 0, i32 0
IC: ADD DEFERRED: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0
IC: ERASE %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: %1 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: ERASE store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: ADD DEFERRED: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: ERASE %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: ret void
INSTCOMBINE ITERATION #2 on _ZN4SubAC2Ev
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: ret void
Calculated Rank[this] = 3
INSTCOMBINE ITERATION #1 on _ZN4SubAC2Ev
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: ret void
SROA function: _ZN4SubAC2Ev
Instruction Merger
GVN iteration: 0
SCCP on function '_ZN4SubAC2Ev'
Marking Block Executable: entry
markOverdefined: %class.SubA* %this
Popped off OI-WL: %class.SubA* %this
markOverdefined: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
Popped off OI-WL: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
Popped off BBWL:
entry:
%0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
ret void
RESOLVING UNDEFs
DemandedBits: Root: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
DemandedBits: Root: ret void
DemandedBits: Visiting: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
INSTCOMBINE ITERATION #1 on _ZN4SubAC2Ev
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: ret void
Jump threading on function '_ZN4SubAC2Ev'
LVI Getting block end value %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0 at 'entry'
PUSH: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0 in entry
POP %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0 in entry = notconstant<i32 (...)*** null>
Result = notconstant<i32 (...)*** null>
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
mark live: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
mark block live: entry
mark live: ret void
post-dom root child is a return: entry
work live: ret void
work live: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
mark live: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
work live: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
final dead terminator blocks:
Trying to eliminate MemoryDefs killed by 1 = MemoryDef(liveOnEntry) ( store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2)
trying to get dominating access
visiting 0 = MemoryDef(liveOnEntry)
... found LiveOnEntryDef
finished walk
Trying to eliminate MemoryDefs at the end of the function
INSTCOMBINE ITERATION #1 on _ZN4SubAC2Ev
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: ret void
Deleting outgoing edge from '_ZN4SubAC2Ev' to '_ZN4BaseD0Ev'
Running an SCC pass across the RefSCC: [(_ZN4SubB2fnEv)]
Running function passes across an SCC: (_ZN4SubB2fnEv)
SROA function: _ZN4SubB2fnEv
Not running SpeculativeExecution because TTI->hasBranchDivergence() is false.
Jump threading on function '_ZN4SubB2fnEv'
INSTCOMBINE ITERATION #1 on _ZN4SubB2fnEv
IC: ADD: ret void
IC: Visiting: ret void
Calculated Rank[this] = 3
INSTCOMBINE ITERATION #1 on _ZN4SubB2fnEv
IC: ADD: ret void
IC: Visiting: ret void
SROA function: _ZN4SubB2fnEv
Instruction Merger
GVN iteration: 0
SCCP on function '_ZN4SubB2fnEv'
Marking Block Executable: entry
markOverdefined: %class.SubB* %this
Popped off OI-WL: %class.SubB* %this
Popped off BBWL:
entry:
ret void
RESOLVING UNDEFs
DemandedBits: Root: ret void
INSTCOMBINE ITERATION #1 on _ZN4SubB2fnEv
IC: ADD: ret void
IC: Visiting: ret void
Jump threading on function '_ZN4SubB2fnEv'
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
mark live: ret void
mark block live: entry
post-dom root child is a return: entry
work live: ret void
final dead terminator blocks:
Trying to eliminate MemoryDefs at the end of the function
INSTCOMBINE ITERATION #1 on _ZN4SubB2fnEv
IC: ADD: ret void
IC: Visiting: ret void
Running an SCC pass across the RefSCC: [(_ZN4SubBD0Ev)]
Inlining calls in: _ZN4SubBD0Ev
Function size: 5
Inlining calls in: _ZN4SubBD0Ev
Function size: 5
Analyzing call of _ZN4BaseD2Ev... (caller:_ZN4SubBD0Ev)
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4SubBD0Ev ----
Computing probabilities for entry
block-frequency: _ZN4SubBD0Ev
=============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubBD0Ev
- entry: float = 1.0, int = 8
NumConstantArgs: 0
NumConstantOffsetPtrArgs: 1
NumAllocaArgs: 0
NumConstantPtrCmps: 0
NumConstantPtrDiffs: 0
NumInstructionsSimplified: 1
NumInstructions: 1
SROACostSavings: 0
SROACostSavingsLost: 0
LoadEliminationCost: 0
ContainsNoDuplicateCall: 0
Cost: -35
Threshold: 337
Inlining (cost=-35, threshold=337), Call: call void @_ZN4BaseD2Ev(%class.Base* nonnull dereferenceable(2) %0) #10
Size after inlining: 4
Deleting outgoing edge from '_ZN4SubBD0Ev' to '_ZN4BaseD2Ev'
Updated inlining SCC: (_ZN4SubBD0Ev)
Running function passes across an SCC: (_ZN4SubBD0Ev)
SROA function: _ZN4SubBD0Ev
EarlyCSE DCE: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0
Not running SpeculativeExecution because TTI->hasBranchDivergence() is false.
Jump threading on function '_ZN4SubBD0Ev'
INSTCOMBINE ITERATION #1 on _ZN4SubBD0Ev
IC: ADD: ret void
IC: ADD: call void @_ZdlPv(i8* nonnull %0) #10
IC: ADD: %0 = bitcast %class.SubB* %this to i8*
IC: Visiting: %0 = bitcast %class.SubB* %this to i8*
IC: Visiting: call void @_ZdlPv(i8* nonnull %0) #10
IC: Visiting: ret void
Marked as tail call candidate: call void @_ZdlPv(i8* nonnull %0) #10
Calculated Rank[this] = 3
INSTCOMBINE ITERATION #1 on _ZN4SubBD0Ev
IC: ADD: ret void
IC: ADD: tail call void @_ZdlPv(i8* nonnull %0) #10
IC: ADD: %0 = bitcast %class.SubB* %this to i8*
IC: Visiting: %0 = bitcast %class.SubB* %this to i8*
IC: Visiting: tail call void @_ZdlPv(i8* nonnull %0) #10
IC: Visiting: ret void
SROA function: _ZN4SubBD0Ev
Instruction Merger
GVN iteration: 0
SCCP on function '_ZN4SubBD0Ev'
Marking Block Executable: entry
markOverdefined: %class.SubB* %this
Popped off OI-WL: %class.SubB* %this
markOverdefined: %0 = bitcast %class.SubB* %this to i8*
Popped off OI-WL: %0 = bitcast %class.SubB* %this to i8*
Popped off BBWL:
entry:
%0 = bitcast %class.SubB* %this to i8*
tail call void @_ZdlPv(i8* nonnull %0) #10
ret void
RESOLVING UNDEFs
DemandedBits: Root: tail call void @_ZdlPv(i8* nonnull %0) #10
DemandedBits: Root: ret void
DemandedBits: Visiting: %0 = bitcast %class.SubB* %this to i8*
INSTCOMBINE ITERATION #1 on _ZN4SubBD0Ev
IC: ADD: ret void
IC: ADD: tail call void @_ZdlPv(i8* nonnull %0) #10
IC: ADD: %0 = bitcast %class.SubB* %this to i8*
IC: Visiting: %0 = bitcast %class.SubB* %this to i8*
IC: Visiting: tail call void @_ZdlPv(i8* nonnull %0) #10
IC: Visiting: ret void
Jump threading on function '_ZN4SubBD0Ev'
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
mark live: tail call void @_ZdlPv(i8* nonnull %0) #10
mark block live: entry
mark live: ret void
post-dom root child is a return: entry
work live: ret void
work live: tail call void @_ZdlPv(i8* nonnull %0) #10
mark live: %0 = bitcast %class.SubB* %this to i8*
work live: %0 = bitcast %class.SubB* %this to i8*
final dead terminator blocks:
Trying to eliminate MemoryDefs at the end of the function
INSTCOMBINE ITERATION #1 on _ZN4SubBD0Ev
IC: ADD: ret void
IC: ADD: tail call void @_ZdlPv(i8* nonnull %0) #10
IC: ADD: %0 = bitcast %class.SubB* %this to i8*
IC: Visiting: %0 = bitcast %class.SubB* %this to i8*
IC: Visiting: tail call void @_ZdlPv(i8* nonnull %0) #10
IC: Visiting: ret void
Running an SCC pass across the RefSCC: [(_ZN4SubBC2Ev)]
Inlining calls in: _ZN4SubBC2Ev
Function size: 5
Inlining calls in: _ZN4SubBC2Ev
Function size: 5
Analyzing call of _ZN4BaseC2Ev... (caller:_ZN4SubBC2Ev)
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4SubBC2Ev ----
Computing probabilities for entry
block-frequency: _ZN4SubBC2Ev
=============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubBC2Ev
- entry: float = 1.0, int = 8
NumConstantArgs: 0
NumConstantOffsetPtrArgs: 1
NumAllocaArgs: 0
NumConstantPtrCmps: 0
NumConstantPtrDiffs: 0
NumInstructionsSimplified: 2
NumInstructions: 3
SROACostSavings: 0
SROACostSavingsLost: 0
LoadEliminationCost: 0
ContainsNoDuplicateCall: 0
Cost: -30
Threshold: 487
Inlining (cost=-30, threshold=487), Call: call void @_ZN4BaseC2Ev(%class.Base* nonnull dereferenceable(2) %0) #10
Size after inlining: 6
Deleting outgoing edge from '_ZN4SubBC2Ev' to '_ZN4BaseC2Ev'
Updated inlining SCC: (_ZN4SubBC2Ev)
Running function passes across an SCC: (_ZN4SubBC2Ev)
SROA function: _ZN4SubBC2Ev
Not running SpeculativeExecution because TTI->hasBranchDivergence() is false.
Jump threading on function '_ZN4SubBC2Ev'
LVI Getting block end value %1 = getelementptr inbounds %class.Base, %class.Base* %0, i16 0, i32 0 at 'entry'
PUSH: %1 = getelementptr inbounds %class.Base, %class.Base* %0, i16 0, i32 0 in entry
POP %1 = getelementptr inbounds %class.Base, %class.Base* %0, i16 0, i32 0 in entry = notconstant<i32 (...)*** null>
Result = notconstant<i32 (...)*** null>
LVI Getting block end value %2 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0 at 'entry'
PUSH: %2 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0 in entry
POP %2 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0 in entry = notconstant<i32 (...)*** null>
Result = notconstant<i32 (...)*** null>
INSTCOMBINE ITERATION #1 on _ZN4SubBC2Ev
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %2, align 1, !tbaa !2
IC: ADD: %2 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: ADD: %1 = getelementptr inbounds %class.Base, %class.Base* %0, i16 0, i32 0
IC: ADD: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0
IC: Visiting: %1 = getelementptr inbounds %class.Base, %class.Base* %0, i16 0, i32 0
IC: Old = %1 = getelementptr inbounds %class.Base, %class.Base* %0, i16 0, i32 0
New = <badref> = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: ADD: %1 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: ERASE %2 = getelementptr inbounds %class.Base, %class.Base* %0, i16 0, i32 0
IC: ADD DEFERRED: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0
IC: ERASE %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: %1 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: ERASE store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: ADD DEFERRED: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: ERASE %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: ret void
INSTCOMBINE ITERATION #2 on _ZN4SubBC2Ev
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: ret void
Calculated Rank[this] = 3
INSTCOMBINE ITERATION #1 on _ZN4SubBC2Ev
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: ret void
SROA function: _ZN4SubBC2Ev
Instruction Merger
GVN iteration: 0
SCCP on function '_ZN4SubBC2Ev'
Marking Block Executable: entry
markOverdefined: %class.SubB* %this
Popped off OI-WL: %class.SubB* %this
markOverdefined: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
Popped off OI-WL: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
Popped off BBWL:
entry:
%0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
ret void
RESOLVING UNDEFs
DemandedBits: Root: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
DemandedBits: Root: ret void
DemandedBits: Visiting: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
INSTCOMBINE ITERATION #1 on _ZN4SubBC2Ev
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: ret void
Jump threading on function '_ZN4SubBC2Ev'
LVI Getting block end value %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0 at 'entry'
PUSH: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0 in entry
POP %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0 in entry = notconstant<i32 (...)*** null>
Result = notconstant<i32 (...)*** null>
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
mark live: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
mark block live: entry
mark live: ret void
post-dom root child is a return: entry
work live: ret void
work live: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
mark live: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
work live: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
final dead terminator blocks:
Trying to eliminate MemoryDefs killed by 1 = MemoryDef(liveOnEntry) ( store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2)
trying to get dominating access
visiting 0 = MemoryDef(liveOnEntry)
... found LiveOnEntryDef
finished walk
Trying to eliminate MemoryDefs at the end of the function
INSTCOMBINE ITERATION #1 on _ZN4SubBC2Ev
IC: ADD: ret void
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: Visiting: %0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: ret void
Deleting outgoing edge from '_ZN4SubBC2Ev' to '_ZN4BaseD0Ev'
Running an SCC pass across the RefSCC: [(_Z11testIndCallc)]
Inlining calls in: _Z11testIndCallc
Function size: 26
Inlining calls in: _Z11testIndCallc
Function size: 26
Analyzing call of _ZN4SubAC2Ev... (caller:_Z11testIndCallc)
Looking for trivial roots
Found a new trivial root: %if.end
Last visited node: %if.else
Looking for non-trivial roots
Total: 4, Num: 5
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %if.end
3: %if.then
4: %entry
5: %if.else
Found roots: %if.end
---- Branch Probability Info : _Z11testIndCallc ----
Computing probabilities for if.end
Computing probabilities for if.else
Computing probabilities for if.then
Computing probabilities for entry
eraseBlock entry
set edge entry -> 0 successor probability to 0x30000000 / 0x80000000 = 37.50%
set edge entry -> 1 successor probability to 0x50000000 / 0x80000000 = 62.50%
block-frequency: _Z11testIndCallc
=================================
reverse-post-order-traversal
- 0: entry
- 1: if.then
- 2: if.else
- 3: if.end
loop-detection
compute-mass-in-function
- node: entry
=> [ local ] weight = 805306368, succ = if.else
=> [ local ] weight = 1342177280, succ = if.then
=> mass: ffffffffffffffff
=> assign 9fffffffffffffff (6000000000000000) to if.then
=> assign 6000000000000000 (0000000000000000) to if.else
- node: if.then
=> [ local ] weight = 2147483648, succ = if.end
=> mass: 9fffffffffffffff
=> assign 9fffffffffffffff (0000000000000000) to if.end
- node: if.else
=> [ local ] weight = 2147483648, succ = if.end
=> mass: 6000000000000000
=> assign 6000000000000000 (0000000000000000) to if.end
- node: if.end
=> mass: ffffffffffffffff
float-to-int: min = 0.375, max = 1.0, factor = 21.33333333
- entry: float = 1.0, scaled = 21.33333333, int = 21
- if.then: float = 0.625, scaled = 13.33333333, int = 13
- if.else: float = 0.375, scaled = 8.0, int = 8
- if.end: float = 1.0, scaled = 21.33333333, int = 21
block-frequency-info: _Z11testIndCallc
- entry: float = 1.0, int = 21
- if.then: float = 0.625, int = 13
- if.else: float = 0.375, int = 8
- if.end: float = 1.0, int = 21
NumConstantArgs: 0
NumConstantOffsetPtrArgs: 1
NumAllocaArgs: 0
NumConstantPtrCmps: 0
NumConstantPtrDiffs: 0
NumInstructionsSimplified: 2
NumInstructions: 3
SROACostSavings: 0
SROACostSavingsLost: 0
LoadEliminationCost: 0
ContainsNoDuplicateCall: 0
Cost: -30
Threshold: 487
Inlining (cost=-30, threshold=487), Call: call void @_ZN4SubAC2Ev(%class.SubA* nonnull dereferenceable(2) %0) #11
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4SubAC2Ev ----
Computing probabilities for entry
block-frequency: _ZN4SubAC2Ev
=============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubAC2Ev
- entry: float = 1.0, int = 8
Size after inlining: 27
Analyzing call of _ZN4SubBC2Ev... (caller:_Z11testIndCallc)
NumConstantArgs: 0
NumConstantOffsetPtrArgs: 1
NumAllocaArgs: 0
NumConstantPtrCmps: 0
NumConstantPtrDiffs: 0
NumInstructionsSimplified: 2
NumInstructions: 3
SROACostSavings: 0
SROACostSavingsLost: 0
LoadEliminationCost: 0
ContainsNoDuplicateCall: 0
Cost: -30
Threshold: 487
Inlining (cost=-30, threshold=487), Call: call void @_ZN4SubBC2Ev(%class.SubB* nonnull dereferenceable(2) %3) #11
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4SubBC2Ev ----
Computing probabilities for entry
block-frequency: _ZN4SubBC2Ev
=============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubBC2Ev
- entry: float = 1.0, int = 8
Size after inlining: 28
Deleting outgoing edge from '_Z11testIndCallc' to '_ZN4SubAC2Ev'
Deleting outgoing edge from '_Z11testIndCallc' to '_ZN4SubBC2Ev'
Updated inlining SCC: (_Z11testIndCallc)
Running function passes across an SCC: (_Z11testIndCallc)
SROA function: _Z11testIndCallc
Starting Memory SSA clobber for %vtable = load void (%class.Base*)**, void (%class.Base*)*** %6, align 1, !tbaa !2 is MemoryUse(9) MayAlias
Optimized Memory SSA clobber for %vtable = load void (%class.Base*)**, void (%class.Base*)*** %6, align 1, !tbaa !2 is 9 = MemoryPhi({if.else,6},{if.then,3})
Result Memory SSA clobber [SkipSelf = 0] for %vtable = load void (%class.Base*)**, void (%class.Base*)*** %6, align 1, !tbaa !2 is 9 = MemoryPhi({if.else,6},{if.then,3})
Starting Memory SSA clobber for %7 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1 is MemoryUse(9) MayAlias
Optimized Memory SSA clobber for %7 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1 is 9 = MemoryPhi({if.else,6},{if.then,3})
Result Memory SSA clobber [SkipSelf = 0] for %7 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1 is 9 = MemoryPhi({if.else,6},{if.then,3})
EarlyCSE CVP: Add conditional value for 'tobool.not' as i1 true in if.else
EarlyCSE CVP: Add conditional value for 'tobool.not' as i1 false in if.then
Not running SpeculativeExecution because TTI->hasBranchDivergence() is false.
Jump threading on function '_Z11testIndCallc'
LVI Getting value i8 %sel at ''
Result = overdefined
LVI Getting block end value i8 %sel at 'entry'
PUSH: i8 %sel in entry
POP i8 %sel in entry = overdefined
Result = overdefined
LVI Getting block end value %4 = bitcast i8* %call1 to i16* at 'if.else'
PUSH: %4 = bitcast i8* %call1 to i16* in if.else
POP %4 = bitcast i8* %call1 to i16* in if.else = notconstant<i16* null>
Result = notconstant<i16* null>
LVI Getting block end value %5 = getelementptr inbounds %class.SubB, %class.SubB* %3, i16 0, i32 0, i32 0 at 'if.else'
PUSH: %5 = getelementptr inbounds %class.SubB, %class.SubB* %3, i16 0, i32 0, i32 0 in if.else
POP %5 = getelementptr inbounds %class.SubB, %class.SubB* %3, i16 0, i32 0, i32 0 in if.else = notconstant<i32 (...)*** null>
Result = notconstant<i32 (...)*** null>
LVI Getting edge value %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10 from 'if.then' to 'if.end'
PUSH: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10 in if.then
POP %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10 in if.then = notconstant<i8* null>
Result = notconstant<i8* null>
LVI Getting edge value %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10 from 'if.else' to 'if.end'
PUSH: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10 in if.else
POP %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10 in if.else = notconstant<i8* null>
Result = notconstant<i8* null>
LVI Getting block end value %6 = bitcast i8* %b.0.in to void (%class.Base*)*** at 'if.end'
PUSH: %6 = bitcast i8* %b.0.in to void (%class.Base*)*** in if.end
POP %6 = bitcast i8* %b.0.in to void (%class.Base*)*** in if.end = notconstant<void (%class.Base*)*** null>
Result = notconstant<void (%class.Base*)*** null>
LVI Getting block end value %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2 at 'if.end'
PUSH: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2 in if.end
POP %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2 in if.end = notconstant<void (%class.Base*)** null>
Result = notconstant<void (%class.Base*)** null>
LVI Getting block end value %6 = bitcast i8* %b.0.in to void (%class.Base*)*** at 'if.end'
Result = notconstant<void (%class.Base*)*** null>
LVI Getting block end value %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1 at 'if.end'
PUSH: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1 in if.end
POP %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1 in if.end = notconstant<void (%class.Base*)** null>
Result = notconstant<void (%class.Base*)** null>
LVI Getting block end value %1 = bitcast i8* %call to i16* at 'if.then'
PUSH: %1 = bitcast i8* %call to i16* in if.then
POP %1 = bitcast i8* %call to i16* in if.then = notconstant<i16* null>
Result = notconstant<i16* null>
LVI Getting block end value %2 = getelementptr inbounds %class.SubA, %class.SubA* %0, i16 0, i32 0, i32 0 at 'if.then'
PUSH: %2 = getelementptr inbounds %class.SubA, %class.SubA* %0, i16 0, i32 0, i32 0 in if.then
POP %2 = getelementptr inbounds %class.SubA, %class.SubA* %0, i16 0, i32 0, i32 0 in if.then = notconstant<i32 (...)*** null>
Result = notconstant<i32 (...)*** null>
INSTCOMBINE ITERATION #1 on _Z11testIndCallc
IC: ADD: br label %if.end
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %5, align 1, !tbaa !2
IC: ADD: %5 = getelementptr inbounds %class.SubB, %class.SubB* %3, i16 0, i32 0, i32 0
IC: ADD: store i16 0, i16* %4, align 2
IC: ADD: %4 = bitcast i8* %call1 to i16*
IC: ADD: %3 = bitcast i8* %call1 to %class.SubB*
IC: ADD: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: ADD: ret void
IC: ADD: call void %8(%class.Base* nonnull dereferenceable(2) %b.0) #11
IC: ADD: %8 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: ADD: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: ADD: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %6, align 1, !tbaa !2
IC: ADD: call void %7(%class.Base* nonnull dereferenceable(2) %b.0)
IC: ADD: %7 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: ADD: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
IC: ADD: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %6, align 1, !tbaa !2
IC: ADD: %6 = bitcast i8* %b.0.in to void (%class.Base*)***
IC: ADD: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: ADD: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
IC: ADD: br label %if.end
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %2, align 1, !tbaa !2
IC: ADD: %2 = getelementptr inbounds %class.SubA, %class.SubA* %0, i16 0, i32 0, i32 0
IC: ADD: store i16 0, i16* %1, align 2
IC: ADD: %1 = bitcast i8* %call to i16*
IC: ADD: %0 = bitcast i8* %call to %class.SubA*
IC: ADD: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: ADD: br i1 %tobool.not, label %if.else, label %if.then
IC: ADD: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: br i1 %tobool.not, label %if.else, label %if.then
IC: Visiting: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: Visiting: %0 = bitcast i8* %call to %class.SubA*
IC: Visiting: %1 = bitcast i8* %call to i16*
IC: Visiting: store i16 0, i16* %1, align 2
IC: Visiting: %2 = getelementptr inbounds %class.SubA, %class.SubA* %0, i16 0, i32 0, i32 0
IC: Old = %2 = getelementptr inbounds %class.SubA, %class.SubA* %0, i16 0, i32 0, i32 0
New = <badref> = bitcast i8* %call to i32 (...)***
IC: ADD: %2 = bitcast i8* %call to i32 (...)***
IC: ERASE %3 = getelementptr inbounds %class.SubA, %class.SubA* %0, i16 0, i32 0, i32 0
IC: ADD DEFERRED: %0 = bitcast i8* %call to %class.SubA*
IC: ERASE %0 = bitcast i8* %call to %class.SubA*
IC: ADD DEFERRED: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: ADD: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: Visiting: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: Visiting: %1 = bitcast i8* %call to i32 (...)***
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: Visiting: br label %if.end
IC: Visiting: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
IC: Visiting: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: Visiting: %5 = bitcast i8* %b.0.in to void (%class.Base*)***
IC: Visiting: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %5, align 1, !tbaa !2
IC: Visiting: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
IC: Visiting: %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: Visiting: call void %6(%class.Base* nonnull dereferenceable(2) %b.0)
IC: Visiting: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %5, align 1, !tbaa !2
IC: Visiting: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: Visiting: %7 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: Visiting: call void %7(%class.Base* nonnull dereferenceable(2) %b.0) #11
IC: Visiting: ret void
IC: Visiting: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: Visiting: %2 = bitcast i8* %call1 to %class.SubB*
IC: Visiting: %3 = bitcast i8* %call1 to i16*
IC: Visiting: store i16 0, i16* %3, align 2
IC: Visiting: %4 = getelementptr inbounds %class.SubB, %class.SubB* %2, i16 0, i32 0, i32 0
IC: Old = %4 = getelementptr inbounds %class.SubB, %class.SubB* %2, i16 0, i32 0, i32 0
New = <badref> = bitcast i8* %call1 to i32 (...)***
IC: ADD: %4 = bitcast i8* %call1 to i32 (...)***
IC: ERASE %5 = getelementptr inbounds %class.SubB, %class.SubB* %2, i16 0, i32 0, i32 0
IC: ADD DEFERRED: %2 = bitcast i8* %call1 to %class.SubB*
IC: ERASE %2 = bitcast i8* %call1 to %class.SubB*
IC: ADD DEFERRED: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: ADD: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: Visiting: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: Visiting: %3 = bitcast i8* %call1 to i32 (...)***
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %3, align 1, !tbaa !2
IC: Visiting: br label %if.end
INSTCOMBINE ITERATION #2 on _Z11testIndCallc
IC: ADD: br label %if.end
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %3, align 1, !tbaa !2
IC: ADD: %3 = bitcast i8* %call1 to i32 (...)***
IC: ADD: store i16 0, i16* %2, align 2
IC: ADD: %2 = bitcast i8* %call1 to i16*
IC: ADD: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: ADD: ret void
IC: ADD: call void %6(%class.Base* nonnull dereferenceable(2) %b.0) #11
IC: ADD: %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: ADD: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: ADD: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: ADD: call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
IC: ADD: %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: ADD: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
IC: ADD: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: ADD: %4 = bitcast i8* %b.0.in to void (%class.Base*)***
IC: ADD: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: ADD: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
IC: ADD: br label %if.end
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: ADD: %1 = bitcast i8* %call to i32 (...)***
IC: ADD: store i16 0, i16* %0, align 2
IC: ADD: %0 = bitcast i8* %call to i16*
IC: ADD: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: ADD: br i1 %tobool.not, label %if.else, label %if.then
IC: ADD: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: br i1 %tobool.not, label %if.else, label %if.then
IC: Visiting: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: Visiting: %0 = bitcast i8* %call to i16*
IC: Visiting: store i16 0, i16* %0, align 2
IC: Visiting: %1 = bitcast i8* %call to i32 (...)***
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: Visiting: br label %if.end
IC: Visiting: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
IC: Visiting: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: Visiting: %4 = bitcast i8* %b.0.in to void (%class.Base*)***
IC: Visiting: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: Visiting: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
IC: Visiting: %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: Visiting: call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
IC: Visiting: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: Visiting: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: Visiting: %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: Visiting: call void %6(%class.Base* nonnull dereferenceable(2) %b.0) #11
IC: Visiting: ret void
IC: Visiting: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: Visiting: %2 = bitcast i8* %call1 to i16*
IC: Visiting: store i16 0, i16* %2, align 2
IC: Visiting: %3 = bitcast i8* %call1 to i32 (...)***
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %3, align 1, !tbaa !2
IC: Visiting: br label %if.end
Marked as tail call candidate: %call = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
Marked as tail call candidate: call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
Marked as tail call candidate: call void %6(%class.Base* nonnull dereferenceable(2) %b.0) #11
Marked as tail call candidate: %call1 = call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
Calculated Rank[sel] = 3
INSTCOMBINE ITERATION #1 on _Z11testIndCallc
IC: ADD: br label %if.end
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %3, align 1, !tbaa !2
IC: ADD: %3 = bitcast i8* %call1 to i32 (...)***
IC: ADD: store i16 0, i16* %2, align 2
IC: ADD: %2 = bitcast i8* %call1 to i16*
IC: ADD: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: ADD: ret void
IC: ADD: tail call void %6(%class.Base* nonnull dereferenceable(2) %b.0) #11
IC: ADD: %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: ADD: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: ADD: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: ADD: tail call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
IC: ADD: %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: ADD: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
IC: ADD: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: ADD: %4 = bitcast i8* %b.0.in to void (%class.Base*)***
IC: ADD: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: ADD: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
IC: ADD: br label %if.end
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: ADD: %1 = bitcast i8* %call to i32 (...)***
IC: ADD: store i16 0, i16* %0, align 2
IC: ADD: %0 = bitcast i8* %call to i16*
IC: ADD: %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: ADD: br i1 %tobool.not, label %if.else, label %if.then
IC: ADD: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: br i1 %tobool.not, label %if.else, label %if.then
IC: Visiting: %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: Visiting: %0 = bitcast i8* %call to i16*
IC: Visiting: store i16 0, i16* %0, align 2
IC: Visiting: %1 = bitcast i8* %call to i32 (...)***
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: Visiting: br label %if.end
IC: Visiting: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
IC: Visiting: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: Visiting: %4 = bitcast i8* %b.0.in to void (%class.Base*)***
IC: Visiting: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: Visiting: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
IC: Visiting: %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: Visiting: tail call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
IC: Visiting: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: Visiting: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: Visiting: %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: Visiting: tail call void %6(%class.Base* nonnull dereferenceable(2) %b.0) #11
IC: Visiting: ret void
IC: Visiting: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: Visiting: %2 = bitcast i8* %call1 to i16*
IC: Visiting: store i16 0, i16* %2, align 2
IC: Visiting: %3 = bitcast i8* %call1 to i32 (...)***
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %3, align 1, !tbaa !2
IC: Visiting: br label %if.end
SROA function: _Z11testIndCallc
Instruction Merger
can Sink? : store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %3, align 1, !tbaa !2
can Sink? : store i16 0, i16* %2, align 2
GVN iteration: 0
GVN: load void (%class.Base*)** %vtable2 is clobbered by tail call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
GVN: load void (%class.Base*)* %6 is clobbered by tail call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
SCCP on function '_Z11testIndCallc'
Marking Block Executable: entry
markOverdefined: i8 %sel
Popped off OI-WL: i8 %sel
markOverdefined: %tobool.not = icmp eq i8 %sel, 0
Popped off OI-WL: %tobool.not = icmp eq i8 %sel, 0
Marking Block Executable: if.else
Marking Block Executable: if.then
Popped off BBWL:
if.then: ; preds = %entry
%call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
%0 = bitcast i8* %call to i16*
store i16 0, i16* %0, align 2
%1 = bitcast i8* %call to i32 (...)***
store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
br label %if.end
Merged overdefined into %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10 : overdefined
markOverdefined: %0 = bitcast i8* %call to i16*
markOverdefined: %1 = bitcast i8* %call to i32 (...)***
Marking Block Executable: if.end
Popped off BBWL:
if.end: ; preds = %if.else, %if.then
%b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
%b.0 = bitcast i8* %b.0.in to %class.Base*
%4 = bitcast i8* %b.0.in to void (%class.Base*)***
%vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
%vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
%5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
tail call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
%vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
%vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
%6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
tail call void %6(%class.Base* nonnull dereferenceable(2) %b.0) #11
ret void
Merged overdefined into %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ] : overdefined
markOverdefined: %b.0 = bitcast i8* %b.0.in to %class.Base*
markOverdefined: %4 = bitcast i8* %b.0.in to void (%class.Base*)***
Merged overdefined into %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2 : overdefined
markOverdefined: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
Merged overdefined into %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1 : overdefined
Merged overdefined into %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2 : overdefined
markOverdefined: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
Merged overdefined into %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1 : overdefined
Popped off BBWL:
if.else: ; preds = %entry
%call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
%2 = bitcast i8* %call1 to i16*
store i16 0, i16* %2, align 2
%3 = bitcast i8* %call1 to i32 (...)***
store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %3, align 1, !tbaa !2
br label %if.end
Merged overdefined into %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10 : overdefined
markOverdefined: %2 = bitcast i8* %call1 to i16*
markOverdefined: %3 = bitcast i8* %call1 to i32 (...)***
Marking Edge Executable: if.else -> if.end
Popped off BBWL:
entry:
%tobool.not = icmp eq i8 %sel, 0
br i1 %tobool.not, label %if.else, label %if.then
Popped off OI-WL: %3 = bitcast i8* %call1 to i32 (...)***
Popped off OI-WL: %2 = bitcast i8* %call1 to i16*
Popped off OI-WL: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
Popped off OI-WL: %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
Popped off OI-WL: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
Popped off OI-WL: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
Popped off OI-WL: %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
Popped off OI-WL: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
Popped off OI-WL: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
Popped off OI-WL: %4 = bitcast i8* %b.0.in to void (%class.Base*)***
Popped off OI-WL: %b.0 = bitcast i8* %b.0.in to %class.Base*
Popped off OI-WL: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
Popped off OI-WL: %1 = bitcast i8* %call to i32 (...)***
Popped off OI-WL: %0 = bitcast i8* %call to i16*
Popped off OI-WL: %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
RESOLVING UNDEFs
DemandedBits: Root: br i1 %tobool.not, label %if.else, label %if.then
DemandedBits: Root: %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
DemandedBits: Root: store i16 0, i16* %0, align 2
DemandedBits: Root: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
DemandedBits: Root: br label %if.end
DemandedBits: Root: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
DemandedBits: Root: store i16 0, i16* %2, align 2
DemandedBits: Root: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %3, align 1, !tbaa !2
DemandedBits: Root: br label %if.end
DemandedBits: Root: tail call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
DemandedBits: Root: tail call void %6(%class.Base* nonnull dereferenceable(2) %b.0) #11
DemandedBits: Root: ret void
DemandedBits: Visiting: %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
DemandedBits: Visiting: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
DemandedBits: Visiting: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
DemandedBits: Visiting: %4 = bitcast i8* %b.0.in to void (%class.Base*)***
DemandedBits: Visiting: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
DemandedBits: Visiting: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
DemandedBits: Visiting: %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
DemandedBits: Visiting: %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
DemandedBits: Visiting: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
DemandedBits: Visiting: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
DemandedBits: Visiting: %b.0 = bitcast i8* %b.0.in to %class.Base*
DemandedBits: Visiting: %3 = bitcast i8* %call1 to i32 (...)***
DemandedBits: Visiting: %2 = bitcast i8* %call1 to i16*
DemandedBits: Visiting: %1 = bitcast i8* %call to i32 (...)***
DemandedBits: Visiting: %0 = bitcast i8* %call to i16*
DemandedBits: Visiting: %tobool.not = icmp eq i8 %sel, 0 Alive Out: 0x1
INSTCOMBINE ITERATION #1 on _Z11testIndCallc
IC: ADD: br label %if.end
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %3, align 1, !tbaa !2
IC: ADD: %3 = bitcast i8* %call1 to i32 (...)***
IC: ADD: store i16 0, i16* %2, align 2
IC: ADD: %2 = bitcast i8* %call1 to i16*
IC: ADD: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: ADD: ret void
IC: ADD: tail call void %6(%class.Base* nonnull dereferenceable(2) %b.0) #11
IC: ADD: %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: ADD: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: ADD: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: ADD: tail call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
IC: ADD: %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: ADD: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
IC: ADD: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: ADD: %4 = bitcast i8* %b.0.in to void (%class.Base*)***
IC: ADD: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: ADD: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
IC: ADD: br label %if.end
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: ADD: %1 = bitcast i8* %call to i32 (...)***
IC: ADD: store i16 0, i16* %0, align 2
IC: ADD: %0 = bitcast i8* %call to i16*
IC: ADD: %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: ADD: br i1 %tobool.not, label %if.else, label %if.then
IC: ADD: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: br i1 %tobool.not, label %if.else, label %if.then
IC: Visiting: %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: Visiting: %0 = bitcast i8* %call to i16*
IC: Visiting: store i16 0, i16* %0, align 2
IC: Visiting: %1 = bitcast i8* %call to i32 (...)***
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: Visiting: br label %if.end
IC: Visiting: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
IC: Visiting: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: Visiting: %4 = bitcast i8* %b.0.in to void (%class.Base*)***
IC: Visiting: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: Visiting: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
IC: Visiting: %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: Visiting: tail call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
IC: Visiting: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
IC: Visiting: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: Visiting: %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: Visiting: tail call void %6(%class.Base* nonnull dereferenceable(2) %b.0) #11
IC: Visiting: ret void
IC: Visiting: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: Visiting: %2 = bitcast i8* %call1 to i16*
IC: Visiting: store i16 0, i16* %2, align 2
IC: Visiting: %3 = bitcast i8* %call1 to i32 (...)***
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %3, align 1, !tbaa !2
IC: Visiting: br label %if.end
Jump threading on function '_Z11testIndCallc'
LVI Getting value i8 %sel at ''
Result = overdefined
LVI Getting block end value i8 %sel at 'entry'
PUSH: i8 %sel in entry
POP i8 %sel in entry = overdefined
Result = overdefined
LVI Getting block end value %2 = bitcast i8* %call1 to i16* at 'if.else'
PUSH: %2 = bitcast i8* %call1 to i16* in if.else
POP %2 = bitcast i8* %call1 to i16* in if.else = notconstant<i16* null>
Result = notconstant<i16* null>
LVI Getting block end value %3 = bitcast i8* %call1 to i32 (...)*** at 'if.else'
PUSH: %3 = bitcast i8* %call1 to i32 (...)*** in if.else
POP %3 = bitcast i8* %call1 to i32 (...)*** in if.else = notconstant<i32 (...)*** null>
Result = notconstant<i32 (...)*** null>
LVI Getting edge value %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10 from 'if.then' to 'if.end'
PUSH: %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10 in if.then
POP %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10 in if.then = notconstant<i8* null>
Result = notconstant<i8* null>
LVI Getting edge value %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10 from 'if.else' to 'if.end'
PUSH: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10 in if.else
POP %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10 in if.else = notconstant<i8* null>
Result = notconstant<i8* null>
LVI Getting block end value %4 = bitcast i8* %b.0.in to void (%class.Base*)*** at 'if.end'
PUSH: %4 = bitcast i8* %b.0.in to void (%class.Base*)*** in if.end
POP %4 = bitcast i8* %b.0.in to void (%class.Base*)*** in if.end = notconstant<void (%class.Base*)*** null>
Result = notconstant<void (%class.Base*)*** null>
LVI Getting block end value %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2 at 'if.end'
PUSH: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2 in if.end
POP %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2 in if.end = notconstant<void (%class.Base*)** null>
Result = notconstant<void (%class.Base*)** null>
LVI Getting block end value %4 = bitcast i8* %b.0.in to void (%class.Base*)*** at 'if.end'
Result = notconstant<void (%class.Base*)*** null>
LVI Getting block end value %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1 at 'if.end'
PUSH: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1 in if.end
POP %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1 in if.end = notconstant<void (%class.Base*)** null>
Result = notconstant<void (%class.Base*)** null>
LVI Getting block end value %0 = bitcast i8* %call to i16* at 'if.then'
PUSH: %0 = bitcast i8* %call to i16* in if.then
POP %0 = bitcast i8* %call to i16* in if.then = notconstant<i16* null>
Result = notconstant<i16* null>
LVI Getting block end value %1 = bitcast i8* %call to i32 (...)*** at 'if.then'
PUSH: %1 = bitcast i8* %call to i32 (...)*** in if.then
POP %1 = bitcast i8* %call to i32 (...)*** in if.then = notconstant<i32 (...)*** null>
Result = notconstant<i32 (...)*** null>
Looking for trivial roots
Found a new trivial root: %if.end
Last visited node: %if.else
Looking for non-trivial roots
Total: 4, Num: 5
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %if.end
3: %if.then
4: %entry
5: %if.else
Found roots: %if.end
mark live: %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
mark block live: if.then
mark live: br label %if.end
mark live: store i16 0, i16* %0, align 2
mark live: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
mark live: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
mark block live: if.else
mark live: br label %if.end
mark live: store i16 0, i16* %2, align 2
mark live: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %3, align 1, !tbaa !2
mark live: tail call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
mark block live: if.end
mark live: tail call void %6(%class.Base* nonnull dereferenceable(2) %b.0) #11
mark live: ret void
post-dom root child is a return: if.end
work live: ret void
work live: tail call void %6(%class.Base* nonnull dereferenceable(2) %b.0) #11
mark live: %b.0 = bitcast i8* %b.0.in to %class.Base*
mark live: %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
work live: %6 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
mark live: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
work live: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
mark live: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
work live: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
mark live: %4 = bitcast i8* %b.0.in to void (%class.Base*)***
work live: %4 = bitcast i8* %b.0.in to void (%class.Base*)***
mark live: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
work live: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
work live: %b.0 = bitcast i8* %b.0.in to %class.Base*
work live: tail call void %5(%class.Base* nonnull dereferenceable(2) %b.0)
mark live: %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
work live: %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
mark live: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
work live: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
mark live: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
work live: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2
work live: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %3, align 1, !tbaa !2
mark live: %3 = bitcast i8* %call1 to i32 (...)***
work live: %3 = bitcast i8* %call1 to i32 (...)***
work live: store i16 0, i16* %2, align 2
mark live: %2 = bitcast i8* %call1 to i16*
work live: %2 = bitcast i8* %call1 to i16*
work live: br label %if.end
work live: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
work live: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
mark live: %1 = bitcast i8* %call to i32 (...)***
work live: %1 = bitcast i8* %call to i32 (...)***
work live: store i16 0, i16* %0, align 2
mark live: %0 = bitcast i8* %call to i16*
work live: %0 = bitcast i8* %call to i16*
work live: br label %if.end
work live: %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
new live blocks:
if.then
if.else
if.end
dead terminator blocks:
entry
live control in: entry
mark live: br i1 %tobool.not, label %if.else, label %if.then
work live: br i1 %tobool.not, label %if.else, label %if.then
mark live: %tobool.not = icmp eq i8 %sel, 0
work live: %tobool.not = icmp eq i8 %sel, 0
final dead terminator blocks:
Starting Memory SSA clobber for %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2 is MemoryUse(9) MayAlias
Optimized Memory SSA clobber for %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2 is 9 = MemoryPhi({if.else,6},{if.then,3})
Result Memory SSA clobber [SkipSelf = 0] for %vtable = load void (%class.Base*)**, void (%class.Base*)*** %4, align 1, !tbaa !2 is 9 = MemoryPhi({if.else,6},{if.then,3})
Starting Memory SSA clobber for %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1 is MemoryUse(9) MayAlias
Optimized Memory SSA clobber for %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1 is 9 = MemoryPhi({if.else,6},{if.then,3})
Result Memory SSA clobber [SkipSelf = 0] for %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1 is 9 = MemoryPhi({if.else,6},{if.then,3})
Trying to eliminate MemoryDefs killed by 5 = MemoryDef(4) ( store i16 0, i16* %2, align 2)
trying to get dominating access
visiting 4 = MemoryDef(liveOnEntry) ( %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10)
... skip, barrier
finished walk
Trying to eliminate MemoryDefs killed by 6 = MemoryDef(5) ( store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %3, align 1, !tbaa !2)
trying to get dominating access
visiting 5 = MemoryDef(4) ( store i16 0, i16* %2, align 2)
Checking for reads of 5 = MemoryDef(4) ( store i16 0, i16* %2, align 2)
6 = MemoryDef(5) ( store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %3, align 1, !tbaa !2)
... skipping killing def/dom access
Checking if we can kill 5 = MemoryDef(4) ( store i16 0, i16* %2, align 2)
DSE: Remove Dead Store:
DEAD: store i16 0, i16* %2, align 2
KILLER: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %3, align 1, !tbaa !2
trying to get dominating access
visiting 4 = MemoryDef(liveOnEntry) ( %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10)
... skip, barrier
finished walk
Trying to eliminate MemoryDefs killed by 2 = MemoryDef(1) ( store i16 0, i16* %0, align 2)
trying to get dominating access
visiting 1 = MemoryDef(liveOnEntry) ( %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10)
... skip, barrier
finished walk
Trying to eliminate MemoryDefs killed by 3 = MemoryDef(2) ( store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2)
trying to get dominating access
visiting 2 = MemoryDef(1) ( store i16 0, i16* %0, align 2)
Checking for reads of 2 = MemoryDef(1) ( store i16 0, i16* %0, align 2)
3 = MemoryDef(2) ( store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2)
... skipping killing def/dom access
Checking if we can kill 2 = MemoryDef(1) ( store i16 0, i16* %0, align 2)
DSE: Remove Dead Store:
DEAD: store i16 0, i16* %0, align 2
KILLER: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
trying to get dominating access
visiting 1 = MemoryDef(liveOnEntry) ( %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10)
... skip, barrier
finished walk
Trying to eliminate MemoryDefs at the end of the function
INSTCOMBINE ITERATION #1 on _Z11testIndCallc
IC: ADD: br label %if.end
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: ADD: %1 = bitcast i8* %call1 to i32 (...)***
IC: ADD: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: ADD: ret void
IC: ADD: tail call void %4(%class.Base* nonnull dereferenceable(2) %b.0) #11
IC: ADD: %4 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: ADD: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: ADD: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %2, align 1, !tbaa !2
IC: ADD: tail call void %3(%class.Base* nonnull dereferenceable(2) %b.0)
IC: ADD: %3 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: ADD: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
IC: ADD: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %2, align 1, !tbaa !2
IC: ADD: %2 = bitcast i8* %b.0.in to void (%class.Base*)***
IC: ADD: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: ADD: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
IC: ADD: br label %if.end
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %0 = bitcast i8* %call to i32 (...)***
IC: ADD: %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: ADD: br i1 %tobool.not, label %if.else, label %if.then
IC: ADD: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: br i1 %tobool.not, label %if.else, label %if.then
IC: Visiting: %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: Visiting: %0 = bitcast i8* %call to i32 (...)***
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: br label %if.end
IC: Visiting: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
IC: Visiting: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: Visiting: %2 = bitcast i8* %b.0.in to void (%class.Base*)***
IC: Visiting: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %2, align 1, !tbaa !2
IC: Visiting: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
IC: Visiting: %3 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: Visiting: tail call void %3(%class.Base* nonnull dereferenceable(2) %b.0)
IC: Visiting: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %2, align 1, !tbaa !2
IC: Visiting: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: Visiting: %4 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: Visiting: tail call void %4(%class.Base* nonnull dereferenceable(2) %b.0) #11
IC: Visiting: ret void
IC: Visiting: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #10
IC: Visiting: %1 = bitcast i8* %call1 to i32 (...)***
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: Visiting: br label %if.end
GLOBAL DEAD: ; Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly
declare void @llvm.memset.p0i8.i16(i8* nocapture writeonly, i8, i16, i1 immarg) #2
GLOBAL DEAD: ; Function Attrs: inlinehint nounwind willreturn
define linkonce_odr dso_local void @_ZN4SubAC2Ev(%class.SubA* nonnull dereferenceable(2) %this) unnamed_addr #2 comdat align 2 {
entry:
%0 = getelementptr inbounds %class.SubA, %class.SubA* %this, i16 0, i32 0, i32 0
store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
ret void
}
GLOBAL DEAD: ; Function Attrs: inlinehint nounwind willreturn
define linkonce_odr dso_local void @_ZN4SubBC2Ev(%class.SubB* nonnull dereferenceable(2) %this) unnamed_addr #2 comdat align 2 {
entry:
%0 = getelementptr inbounds %class.SubB, %class.SubB* %this, i16 0, i32 0, i32 0
store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
ret void
}
GLOBAL DEAD: ; Function Attrs: inlinehint nounwind willreturn
define linkonce_odr dso_local void @_ZN4BaseC2Ev(%class.Base* nonnull dereferenceable(2) %this) unnamed_addr #2 comdat align 2 {
entry:
%0 = getelementptr inbounds %class.Base, %class.Base* %this, i16 0, i32 0
store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4Base, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
ret void
}
GLOBAL DEAD: @_ZTV4Base = linkonce_odr dso_local unnamed_addr constant { [5 x i8*] } { [5 x i8*] [i8* null, i8* bitcast ({ i8*, i8* }* @_ZTI4Base to i8*), i8* bitcast (void (%class.Base*)* @_ZN4BaseD2Ev to i8*), i8* bitcast (void (%class.Base*)* @_ZN4BaseD0Ev to i8*), i8* bitcast (void ()* @__cxa_pure_virtual to i8*)] }, comdat, align 1
GLOBAL DEAD: declare dso_local void @__cxa_pure_virtual() unnamed_addr
GLOBAL DEAD: ; Function Attrs: nounwind
define linkonce_odr dso_local void @_ZN4BaseD0Ev(%class.Base* nonnull dereferenceable(2) %this) unnamed_addr #4 comdat align 2 {
entry:
tail call void @llvm.trap() #8
unreachable
}
GLOBAL DEAD: ; Function Attrs: cold noreturn nounwind
declare void @llvm.trap() #4
F2I: Looking at function _Z11testIndCallc
Looking for trivial roots
Found a new trivial root: %if.end
Last visited node: %if.else
Looking for non-trivial roots
Total: 4, Num: 5
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %if.end
3: %if.then
4: %entry
5: %if.else
Found roots: %if.end
---- Branch Probability Info : _Z11testIndCallc ----
Computing probabilities for if.end
Computing probabilities for if.else
Computing probabilities for if.then
Computing probabilities for entry
eraseBlock entry
set edge entry -> 0 successor probability to 0x30000000 / 0x80000000 = 37.50%
set edge entry -> 1 successor probability to 0x50000000 / 0x80000000 = 62.50%
block-frequency: _Z11testIndCallc
=================================
reverse-post-order-traversal
- 0: entry
- 1: if.then
- 2: if.else
- 3: if.end
loop-detection
compute-mass-in-function
- node: entry
=> [ local ] weight = 805306368, succ = if.else
=> [ local ] weight = 1342177280, succ = if.then
=> mass: ffffffffffffffff
=> assign 9fffffffffffffff (6000000000000000) to if.then
=> assign 6000000000000000 (0000000000000000) to if.else
- node: if.then
=> [ local ] weight = 2147483648, succ = if.end
=> mass: 9fffffffffffffff
=> assign 9fffffffffffffff (0000000000000000) to if.end
- node: if.else
=> [ local ] weight = 2147483648, succ = if.end
=> mass: 6000000000000000
=> assign 6000000000000000 (0000000000000000) to if.end
- node: if.end
=> mass: ffffffffffffffff
float-to-int: min = 0.375, max = 1.0, factor = 21.33333333
- entry: float = 1.0, scaled = 21.33333333, int = 21
- if.then: float = 0.625, scaled = 13.33333333, int = 13
- if.else: float = 0.375, scaled = 8.0, int = 8
- if.end: float = 1.0, scaled = 21.33333333, int = 21
block-frequency-info: _Z11testIndCallc
- entry: float = 1.0, int = 21
- if.then: float = 0.625, int = 13
- if.else: float = 0.375, int = 8
- if.end: float = 1.0, int = 21
Starting Memory SSA clobber for %vtable = load void (%class.Base*)**, void (%class.Base*)*** %2, align 1, !tbaa !2 is MemoryUse(7) MayAlias
Optimized Memory SSA clobber for %vtable = load void (%class.Base*)**, void (%class.Base*)*** %2, align 1, !tbaa !2 is 7 = MemoryPhi({if.else,4},{if.then,2})
Result Memory SSA clobber [SkipSelf = 0] for %vtable = load void (%class.Base*)**, void (%class.Base*)*** %2, align 1, !tbaa !2 is 7 = MemoryPhi({if.else,4},{if.then,2})
Starting Memory SSA clobber for %3 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1 is MemoryUse(7) MayAlias
Optimized Memory SSA clobber for %3 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1 is 7 = MemoryPhi({if.else,4},{if.then,2})
Result Memory SSA clobber [SkipSelf = 0] for %3 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1 is 7 = MemoryPhi({if.else,4},{if.then,2})
INSTCOMBINE ITERATION #1 on _Z11testIndCallc
IC: ADD: br label %if.end
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: ADD: %1 = bitcast i8* %call1 to i32 (...)***
IC: ADD: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6
IC: ADD: ret void
IC: ADD: tail call void %4(%class.Base* nonnull dereferenceable(2) %b.0) #7
IC: ADD: %4 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: ADD: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: ADD: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %2, align 1, !tbaa !2
IC: ADD: tail call void %3(%class.Base* nonnull dereferenceable(2) %b.0)
IC: ADD: %3 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: ADD: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
IC: ADD: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %2, align 1, !tbaa !2
IC: ADD: %2 = bitcast i8* %b.0.in to void (%class.Base*)***
IC: ADD: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: ADD: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
IC: ADD: br label %if.end
IC: ADD: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %0 = bitcast i8* %call to i32 (...)***
IC: ADD: %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6
IC: ADD: br i1 %tobool.not, label %if.else, label %if.then
IC: ADD: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: br i1 %tobool.not, label %if.else, label %if.then
IC: Visiting: %call = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6
IC: Visiting: %0 = bitcast i8* %call to i32 (...)***
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: br label %if.end
IC: Visiting: %b.0.in = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
IC: Visiting: %b.0 = bitcast i8* %b.0.in to %class.Base*
IC: Visiting: %2 = bitcast i8* %b.0.in to void (%class.Base*)***
IC: Visiting: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %2, align 1, !tbaa !2
IC: Visiting: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
IC: Visiting: %3 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: Visiting: tail call void %3(%class.Base* nonnull dereferenceable(2) %b.0)
IC: Visiting: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %2, align 1, !tbaa !2
IC: Visiting: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: Visiting: %4 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: Visiting: tail call void %4(%class.Base* nonnull dereferenceable(2) %b.0) #7
IC: Visiting: ret void
IC: Visiting: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6
IC: Visiting: %1 = bitcast i8* %call1 to i32 (...)***
IC: Visiting: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %1, align 1, !tbaa !2
IC: Visiting: br label %if.end
SINK: instruction can be sunk: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
SINK: Sink: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)*** %0, align 1, !tbaa !2
SINK: #phid values: 2
FOUND IF CONDITION! %tobool.not = icmp eq i8 %sel, 0 T: if.else F: if.then
Removing BB:
if.then: ; No predecessors!
br label %if.end
Removing BB:
if.else: ; No predecessors!
br label %if.end
Merging: if.end into entry
SLP: Analyzing blocks in _Z11testIndCallc.
SLP: Found stores for 1 underlying objects.
SLP: Trying to vectorize a list of length = 2.
INSTCOMBINE ITERATION #1 on _Z11testIndCallc
IC: ADD: ret void
IC: ADD: tail call void %3(%class.Base* nonnull dereferenceable(2) %b.0) #7
IC: ADD: %3 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: ADD: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: ADD: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %1, align 1, !tbaa !2
IC: ADD: tail call void %2(%class.Base* nonnull dereferenceable(2) %b.0)
IC: ADD: %2 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: ADD: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i16 2
IC: ADD: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %1, align 1, !tbaa !2
IC: ADD: %1 = bitcast i8* %call1 to void (%class.Base*)***
IC: ADD: %b.0 = bitcast i8* %call1 to %class.Base*
IC: ADD: store i32 (...)** %.sink, i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %.sink = select i1 %tobool.not, i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**)
IC: ADD: %0 = bitcast i8* %call1 to i32 (...)***
IC: ADD: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6
IC: ADD: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6
IC: Visiting: %0 = bitcast i8* %call1 to i32 (...)***
IC: Visiting: %.sink = select i1 %tobool.not, i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**)
IC: Visiting: store i32 (...)** %.sink, i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: %b.0 = bitcast i8* %call1 to %class.Base*
IC: Visiting: %1 = bitcast i8* %call1 to void (%class.Base*)***
IC: Visiting: %vtable = load void (%class.Base*)**, void (%class.Base*)*** %1, align 1, !tbaa !2
IC: ADD DEFERRED: %vtable.cast = bitcast i32 (...)** %.sink to void (%class.Base*)**
IC: Replacing %vtable = load void (%class.Base*)**, void (%class.Base*)*** %1, align 1, !tbaa !2
with %vtable.cast = bitcast i32 (...)** %.sink to void (%class.Base*)**
IC: Mod = %vtable = load void (%class.Base*)**, void (%class.Base*)*** %1, align 1, !tbaa !2
New = %vtable = load void (%class.Base*)**, void (%class.Base*)*** %1, align 1, !tbaa !2
IC: ERASE %vtable = load void (%class.Base*)**, void (%class.Base*)*** %1, align 1, !tbaa !2
IC: ADD DEFERRED: %1 = bitcast i8* %call1 to void (%class.Base*)***
IC: ADD: %1 = bitcast i8* %call1 to void (%class.Base*)***
IC: ADD: %vtable.cast = bitcast i32 (...)** %.sink to void (%class.Base*)**
IC: Visiting: %vtable.cast = bitcast i32 (...)** %.sink to void (%class.Base*)**
IC: Visiting: %1 = bitcast i8* %call1 to void (%class.Base*)***
IC: Visiting: %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable.cast, i16 2
IC: ADD DEFERRED: %vfn6 = getelementptr inbounds i32 (...)*, i32 (...)** %.sink, i16 2
IC: Old = %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable.cast, i16 2
New = <badref> = bitcast i32 (...)** %vfn6 to void (%class.Base*)**
IC: ADD: %vfn = bitcast i32 (...)** %vfn6 to void (%class.Base*)**
IC: ERASE %2 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable.cast, i16 2
IC: ADD DEFERRED: %vtable.cast = bitcast i32 (...)** %.sink to void (%class.Base*)**
IC: ERASE %vtable.cast = bitcast i32 (...)** %.sink to void (%class.Base*)**
IC: ADD DEFERRED: %.sink = select i1 %tobool.not, i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**)
IC: ADD: %.sink = select i1 %tobool.not, i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**)
IC: ADD: %vfn6 = getelementptr inbounds i32 (...)*, i32 (...)** %.sink, i16 2
IC: Visiting: %vfn6 = getelementptr inbounds i32 (...)*, i32 (...)** %.sink, i16 2
IC: Old = %vfn6 = getelementptr inbounds i32 (...)*, i32 (...)** %.sink, i16 2
New = <badref> = select i1 %tobool.not, i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 4) to i32 (...)**), i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 4) to i32 (...)**)
IC: ADD: %vfn6 = select i1 %tobool.not, i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 4) to i32 (...)**), i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 4) to i32 (...)**)
IC: ERASE %2 = getelementptr inbounds i32 (...)*, i32 (...)** %.sink, i16 2
IC: ADD DEFERRED: %.sink = select i1 %tobool.not, i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**)
IC: Visiting: %vfn6 = select i1 %tobool.not, i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 4) to i32 (...)**), i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 4) to i32 (...)**)
IC: Visiting: %.sink = select i1 %tobool.not, i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**)
IC: Visiting: %vfn = bitcast i32 (...)** %vfn6 to void (%class.Base*)**
IC: Old = %vfn = bitcast i32 (...)** %vfn6 to void (%class.Base*)**
New = <badref> = select i1 %tobool.not, void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**), void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**)
IC: ADD: %vfn = select i1 %tobool.not, void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**), void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**)
IC: ERASE %2 = bitcast i32 (...)** %vfn6 to void (%class.Base*)**
IC: ADD DEFERRED: %vfn6 = select i1 %tobool.not, i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 4) to i32 (...)**), i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 4) to i32 (...)**)
IC: ERASE %vfn6 = select i1 %tobool.not, i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 4) to i32 (...)**), i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 4) to i32 (...)**)
IC: ADD DEFERRED: %tobool.not = icmp eq i8 %sel, 0
IC: ADD: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: %vfn = select i1 %tobool.not, void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**), void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**)
IC: Visiting: %2 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: ADD DEFERRED: %.val = load void (%class.Base*)*, void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**), align 1
IC: ADD DEFERRED: %.val7 = load void (%class.Base*)*, void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**), align 1
IC: Old = %2 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
New = <badref> = select i1 %tobool.not, void (%class.Base*)* %.val, void (%class.Base*)* %.val7
IC: ADD: %2 = select i1 %tobool.not, void (%class.Base*)* %.val, void (%class.Base*)* %.val7
IC: ERASE %3 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 1
IC: ADD DEFERRED: %vfn = select i1 %tobool.not, void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**), void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**)
IC: ERASE %vfn = select i1 %tobool.not, void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**), void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**)
IC: ADD DEFERRED: %tobool.not = icmp eq i8 %sel, 0
IC: ADD: %tobool.not = icmp eq i8 %sel, 0
IC: ADD: %.val7 = load void (%class.Base*)*, void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**), align 1
IC: ADD: %.val = load void (%class.Base*)*, void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**), align 1
IC: ConstFold to: void (%class.Base*)* bitcast (void (%class.SubB*)* @_ZN4SubB2fnEv to void (%class.Base*)*) from: %.val = load void (%class.Base*)*, void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**), align 1
IC: Replacing %.val = load void (%class.Base*)*, void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**), align 1
with void (%class.Base*)* bitcast (void (%class.SubB*)* @_ZN4SubB2fnEv to void (%class.Base*)*)
IC: ERASE %.val = load void (%class.Base*)*, void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**), align 1
IC: ConstFold to: void (%class.Base*)* bitcast (void (%class.SubA*)* @_ZN4SubA2fnEv to void (%class.Base*)*) from: %.val7 = load void (%class.Base*)*, void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**), align 1
IC: Replacing %.val7 = load void (%class.Base*)*, void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**), align 1
with void (%class.Base*)* bitcast (void (%class.SubA*)* @_ZN4SubA2fnEv to void (%class.Base*)*)
IC: ERASE %.val7 = load void (%class.Base*)*, void (%class.Base*)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 4) to void (%class.Base*)**), align 1
IC: Visiting: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: %2 = select i1 %tobool.not, void (%class.Base*)* bitcast (void (%class.SubB*)* @_ZN4SubB2fnEv to void (%class.Base*)*), void (%class.Base*)* bitcast (void (%class.SubA*)* @_ZN4SubA2fnEv to void (%class.Base*)*)
IC: Visiting: tail call void %2(%class.Base* nonnull dereferenceable(2) %b.0)
IC: Visiting: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %1, align 1, !tbaa !2
IC: Visiting: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: Visiting: %3 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: Visiting: tail call void %3(%class.Base* nonnull dereferenceable(2) %b.0) #7
IC: Visiting: ret void
INSTCOMBINE ITERATION #2 on _Z11testIndCallc
IC: ADD: ret void
IC: ADD: tail call void %3(%class.Base* nonnull dereferenceable(2) %b.0) #7
IC: ADD: %3 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: ADD: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: ADD: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %1, align 1, !tbaa !2
IC: ADD: tail call void %2(%class.Base* nonnull dereferenceable(2) %b.0)
IC: ADD: %2 = select i1 %tobool.not, void (%class.Base*)* bitcast (void (%class.SubB*)* @_ZN4SubB2fnEv to void (%class.Base*)*), void (%class.Base*)* bitcast (void (%class.SubA*)* @_ZN4SubA2fnEv to void (%class.Base*)*)
IC: ADD: %1 = bitcast i8* %call1 to void (%class.Base*)***
IC: ADD: %b.0 = bitcast i8* %call1 to %class.Base*
IC: ADD: store i32 (...)** %.sink, i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %.sink = select i1 %tobool.not, i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**)
IC: ADD: %0 = bitcast i8* %call1 to i32 (...)***
IC: ADD: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6
IC: ADD: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6
IC: Visiting: %0 = bitcast i8* %call1 to i32 (...)***
IC: Visiting: %.sink = select i1 %tobool.not, i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**)
IC: Visiting: store i32 (...)** %.sink, i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: %b.0 = bitcast i8* %call1 to %class.Base*
IC: Visiting: %1 = bitcast i8* %call1 to void (%class.Base*)***
IC: Visiting: %2 = select i1 %tobool.not, void (%class.Base*)* bitcast (void (%class.SubB*)* @_ZN4SubB2fnEv to void (%class.Base*)*), void (%class.Base*)* bitcast (void (%class.SubA*)* @_ZN4SubA2fnEv to void (%class.Base*)*)
IC: Visiting: tail call void %2(%class.Base* nonnull dereferenceable(2) %b.0)
IC: Visiting: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %1, align 1, !tbaa !2
IC: Visiting: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: Visiting: %3 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: Visiting: tail call void %3(%class.Base* nonnull dereferenceable(2) %b.0) #7
IC: Visiting: ret void
INSTCOMBINE ITERATION #1 on _Z11testIndCallc
IC: ADD: ret void
IC: ADD: tail call void %3(%class.Base* nonnull dereferenceable(2) %b.0) #7
IC: ADD: %3 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: ADD: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: ADD: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %1, align 1, !tbaa !2
IC: ADD: tail call void %2(%class.Base* nonnull dereferenceable(2) %b.0)
IC: ADD: %2 = select i1 %tobool.not, void (%class.Base*)* bitcast (void (%class.SubB*)* @_ZN4SubB2fnEv to void (%class.Base*)*), void (%class.Base*)* bitcast (void (%class.SubA*)* @_ZN4SubA2fnEv to void (%class.Base*)*)
IC: ADD: %1 = bitcast i8* %call1 to void (%class.Base*)***
IC: ADD: %b.0 = bitcast i8* %call1 to %class.Base*
IC: ADD: store i32 (...)** %.sink, i32 (...)*** %0, align 1, !tbaa !2
IC: ADD: %.sink = select i1 %tobool.not, i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**)
IC: ADD: %0 = bitcast i8* %call1 to i32 (...)***
IC: ADD: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6
IC: ADD: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: %tobool.not = icmp eq i8 %sel, 0
IC: Visiting: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6
IC: Visiting: %0 = bitcast i8* %call1 to i32 (...)***
IC: Visiting: %.sink = select i1 %tobool.not, i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**)
IC: Visiting: store i32 (...)** %.sink, i32 (...)*** %0, align 1, !tbaa !2
IC: Visiting: %b.0 = bitcast i8* %call1 to %class.Base*
IC: Visiting: %1 = bitcast i8* %call1 to void (%class.Base*)***
IC: Visiting: %2 = select i1 %tobool.not, void (%class.Base*)* bitcast (void (%class.SubB*)* @_ZN4SubB2fnEv to void (%class.Base*)*), void (%class.Base*)* bitcast (void (%class.SubA*)* @_ZN4SubA2fnEv to void (%class.Base*)*)
IC: Visiting: tail call void %2(%class.Base* nonnull dereferenceable(2) %b.0)
IC: Visiting: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %1, align 1, !tbaa !2
IC: Visiting: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
IC: Visiting: %3 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
IC: Visiting: tail call void %3(%class.Base* nonnull dereferenceable(2) %b.0) #7
IC: Visiting: ret void
F2I: Looking at function _ZN4SubAD0Ev
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4SubAD0Ev ----
Computing probabilities for entry
block-frequency: _ZN4SubAD0Ev
=============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubAD0Ev
- entry: float = 1.0, int = 8
INSTCOMBINE ITERATION #1 on _ZN4SubAD0Ev
IC: ADD: ret void
IC: ADD: tail call void @_ZdlPv(i8* nonnull %0) #6
IC: ADD: %0 = bitcast %class.SubA* %this to i8*
IC: Visiting: %0 = bitcast %class.SubA* %this to i8*
IC: Visiting: tail call void @_ZdlPv(i8* nonnull %0) #6
IC: Visiting: ret void
SLP: Analyzing blocks in _ZN4SubAD0Ev.
INSTCOMBINE ITERATION #1 on _ZN4SubAD0Ev
IC: ADD: ret void
IC: ADD: tail call void @_ZdlPv(i8* nonnull %0) #6
IC: ADD: %0 = bitcast %class.SubA* %this to i8*
IC: Visiting: %0 = bitcast %class.SubA* %this to i8*
IC: Visiting: tail call void @_ZdlPv(i8* nonnull %0) #6
IC: Visiting: ret void
INSTCOMBINE ITERATION #1 on _ZN4SubAD0Ev
IC: ADD: ret void
IC: ADD: tail call void @_ZdlPv(i8* nonnull %0) #6
IC: ADD: %0 = bitcast %class.SubA* %this to i8*
IC: Visiting: %0 = bitcast %class.SubA* %this to i8*
IC: Visiting: tail call void @_ZdlPv(i8* nonnull %0) #6
IC: Visiting: ret void
F2I: Looking at function _ZN4SubA2fnEv
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4SubA2fnEv ----
Computing probabilities for entry
block-frequency: _ZN4SubA2fnEv
==============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubA2fnEv
- entry: float = 1.0, int = 8
INSTCOMBINE ITERATION #1 on _ZN4SubA2fnEv
IC: ADD: ret void
IC: Visiting: ret void
SLP: Analyzing blocks in _ZN4SubA2fnEv.
INSTCOMBINE ITERATION #1 on _ZN4SubA2fnEv
IC: ADD: ret void
IC: Visiting: ret void
INSTCOMBINE ITERATION #1 on _ZN4SubA2fnEv
IC: ADD: ret void
IC: Visiting: ret void
F2I: Looking at function _ZN4BaseD2Ev
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4BaseD2Ev ----
Computing probabilities for entry
block-frequency: _ZN4BaseD2Ev
=============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4BaseD2Ev
- entry: float = 1.0, int = 8
INSTCOMBINE ITERATION #1 on _ZN4BaseD2Ev
IC: ADD: ret void
IC: Visiting: ret void
SLP: Analyzing blocks in _ZN4BaseD2Ev.
INSTCOMBINE ITERATION #1 on _ZN4BaseD2Ev
IC: ADD: ret void
IC: Visiting: ret void
INSTCOMBINE ITERATION #1 on _ZN4BaseD2Ev
IC: ADD: ret void
IC: Visiting: ret void
F2I: Looking at function _ZN4SubBD0Ev
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4SubBD0Ev ----
Computing probabilities for entry
block-frequency: _ZN4SubBD0Ev
=============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubBD0Ev
- entry: float = 1.0, int = 8
INSTCOMBINE ITERATION #1 on _ZN4SubBD0Ev
IC: ADD: ret void
IC: ADD: tail call void @_ZdlPv(i8* nonnull %0) #6
IC: ADD: %0 = bitcast %class.SubB* %this to i8*
IC: Visiting: %0 = bitcast %class.SubB* %this to i8*
IC: Visiting: tail call void @_ZdlPv(i8* nonnull %0) #6
IC: Visiting: ret void
SLP: Analyzing blocks in _ZN4SubBD0Ev.
INSTCOMBINE ITERATION #1 on _ZN4SubBD0Ev
IC: ADD: ret void
IC: ADD: tail call void @_ZdlPv(i8* nonnull %0) #6
IC: ADD: %0 = bitcast %class.SubB* %this to i8*
IC: Visiting: %0 = bitcast %class.SubB* %this to i8*
IC: Visiting: tail call void @_ZdlPv(i8* nonnull %0) #6
IC: Visiting: ret void
INSTCOMBINE ITERATION #1 on _ZN4SubBD0Ev
IC: ADD: ret void
IC: ADD: tail call void @_ZdlPv(i8* nonnull %0) #6
IC: ADD: %0 = bitcast %class.SubB* %this to i8*
IC: Visiting: %0 = bitcast %class.SubB* %this to i8*
IC: Visiting: tail call void @_ZdlPv(i8* nonnull %0) #6
IC: Visiting: ret void
F2I: Looking at function _ZN4SubB2fnEv
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4SubB2fnEv ----
Computing probabilities for entry
block-frequency: _ZN4SubB2fnEv
==============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubB2fnEv
- entry: float = 1.0, int = 8
INSTCOMBINE ITERATION #1 on _ZN4SubB2fnEv
IC: ADD: ret void
IC: Visiting: ret void
SLP: Analyzing blocks in _ZN4SubB2fnEv.
INSTCOMBINE ITERATION #1 on _ZN4SubB2fnEv
IC: ADD: ret void
IC: Visiting: ret void
INSTCOMBINE ITERATION #1 on _ZN4SubB2fnEv
IC: ADD: ret void
IC: Visiting: ret void
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _Z11testIndCallc ----
Computing probabilities for entry
block-frequency: _Z11testIndCallc
=================================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _Z11testIndCallc
- entry: float = 1.0, int = 8
**** ObjCARC Contract ****
Visiting: %tobool.not = icmp eq i8 %sel, 0
Visiting: %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6
Visiting: %0 = bitcast i8* %call1 to i32 (...)***
Visiting: %.sink = select i1 %tobool.not, i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**)
Visiting: store i32 (...)** %.sink, i32 (...)*** %0, align 1, !tbaa !2
Visiting: %b.0 = bitcast i8* %call1 to %class.Base*
Visiting: %1 = bitcast i8* %call1 to void (%class.Base*)***
Visiting: %2 = select i1 %tobool.not, void (%class.Base*)* bitcast (void (%class.SubB*)* @_ZN4SubB2fnEv to void (%class.Base*)*), void (%class.Base*)* bitcast (void (%class.SubA*)* @_ZN4SubA2fnEv to void (%class.Base*)*)
Visiting: tail call void %2(%class.Base* nonnull dereferenceable(2) %b.0)
Visiting: %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %1, align 1, !tbaa !2
Visiting: %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1
Visiting: %3 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1
Visiting: tail call void %3(%class.Base* nonnull dereferenceable(2) %b.0) #7
Visiting: ret void
**** ObjCARC Contract ****
Visiting: %0 = bitcast %class.SubA* %this to i8*
Visiting: tail call void @_ZdlPv(i8* nonnull %0) #6
Visiting: ret void
**** ObjCARC Contract ****
Visiting: ret void
**** ObjCARC Contract ****
Visiting: ret void
**** ObjCARC Contract ****
Visiting: %0 = bitcast %class.SubB* %this to i8*
Visiting: tail call void @_ZdlPv(i8* nonnull %0) #6
Visiting: ret void
**** ObjCARC Contract ****
Visiting: ret void
**** MOS NoRecurse Pass ****
Found new non-recursive function.
Call graph node for function: '_ZN4SubA2fnEv'<<0x2002c998160>> #uses=1
Found new non-recursive function.
Call graph node for function: '_ZN4BaseD2Ev'<<0x2002c998660>> #uses=1
Found new non-recursive function.
Call graph node for function: '_ZN4SubB2fnEv'<<0x2002c998360>> #uses=1
MergeICmpsLegacyPass: _Z11testIndCallc
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _Z11testIndCallc ----
Computing probabilities for entry
block-frequency: _Z11testIndCallc
=================================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _Z11testIndCallc
- entry: float = 1.0, int = 8
********** Begin Constant Hoisting **********
********** Function: _Z11testIndCallc
********** End Constant Hoisting **********
---- Branch Probability Info : _Z11testIndCallc ----
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
Computing probabilities for entry
block-frequency: _Z11testIndCallc
=================================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _Z11testIndCallc
- entry: float = 1.0, int = 8
CGP: Found local addrmode: [inbounds Base:%call1]
CGP: Found local addrmode: [inbounds Base:%call1]
CGP: Found local addrmode: [inbounds Base:%call1]
CGP: Found local addrmode: [inbounds 2 + Base:%vtable2]
CGP: Found local addrmode: [inbounds Base:%call1]
CGP: Found local addrmode: [inbounds Base:%call1]
CGP: Found local addrmode: [inbounds 2 + Base:%vtable2]
MergeICmpsLegacyPass: _ZN4SubAD0Ev
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4SubAD0Ev ----
Computing probabilities for entry
block-frequency: _ZN4SubAD0Ev
=============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubAD0Ev
- entry: float = 1.0, int = 8
********** Begin Constant Hoisting **********
********** Function: _ZN4SubAD0Ev
********** End Constant Hoisting **********
---- Branch Probability Info : _ZN4SubAD0Ev ----
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
Computing probabilities for entry
block-frequency: _ZN4SubAD0Ev
=============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubAD0Ev
- entry: float = 1.0, int = 8
MergeICmpsLegacyPass: _ZN4SubA2fnEv
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4SubA2fnEv ----
Computing probabilities for entry
block-frequency: _ZN4SubA2fnEv
==============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubA2fnEv
- entry: float = 1.0, int = 8
********** Begin Constant Hoisting **********
********** Function: _ZN4SubA2fnEv
********** End Constant Hoisting **********
---- Branch Probability Info : _ZN4SubA2fnEv ----
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
Computing probabilities for entry
block-frequency: _ZN4SubA2fnEv
==============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubA2fnEv
- entry: float = 1.0, int = 8
MergeICmpsLegacyPass: _ZN4BaseD2Ev
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4BaseD2Ev ----
Computing probabilities for entry
block-frequency: _ZN4BaseD2Ev
=============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4BaseD2Ev
- entry: float = 1.0, int = 8
********** Begin Constant Hoisting **********
********** Function: _ZN4BaseD2Ev
********** End Constant Hoisting **********
---- Branch Probability Info : _ZN4BaseD2Ev ----
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
Computing probabilities for entry
block-frequency: _ZN4BaseD2Ev
=============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4BaseD2Ev
- entry: float = 1.0, int = 8
MergeICmpsLegacyPass: _ZN4SubBD0Ev
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4SubBD0Ev ----
Computing probabilities for entry
block-frequency: _ZN4SubBD0Ev
=============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubBD0Ev
- entry: float = 1.0, int = 8
********** Begin Constant Hoisting **********
********** Function: _ZN4SubBD0Ev
********** End Constant Hoisting **********
---- Branch Probability Info : _ZN4SubBD0Ev ----
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
Computing probabilities for entry
block-frequency: _ZN4SubBD0Ev
=============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubBD0Ev
- entry: float = 1.0, int = 8
MergeICmpsLegacyPass: _ZN4SubB2fnEv
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4SubB2fnEv ----
Computing probabilities for entry
block-frequency: _ZN4SubB2fnEv
==============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubB2fnEv
- entry: float = 1.0, int = 8
********** Begin Constant Hoisting **********
********** Function: _ZN4SubB2fnEv
********** End Constant Hoisting **********
---- Branch Probability Info : _ZN4SubB2fnEv ----
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
Computing probabilities for entry
block-frequency: _ZN4SubB2fnEv
==============================
reverse-post-order-traversal
- 0: entry
loop-detection
compute-mass-in-function
- node: entry
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- entry: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubB2fnEv
- entry: float = 1.0, int = 8
[SafeStack] Function: _Z11testIndCallc
[SafeStack] safestack is not requested for this function
Looking for trivial roots
Found a new trivial root: %select.end8
Last visited node: %entry
Looking for non-trivial roots
Total: 5, Num: 6
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %select.end8
3: %select.false9
4: %select.end
5: %select.false
6: %entry
Found roots: %select.end8
---- Branch Probability Info : _Z11testIndCallc ----
Computing probabilities for select.end8
Computing probabilities for select.false9
Computing probabilities for select.end
eraseBlock select.end
set edge select.end -> 0 successor probability to 0x30000000 / 0x80000000 = 37.50%
set edge select.end -> 1 successor probability to 0x50000000 / 0x80000000 = 62.50%
Computing probabilities for select.false
Computing probabilities for entry
eraseBlock entry
set edge entry -> 0 successor probability to 0x30000000 / 0x80000000 = 37.50%
set edge entry -> 1 successor probability to 0x50000000 / 0x80000000 = 62.50%
Checking DILocation from %.sink.frozen = freeze i8 %sel was copied to G_FREEZE
CSEInfo::Recording new MI G_CONSTANT
Checking DILocation from %tobool.not = icmp eq i8 %.sink.frozen, 0 was copied to G_CONSTANT
Checking DILocation from %tobool.not = icmp eq i8 %.sink.frozen, 0 was copied to G_ICMP
CSEInfo::Recording new MI G_CONSTANT
Checking DILocation from %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6 was copied to G_CONSTANT
Checking DILocation from %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6 was copied to ADJCALLSTACKDOWN implicit-def $rs0, implicit $rs0
CSEInfo::Recording new MI G_UNMERGE_VALUES
Checking DILocation from %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6 was copied to G_UNMERGE_VALUES
Checking DILocation from %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6 was copied to COPY
Checking DILocation from %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6 was copied to COPY
Checking DILocation from %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6 was copied to JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $a, implicit $x
Checking DILocation from %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6 was copied to COPY
Checking DILocation from %call1 = tail call noalias nonnull i8* @_Znwt(i16 zeroext 2) #6 was copied to ADJCALLSTACKUP implicit-def $rs0, implicit $rs0
Checking DILocation from br i1 %tobool.not, label %select.end, label %select.false was copied to G_BRCOND
Checking DILocation from br i1 %tobool.not, label %select.end, label %select.false was copied to G_BR
Checking DILocation from %.sink = phi i32 (...)** [ bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), %entry ], [ bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), %select.false ] was copied to G_PHI
Checking DILocation from %.frozen = freeze i8 %sel was copied to G_FREEZE
Checking DILocation from %1 = icmp eq i8 %.frozen, 0 was copied to G_ICMP
Checking DILocation from store i32 (...)** %.sink, i32 (...)*** %0, align 1, !tbaa !2 was copied to G_STORE
Checking DILocation from br i1 %1, label %select.end8, label %select.false9 was copied to G_BRCOND
Checking DILocation from br i1 %1, label %select.end8, label %select.false9 was copied to G_BR
Checking DILocation from %2 = phi void (%class.Base*)* [ bitcast (void (%class.SubB*)* @_ZN4SubB2fnEv to void (%class.Base*)*), %select.end ], [ bitcast (void (%class.SubA*)* @_ZN4SubA2fnEv to void (%class.Base*)*), %select.false9 ] was copied to G_PHI
Checking DILocation from tail call void %2(%class.Base* nonnull dereferenceable(2) %4) was copied to COPY
Checking DILocation from tail call void %2(%class.Base* nonnull dereferenceable(2) %4) was copied to ADJCALLSTACKDOWN implicit-def $rs0, implicit $rs0
Checking DILocation from tail call void %2(%class.Base* nonnull dereferenceable(2) %4) was copied to COPY
Checking DILocation from tail call void %2(%class.Base* nonnull dereferenceable(2) %4) was copied to JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
Checking DILocation from tail call void %2(%class.Base* nonnull dereferenceable(2) %4) was copied to ADJCALLSTACKUP implicit-def $rs0, implicit $rs0
Checking DILocation from %vtable2 = load void (%class.Base*)**, void (%class.Base*)*** %3, align 1, !tbaa !2 was copied to G_LOAD
CSEInfo::Recording new MI G_CONSTANT
Checking DILocation from %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1 was copied to G_CONSTANT
CSEInfo::Recording new MI G_PTR_ADD
Checking DILocation from %vfn3 = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable2, i16 1 was copied to G_PTR_ADD
Checking DILocation from %5 = load void (%class.Base*)*, void (%class.Base*)** %vfn3, align 1 was copied to G_LOAD
Checking DILocation from tail call void %5(%class.Base* nonnull dereferenceable(2) %4) #7 was copied to COPY
Checking DILocation from tail call void %5(%class.Base* nonnull dereferenceable(2) %4) #7 was copied to ADJCALLSTACKDOWN implicit-def $rs0, implicit $rs0
Checking DILocation from tail call void %5(%class.Base* nonnull dereferenceable(2) %4) #7 was copied to COPY
Checking DILocation from tail call void %5(%class.Base* nonnull dereferenceable(2) %4) #7 was copied to JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
Checking DILocation from tail call void %5(%class.Base* nonnull dereferenceable(2) %4) #7 was copied to ADJCALLSTACKUP implicit-def $rs0, implicit $rs0
Checking DILocation from ret void was copied to RTS
Checking DILocation from %.sink = phi i32 (...)** [ bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), %entry ], [ bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), %select.false ] was copied to G_GLOBAL_VALUE
Checking DILocation from %.sink = phi i32 (...)** [ bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), %entry ], [ bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), %select.false ] was copied to G_CONSTANT
Checking DILocation from %.sink = phi i32 (...)** [ bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), %entry ], [ bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), %select.false ] was copied to G_PTR_ADD
Checking DILocation from %.sink = phi i32 (...)** [ bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), %entry ], [ bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), %select.false ] was copied to COPY
Checking DILocation from %.sink = phi i32 (...)** [ bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), %entry ], [ bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), %select.false ] was copied to G_GLOBAL_VALUE
CSEInfo::Found Instr %19:_(s16) = G_CONSTANT i16 4
Checking DILocation from %.sink = phi i32 (...)** [ bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), %entry ], [ bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), %select.false ] was copied to G_PTR_ADD
Checking DILocation from %.sink = phi i32 (...)** [ bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubB, i16 0, inrange i32 0, i16 2) to i32 (...)**), %entry ], [ bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV4SubA, i16 0, inrange i32 0, i16 2) to i32 (...)**), %select.false ] was copied to COPY
Checking DILocation from %2 = phi void (%class.Base*)* [ bitcast (void (%class.SubB*)* @_ZN4SubB2fnEv to void (%class.Base*)*), %select.end ], [ bitcast (void (%class.SubA*)* @_ZN4SubA2fnEv to void (%class.Base*)*), %select.false9 ] was copied to G_GLOBAL_VALUE
Checking DILocation from %2 = phi void (%class.Base*)* [ bitcast (void (%class.SubB*)* @_ZN4SubB2fnEv to void (%class.Base*)*), %select.end ], [ bitcast (void (%class.SubA*)* @_ZN4SubA2fnEv to void (%class.Base*)*), %select.false9 ] was copied to COPY
Checking DILocation from %2 = phi void (%class.Base*)* [ bitcast (void (%class.SubB*)* @_ZN4SubB2fnEv to void (%class.Base*)*), %select.end ], [ bitcast (void (%class.SubA*)* @_ZN4SubA2fnEv to void (%class.Base*)*), %select.false9 ] was copied to G_GLOBAL_VALUE
Checking DILocation from %2 = phi void (%class.Base*)* [ bitcast (void (%class.SubB*)* @_ZN4SubB2fnEv to void (%class.Base*)*), %select.end ], [ bitcast (void (%class.SubA*)* @_ZN4SubA2fnEv to void (%class.Base*)*), %select.false9 ] was copied to COPY
CSEInfo::CSE Hit for Opc 104 : 1
CSEInfo::Add MI: %2:_(s8) = G_CONSTANT i8 0
CSEInfo::Add MI: %5:_(s16) = G_CONSTANT i16 2
CSEInfo::Add MI: %19:_(s16) = G_CONSTANT i16 4
CSEInfo::Add MI: %17:_(p0) = G_PTR_ADD %18:_, %19:_(s16)
CSEInfo::Add MI: %21:_(p0) = G_PTR_ADD %22:_, %19:_(s16)
CSEInfo::Add MI: %6:_(s8), %7:_(s8) = G_UNMERGE_VALUES %5:_(s16)
CSEInfo::Add MI: %13:_(s16) = G_CONSTANT i16 2
CSEInfo::Add MI: %14:_(p0) = G_PTR_ADD %12:_, %13:_(s16)
Generic MI Combiner for: _Z11testIndCallc
Try combining %0:_(s8) = COPY $a
Try combining %2:_(s8) = G_CONSTANT i8 0
Try combining %5:_(s16) = G_CONSTANT i16 2
Try combining %18:_(p0) = G_GLOBAL_VALUE @_ZTV4SubB
Try combining %19:_(s16) = G_CONSTANT i16 4
Try combining %17:_(p0) = G_PTR_ADD %18:_, %19:_(s16)
Changing: %17:_(p0) = G_PTR_ADD %18:_, %19:_(s16)
CSEInfo::Recording new MI %17:_(p0) = G_PTR_ADD %18:_, %19:_(s16)
Changed: %17:_(p0) = G_GLOBAL_VALUE @_ZTV4SubB + 4
Try combining %17:_(p0) = G_GLOBAL_VALUE @_ZTV4SubB + 4
Try combining %16:_(p0) = COPY %17:_(p0)
Erasing: %16:_(p0) = COPY %17:_(p0)
Changing: %8:_(p0) = G_PHI %16:_(p0), %bb.1, %20:_(p0), %bb.2
Changed: %8:_(p0) = G_PHI %17:_(p0), %bb.1, %20:_(p0), %bb.2
Try combining %22:_(p0) = G_GLOBAL_VALUE @_ZTV4SubA
Try combining %21:_(p0) = G_PTR_ADD %22:_, %19:_(s16)
Changing: %21:_(p0) = G_PTR_ADD %22:_, %19:_(s16)
CSEInfo::Recording new MI %21:_(p0) = G_PTR_ADD %22:_, %19:_(s16)
Changed: %21:_(p0) = G_GLOBAL_VALUE @_ZTV4SubA + 4
Try combining %21:_(p0) = G_GLOBAL_VALUE @_ZTV4SubA + 4
Try combining %20:_(p0) = COPY %21:_(p0)
Erasing: %20:_(p0) = COPY %21:_(p0)
Changing: %8:_(p0) = G_PHI %17:_(p0), %bb.1, %20:_(p0), %bb.2
Changed: %8:_(p0) = G_PHI %17:_(p0), %bb.1, %21:_(p0), %bb.2
Try combining %24:_(p0) = G_GLOBAL_VALUE @_ZN4SubB2fnEv
Try combining %23:_(p0) = COPY %24:_(p0)
Erasing: %23:_(p0) = COPY %24:_(p0)
Changing: %11:_(p0) = G_PHI %23:_(p0), %bb.3, %25:_(p0), %bb.4
Changed: %11:_(p0) = G_PHI %24:_(p0), %bb.3, %25:_(p0), %bb.4
Try combining %26:_(p0) = G_GLOBAL_VALUE @_ZN4SubA2fnEv
Try combining %25:_(p0) = COPY %26:_(p0)
Erasing: %25:_(p0) = COPY %26:_(p0)
Changing: %11:_(p0) = G_PHI %24:_(p0), %bb.3, %25:_(p0), %bb.4
Changed: %11:_(p0) = G_PHI %24:_(p0), %bb.3, %26:_(p0), %bb.4
Try combining %1:_(s8) = G_FREEZE %0:_
Try combining %3:_(s1) = G_ICMP intpred(eq), %1:_(s8), %2:_
Try combining ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Try combining %6:_(s8), %7:_(s8) = G_UNMERGE_VALUES %5:_(s16)
Creating: G_CONSTANT
CSEInfo::Recording new MI G_CONSTANT
CSEInfo::Found Instr %2:_(s8) = G_CONSTANT i8 0
Creating: COPY
Erasing: %6:_(s8), %7:_(s8) = G_UNMERGE_VALUES %5:_(s16)
Created: %6:_(s8) = G_CONSTANT i8 2
Created: %7:_(s8) = COPY %2:_(s8)
Try combining %7:_(s8) = COPY %2:_(s8)
Erasing: %7:_(s8) = COPY %2:_(s8)
Changing: $x = COPY %7:_(s8)
Changed: $x = COPY %2:_(s8)
Try combining %6:_(s8) = G_CONSTANT i8 2
Try combining $a = COPY %6:_(s8)
Try combining $x = COPY %2:_(s8)
Try combining JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $a, implicit $x, implicit-def $rs1
Try combining %4:_(p0) = COPY $rs1
Try combining ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Try combining G_BRCOND %3:_(s1), %bb.3
Try combining G_BR %bb.2
Try combining %8:_(p0) = G_PHI %17:_(p0), %bb.1, %21:_(p0), %bb.2
Try combining %9:_(s8) = G_FREEZE %0:_
Try combining %10:_(s1) = G_ICMP intpred(eq), %9:_(s8), %2:_
Try combining G_STORE %8:_(p0), %4:_(p0) :: (store 2 into %ir.0, align 1, !tbaa !2)
Try combining G_BRCOND %10:_(s1), %bb.5
Try combining G_BR %bb.4
Try combining %11:_(p0) = G_PHI %24:_(p0), %bb.3, %26:_(p0), %bb.4
Try combining $rs8 = COPY %11:_(p0)
Try combining ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Try combining $rs1 = COPY %4:_(p0)
Try combining JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
Try combining ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Try combining %12:_(p0) = G_LOAD %4:_(p0) :: (load 2 from %ir.3, align 1, !tbaa !2)
Try combining %13:_(s16) = G_CONSTANT i16 2
Try combining %14:_(p0) = G_PTR_ADD %12:_, %13:_(s16)
Try combining %15:_(p0) = G_LOAD %14:_(p0) :: (load 2 from %ir.vfn3, align 1)
Try combining $rs8 = COPY %15:_(p0)
Try combining ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Try combining $rs1 = COPY %4:_(p0)
Try combining JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
Try combining ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Try combining RTS
%22:_(p0) = G_GLOBAL_VALUE @_ZTV4SubA
Is dead; erasing.
Erasing: %22:_(p0) = G_GLOBAL_VALUE @_ZTV4SubA
%19:_(s16) = G_CONSTANT i16 4
Is dead; erasing.
Erasing: %19:_(s16) = G_CONSTANT i16 4
%18:_(p0) = G_GLOBAL_VALUE @_ZTV4SubB
Is dead; erasing.
Erasing: %18:_(p0) = G_GLOBAL_VALUE @_ZTV4SubB
%5:_(s16) = G_CONSTANT i16 2
Is dead; erasing.
Erasing: %5:_(s16) = G_CONSTANT i16 2
Try combining %0:_(s8) = COPY $a
Try combining %2:_(s8) = G_CONSTANT i8 0
Try combining %17:_(p0) = G_GLOBAL_VALUE @_ZTV4SubB + 4
Try combining %21:_(p0) = G_GLOBAL_VALUE @_ZTV4SubA + 4
Try combining %24:_(p0) = G_GLOBAL_VALUE @_ZN4SubB2fnEv
Try combining %26:_(p0) = G_GLOBAL_VALUE @_ZN4SubA2fnEv
Try combining %1:_(s8) = G_FREEZE %0:_
Try combining %3:_(s1) = G_ICMP intpred(eq), %1:_(s8), %2:_
Try combining ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Try combining %6:_(s8) = G_CONSTANT i8 2
Try combining $a = COPY %6:_(s8)
Try combining $x = COPY %2:_(s8)
Try combining JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $a, implicit $x, implicit-def $rs1
Try combining %4:_(p0) = COPY $rs1
Try combining ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Try combining G_BRCOND %3:_(s1), %bb.3
Try combining G_BR %bb.2
Try combining %8:_(p0) = G_PHI %17:_(p0), %bb.1, %21:_(p0), %bb.2
Try combining %9:_(s8) = G_FREEZE %0:_
Try combining %10:_(s1) = G_ICMP intpred(eq), %9:_(s8), %2:_
Try combining G_STORE %8:_(p0), %4:_(p0) :: (store 2 into %ir.0, align 1, !tbaa !2)
Try combining G_BRCOND %10:_(s1), %bb.5
Try combining G_BR %bb.4
Try combining %11:_(p0) = G_PHI %24:_(p0), %bb.3, %26:_(p0), %bb.4
Try combining $rs8 = COPY %11:_(p0)
Try combining ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Try combining $rs1 = COPY %4:_(p0)
Try combining JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
Try combining ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Try combining %12:_(p0) = G_LOAD %4:_(p0) :: (load 2 from %ir.3, align 1, !tbaa !2)
Try combining %13:_(s16) = G_CONSTANT i16 2
Try combining %14:_(p0) = G_PTR_ADD %12:_, %13:_(s16)
Try combining %15:_(p0) = G_LOAD %14:_(p0) :: (load 2 from %ir.vfn3, align 1)
Try combining $rs8 = COPY %15:_(p0)
Try combining ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Try combining $rs1 = COPY %4:_(p0)
Try combining JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
Try combining ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Try combining RTS
Legalize Machine IR for: _Z11testIndCallc
=== New Iteration ===
Legalizing: %15:_(p0) = G_LOAD %14:_(p0) :: (load 2 from %ir.vfn3, align 1)
Applying legalizer ruleset to: 74, Tys={p0, p0, }, Opcode=74, MMOs={16, }
.. no match
.. match
.. .. Custom, 0, LLT_invalid
.. Custom legalization
.. .. Changing MI: %15:_(p0) = G_LOAD %14:_(p0) :: (load 2 from %ir.vfn3, align 1)
.. .. Changed MI: %27:_(s16) = G_LOAD %14:_(p0) :: (load 2 from %ir.vfn3, align 1)
.. .. New MI: %15:_(p0) = G_INTTOPTR %27:_(s16)
.. No debug info was present
Legalizing: %27:_(s16) = G_LOAD %14:_(p0) :: (load 2 from %ir.vfn3, align 1)
Applying legalizer ruleset to: 74, Tys={s16, p0, }, Opcode=74, MMOs={16, }
.. no match
.. no match
.. no match
.. match
.. .. NarrowScalar, 0, s8
.. Narrow scalar
CSEInfo::Recording new MI G_CONSTANT
CSEInfo::Recording new MI G_PTR_ADD
.. .. Erasing: %27:_(s16) = G_LOAD %14:_(p0) :: (load 2 from %ir.vfn3, align 1)
.. .. New MI: %28:_(s8) = G_LOAD %14:_(p0) :: (load 1 from %ir.vfn3)
.. .. New MI: %30:_(s16) = G_CONSTANT i16 1
.. .. New MI: %29:_(p0) = G_PTR_ADD %14:_, %30:_(s16)
.. .. New MI: %31:_(s8) = G_LOAD %29:_(p0) :: (load 1 from %ir.vfn3 + 1)
.. .. New MI: %27:_(s16) = G_MERGE_VALUES %28:_(s8), %31:_(s8)
.. No debug info was present
Legalizing: %31:_(s8) = G_LOAD %29:_(p0) :: (load 1 from %ir.vfn3 + 1)
Applying legalizer ruleset to: 74, Tys={s8, p0, }, Opcode=74, MMOs={8, }
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %29:_(p0) = G_PTR_ADD %14:_, %30:_(s16)
Applying legalizer ruleset to: 177, Tys={p0, s16, }, Opcode=177, MMOs={}
.. match
.. .. Custom, 0, LLT_invalid
.. Custom legalization
CSEInfo::Recording new MI G_CONSTANT
.. .. Changing MI: %29:_(p0) = G_PTR_ADD %14:_, %30:_(s16)
CSEInfo::Recording new MI %29:_(p0) = G_PTR_ADD %14:_, %30:_(s16)
.. .. Changed MI: %29:_(p0) = G_INDEX %14:_, %32:_(s8)
.. .. New MI: %32:_(s8) = G_CONSTANT i8 1
.. No debug info was present
Legalizing: %32:_(s8) = G_CONSTANT i8 1
Applying legalizer ruleset to: 104, Tys={s8, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
%30:_(s16) = G_CONSTANT i16 1
Is dead; erasing.
.. .. Erasing: %30:_(s16) = G_CONSTANT i16 1
Legalizing: %28:_(s8) = G_LOAD %14:_(p0) :: (load 1 from %ir.vfn3)
Applying legalizer ruleset to: 74, Tys={s8, p0, }, Opcode=74, MMOs={8, }
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %15:_(p0) = G_INTTOPTR %27:_(s16)
Applying legalizer ruleset to: 66, Tys={p0, s16, }, Opcode=66, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %14:_(p0) = G_PTR_ADD %12:_, %13:_(s16)
Applying legalizer ruleset to: 177, Tys={p0, s16, }, Opcode=177, MMOs={}
.. match
.. .. Custom, 0, LLT_invalid
.. Custom legalization
CSEInfo::Recording new MI G_CONSTANT
.. .. Changing MI: %14:_(p0) = G_PTR_ADD %12:_, %13:_(s16)
CSEInfo::Recording new MI %14:_(p0) = G_PTR_ADD %12:_, %13:_(s16)
.. .. Changed MI: %14:_(p0) = G_INDEX %12:_, %33:_(s8)
.. .. New MI: %33:_(s8) = G_CONSTANT i8 2
.. No debug info was present
Legalizing: %33:_(s8) = G_CONSTANT i8 2
Applying legalizer ruleset to: 104, Tys={s8, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
%13:_(s16) = G_CONSTANT i16 2
Is dead; erasing.
.. .. Erasing: %13:_(s16) = G_CONSTANT i16 2
Legalizing: %12:_(p0) = G_LOAD %4:_(p0) :: (load 2 from %ir.3, align 1, !tbaa !2)
Applying legalizer ruleset to: 74, Tys={p0, p0, }, Opcode=74, MMOs={16, }
.. no match
.. match
.. .. Custom, 0, LLT_invalid
.. Custom legalization
.. .. Changing MI: %12:_(p0) = G_LOAD %4:_(p0) :: (load 2 from %ir.3, align 1, !tbaa !2)
.. .. Changed MI: %34:_(s16) = G_LOAD %4:_(p0) :: (load 2 from %ir.3, align 1, !tbaa !2)
.. .. New MI: %12:_(p0) = G_INTTOPTR %34:_(s16)
.. No debug info was present
Legalizing: %34:_(s16) = G_LOAD %4:_(p0) :: (load 2 from %ir.3, align 1, !tbaa !2)
Applying legalizer ruleset to: 74, Tys={s16, p0, }, Opcode=74, MMOs={16, }
.. no match
.. no match
.. no match
.. match
.. .. NarrowScalar, 0, s8
.. Narrow scalar
CSEInfo::Recording new MI G_CONSTANT
CSEInfo::Recording new MI G_PTR_ADD
.. .. Erasing: %34:_(s16) = G_LOAD %4:_(p0) :: (load 2 from %ir.3, align 1, !tbaa !2)
.. .. New MI: %35:_(s8) = G_LOAD %4:_(p0) :: (load 1 from %ir.3, !tbaa !2)
.. .. New MI: %37:_(s16) = G_CONSTANT i16 1
.. .. New MI: %36:_(p0) = G_PTR_ADD %4:_, %37:_(s16)
.. .. New MI: %38:_(s8) = G_LOAD %36:_(p0) :: (load 1 from %ir.3 + 1, !tbaa !2)
.. .. New MI: %34:_(s16) = G_MERGE_VALUES %35:_(s8), %38:_(s8)
.. No debug info was present
Legalizing: %38:_(s8) = G_LOAD %36:_(p0) :: (load 1 from %ir.3 + 1, !tbaa !2)
Applying legalizer ruleset to: 74, Tys={s8, p0, }, Opcode=74, MMOs={8, }
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %36:_(p0) = G_PTR_ADD %4:_, %37:_(s16)
Applying legalizer ruleset to: 177, Tys={p0, s16, }, Opcode=177, MMOs={}
.. match
.. .. Custom, 0, LLT_invalid
.. Custom legalization
CSEInfo::Found Instr %32:_(s8) = G_CONSTANT i8 1
.. .. Changing MI: %36:_(p0) = G_PTR_ADD %4:_, %37:_(s16)
CSEInfo::Recording new MI %36:_(p0) = G_PTR_ADD %4:_, %37:_(s16)
.. .. Changed MI: %36:_(p0) = G_INDEX %4:_, %32:_(s8)
.. No debug info was present
%37:_(s16) = G_CONSTANT i16 1
Is dead; erasing.
.. .. Erasing: %37:_(s16) = G_CONSTANT i16 1
Legalizing: %35:_(s8) = G_LOAD %4:_(p0) :: (load 1 from %ir.3, !tbaa !2)
Applying legalizer ruleset to: 74, Tys={s8, p0, }, Opcode=74, MMOs={8, }
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %12:_(p0) = G_INTTOPTR %34:_(s16)
Applying legalizer ruleset to: 66, Tys={p0, s16, }, Opcode=66, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %11:_(p0) = G_PHI %24:_(p0), %bb.3, %26:_(p0), %bb.4
Applying legalizer ruleset to: 55, Tys={p0, }, Opcode=55, MMOs={}
.. match
.. .. Custom, 0, LLT_invalid
.. Custom legalization
.. .. Changing MI: %11:_(p0) = G_PHI %24:_(p0), %bb.3, %26:_(p0), %bb.4
.. .. Changed MI: %41:_(s16) = G_PHI %39:_(s16), %bb.3, %40:_(s16), %bb.4
.. .. New MI: %39:_(s16) = G_PTRTOINT %24:_(p0)
.. .. New MI: %40:_(s16) = G_PTRTOINT %26:_(p0)
.. .. New MI: %11:_(p0) = G_INTTOPTR %41:_(s16)
.. No debug info was present
Legalizing: %41:_(s16) = G_PHI %39:_(s16), %bb.3, %40:_(s16), %bb.4
Applying legalizer ruleset to: 55, Tys={s16, }, Opcode=55, MMOs={}
.. no match
.. no match
.. no match
.. no match
.. match
.. .. NarrowScalar, 0, s8
.. Narrow scalar
.. .. Changing MI: %41:_(s16) = G_PHI %39:_(s16), %bb.3, %40:_(s16), %bb.4
CSEInfo::Recording new MI G_UNMERGE_VALUES
CSEInfo::Recording new MI G_UNMERGE_VALUES
.. .. Changed MI: %41:_(s16) = G_PHI %39:_(s16), %bb.3, %40:_(s16), %bb.4
.. .. Erasing: %41:_(s16) = G_PHI %39:_(s16), %bb.3, %40:_(s16), %bb.4
.. .. New MI: %42:_(s8), %43:_(s8) = G_UNMERGE_VALUES %39:_(s16)
.. .. New MI: %44:_(s8), %45:_(s8) = G_UNMERGE_VALUES %40:_(s16)
.. .. New MI: %46:_(s8) = G_PHI %42:_(s8), %bb.3, %44:_(s8), %bb.4
.. .. New MI: %47:_(s8) = G_PHI %43:_(s8), %bb.3, %45:_(s8), %bb.4
.. .. New MI: %41:_(s16) = G_MERGE_VALUES %46:_(s8), %47:_(s8)
.. No debug info was present
Legalizing: %47:_(s8) = G_PHI %43:_(s8), %bb.3, %45:_(s8), %bb.4
Applying legalizer ruleset to: 55, Tys={s8, }, Opcode=55, MMOs={}
.. no match
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %46:_(s8) = G_PHI %42:_(s8), %bb.3, %44:_(s8), %bb.4
Applying legalizer ruleset to: 55, Tys={s8, }, Opcode=55, MMOs={}
.. no match
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %11:_(p0) = G_INTTOPTR %41:_(s16)
Applying legalizer ruleset to: 66, Tys={p0, s16, }, Opcode=66, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %40:_(s16) = G_PTRTOINT %26:_(p0)
Applying legalizer ruleset to: 65, Tys={s16, p0, }, Opcode=65, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %39:_(s16) = G_PTRTOINT %24:_(p0)
Applying legalizer ruleset to: 65, Tys={s16, p0, }, Opcode=65, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: G_BR %bb.4
Applying legalizer ruleset to: 184, Tys={}, Opcode=184, MMOs={}
.. fallback to legacy rules (no rules defined)
.. (legacy) Legal
.. Already legal
.. No debug info was present
Legalizing: G_BRCOND %10:_(s1), %bb.5
Applying legalizer ruleset to: 98, Tys={s1, }, Opcode=98, MMOs={}
.. match
.. .. Custom, 0, LLT_invalid
.. Custom legalization
.. .. Changing MI: G_BRCOND %10:_(s1), %bb.5
.. .. Changed MI: G_BRCOND_IMM %10:_(s1), %bb.5, 1
.. No debug info was present
Legalizing: G_STORE %8:_(p0), %4:_(p0) :: (store 2 into %ir.0, align 1, !tbaa !2)
.. opcode 80 is aliased to 74
Applying legalizer ruleset to: 80, Tys={p0, p0, }, Opcode=80, MMOs={16, }
.. no match
.. match
.. .. Custom, 0, LLT_invalid
.. Custom legalization
.. .. Changing MI: G_STORE %8:_(p0), %4:_(p0) :: (store 2 into %ir.0, align 1, !tbaa !2)
.. .. Changed MI: G_STORE %48:_(s16), %4:_(p0) :: (store 2 into %ir.0, align 1, !tbaa !2)
.. .. New MI: %48:_(s16) = G_PTRTOINT %8:_(p0)
.. No debug info was present
Legalizing: G_STORE %48:_(s16), %4:_(p0) :: (store 2 into %ir.0, align 1, !tbaa !2)
.. opcode 80 is aliased to 74
Applying legalizer ruleset to: 80, Tys={s16, p0, }, Opcode=80, MMOs={16, }
.. no match
.. no match
.. no match
.. match
.. .. NarrowScalar, 0, s8
.. Narrow scalar
CSEInfo::Recording new MI G_UNMERGE_VALUES
CSEInfo::Recording new MI G_CONSTANT
CSEInfo::Recording new MI G_PTR_ADD
.. .. Erasing: G_STORE %48:_(s16), %4:_(p0) :: (store 2 into %ir.0, align 1, !tbaa !2)
.. .. New MI: %49:_(s8), %50:_(s8) = G_UNMERGE_VALUES %48:_(s16)
.. .. New MI: G_STORE %49:_(s8), %4:_(p0) :: (store 1 into %ir.0, !tbaa !2)
.. .. New MI: %52:_(s16) = G_CONSTANT i16 1
.. .. New MI: %51:_(p0) = G_PTR_ADD %4:_, %52:_(s16)
.. .. New MI: G_STORE %50:_(s8), %51:_(p0) :: (store 1 into %ir.0 + 1, !tbaa !2)
.. No debug info was present
Legalizing: G_STORE %50:_(s8), %51:_(p0) :: (store 1 into %ir.0 + 1, !tbaa !2)
.. opcode 80 is aliased to 74
Applying legalizer ruleset to: 80, Tys={s8, p0, }, Opcode=80, MMOs={8, }
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %51:_(p0) = G_PTR_ADD %4:_, %52:_(s16)
Applying legalizer ruleset to: 177, Tys={p0, s16, }, Opcode=177, MMOs={}
.. match
.. .. Custom, 0, LLT_invalid
.. Custom legalization
CSEInfo::Recording new MI G_CONSTANT
.. .. Changing MI: %51:_(p0) = G_PTR_ADD %4:_, %52:_(s16)
CSEInfo::Recording new MI %51:_(p0) = G_PTR_ADD %4:_, %52:_(s16)
.. .. Changed MI: %51:_(p0) = G_INDEX %4:_, %53:_(s8)
.. .. New MI: %53:_(s8) = G_CONSTANT i8 1
.. No debug info was present
Legalizing: %53:_(s8) = G_CONSTANT i8 1
Applying legalizer ruleset to: 104, Tys={s8, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
%52:_(s16) = G_CONSTANT i16 1
Is dead; erasing.
.. .. Erasing: %52:_(s16) = G_CONSTANT i16 1
Legalizing: G_STORE %49:_(s8), %4:_(p0) :: (store 1 into %ir.0, !tbaa !2)
.. opcode 80 is aliased to 74
Applying legalizer ruleset to: 80, Tys={s8, p0, }, Opcode=80, MMOs={8, }
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %48:_(s16) = G_PTRTOINT %8:_(p0)
Applying legalizer ruleset to: 65, Tys={s16, p0, }, Opcode=65, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %10:_(s1) = G_ICMP intpred(eq), %9:_(s8), %2:_
Applying legalizer ruleset to: 118, Tys={s1, s8, }, Opcode=118, MMOs={}
.. match
.. .. Custom, 0, LLT_invalid
.. Custom legalization
CSEInfo::Recording new MI G_CONSTANT
CSEInfo::Recording new MI G_SBC
.. .. Erasing: %10:_(s1) = G_ICMP intpred(eq), %9:_(s8), %2:_
.. .. New MI: %54:_(s1) = G_CONSTANT i1 true
.. .. New MI: %55:_(s8), %56:_(s1), %57:_, %58:_, %59:_ = G_SBC %9:_, %2:_, %54:_
.. .. New MI: %10:_(s1) = COPY %59:_(s1)
.. No debug info was present
Legalizing: %54:_(s1) = G_CONSTANT i1 true
Applying legalizer ruleset to: 104, Tys={s1, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %9:_(s8) = G_FREEZE %0:_
.. opcode 68 is aliased to 54
Applying legalizer ruleset to: 68, Tys={s8, }, Opcode=68, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %8:_(p0) = G_PHI %17:_(p0), %bb.1, %21:_(p0), %bb.2
Applying legalizer ruleset to: 55, Tys={p0, }, Opcode=55, MMOs={}
.. match
.. .. Custom, 0, LLT_invalid
.. Custom legalization
.. .. Changing MI: %8:_(p0) = G_PHI %17:_(p0), %bb.1, %21:_(p0), %bb.2
.. .. Changed MI: %62:_(s16) = G_PHI %60:_(s16), %bb.1, %61:_(s16), %bb.2
.. .. New MI: %60:_(s16) = G_PTRTOINT %17:_(p0)
.. .. New MI: %61:_(s16) = G_PTRTOINT %21:_(p0)
.. .. New MI: %8:_(p0) = G_INTTOPTR %62:_(s16)
.. No debug info was present
Legalizing: %62:_(s16) = G_PHI %60:_(s16), %bb.1, %61:_(s16), %bb.2
Applying legalizer ruleset to: 55, Tys={s16, }, Opcode=55, MMOs={}
.. no match
.. no match
.. no match
.. no match
.. match
.. .. NarrowScalar, 0, s8
.. Narrow scalar
.. .. Changing MI: %62:_(s16) = G_PHI %60:_(s16), %bb.1, %61:_(s16), %bb.2
CSEInfo::Recording new MI G_UNMERGE_VALUES
CSEInfo::Recording new MI G_UNMERGE_VALUES
.. .. Changed MI: %62:_(s16) = G_PHI %60:_(s16), %bb.1, %61:_(s16), %bb.2
.. .. Erasing: %62:_(s16) = G_PHI %60:_(s16), %bb.1, %61:_(s16), %bb.2
.. .. New MI: %63:_(s8), %64:_(s8) = G_UNMERGE_VALUES %60:_(s16)
.. .. New MI: %65:_(s8), %66:_(s8) = G_UNMERGE_VALUES %61:_(s16)
.. .. New MI: %67:_(s8) = G_PHI %63:_(s8), %bb.1, %65:_(s8), %bb.2
.. .. New MI: %68:_(s8) = G_PHI %64:_(s8), %bb.1, %66:_(s8), %bb.2
.. .. New MI: %62:_(s16) = G_MERGE_VALUES %67:_(s8), %68:_(s8)
.. No debug info was present
Legalizing: %68:_(s8) = G_PHI %64:_(s8), %bb.1, %66:_(s8), %bb.2
Applying legalizer ruleset to: 55, Tys={s8, }, Opcode=55, MMOs={}
.. no match
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %67:_(s8) = G_PHI %63:_(s8), %bb.1, %65:_(s8), %bb.2
Applying legalizer ruleset to: 55, Tys={s8, }, Opcode=55, MMOs={}
.. no match
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %8:_(p0) = G_INTTOPTR %62:_(s16)
Applying legalizer ruleset to: 66, Tys={p0, s16, }, Opcode=66, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %61:_(s16) = G_PTRTOINT %21:_(p0)
Applying legalizer ruleset to: 65, Tys={s16, p0, }, Opcode=65, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %60:_(s16) = G_PTRTOINT %17:_(p0)
Applying legalizer ruleset to: 65, Tys={s16, p0, }, Opcode=65, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: G_BR %bb.2
Applying legalizer ruleset to: 184, Tys={}, Opcode=184, MMOs={}
.. fallback to legacy rules (no rules defined)
.. (legacy) Legal
.. Already legal
.. No debug info was present
Legalizing: G_BRCOND %3:_(s1), %bb.3
Applying legalizer ruleset to: 98, Tys={s1, }, Opcode=98, MMOs={}
.. match
.. .. Custom, 0, LLT_invalid
.. Custom legalization
.. .. Changing MI: G_BRCOND %3:_(s1), %bb.3
.. .. Changed MI: G_BRCOND_IMM %3:_(s1), %bb.3, 1
.. No debug info was present
Legalizing: %6:_(s8) = G_CONSTANT i8 2
Applying legalizer ruleset to: 104, Tys={s8, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %3:_(s1) = G_ICMP intpred(eq), %1:_(s8), %2:_
Applying legalizer ruleset to: 118, Tys={s1, s8, }, Opcode=118, MMOs={}
.. match
.. .. Custom, 0, LLT_invalid
.. Custom legalization
CSEInfo::Recording new MI G_CONSTANT
CSEInfo::Recording new MI G_SBC
.. .. Erasing: %3:_(s1) = G_ICMP intpred(eq), %1:_(s8), %2:_
.. .. New MI: %69:_(s1) = G_CONSTANT i1 true
.. .. New MI: %70:_(s8), %71:_(s1), %72:_, %73:_, %74:_ = G_SBC %1:_, %2:_, %69:_
.. .. New MI: %3:_(s1) = COPY %74:_(s1)
.. No debug info was present
Legalizing: %69:_(s1) = G_CONSTANT i1 true
Applying legalizer ruleset to: 104, Tys={s1, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %1:_(s8) = G_FREEZE %0:_
.. opcode 68 is aliased to 54
Applying legalizer ruleset to: 68, Tys={s8, }, Opcode=68, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %26:_(p0) = G_GLOBAL_VALUE @_ZN4SubA2fnEv
.. opcode 57 is aliased to 56
Applying legalizer ruleset to: 57, Tys={p0, }, Opcode=57, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %24:_(p0) = G_GLOBAL_VALUE @_ZN4SubB2fnEv
.. opcode 57 is aliased to 56
Applying legalizer ruleset to: 57, Tys={p0, }, Opcode=57, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %21:_(p0) = G_GLOBAL_VALUE @_ZTV4SubA + 4
.. opcode 57 is aliased to 56
Applying legalizer ruleset to: 57, Tys={p0, }, Opcode=57, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %17:_(p0) = G_GLOBAL_VALUE @_ZTV4SubB + 4
.. opcode 57 is aliased to 56
Applying legalizer ruleset to: 57, Tys={p0, }, Opcode=57, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %2:_(s8) = G_CONSTANT i8 0
Applying legalizer ruleset to: 104, Tys={s8, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
.. No debug info was present
Trying to combine: %62:_(s16) = G_MERGE_VALUES %67:_(s8), %68:_(s8)
.. Not combined, moving to instructions list
Trying to combine: %65:_(s8), %66:_(s8) = G_UNMERGE_VALUES %61:_(s16)
.. Not combined, moving to instructions list
Trying to combine: %63:_(s8), %64:_(s8) = G_UNMERGE_VALUES %60:_(s16)
.. Not combined, moving to instructions list
Trying to combine: %49:_(s8), %50:_(s8) = G_UNMERGE_VALUES %48:_(s16)
.. Not combined, moving to instructions list
Trying to combine: %41:_(s16) = G_MERGE_VALUES %46:_(s8), %47:_(s8)
.. Not combined, moving to instructions list
Trying to combine: %44:_(s8), %45:_(s8) = G_UNMERGE_VALUES %40:_(s16)
.. Not combined, moving to instructions list
Trying to combine: %42:_(s8), %43:_(s8) = G_UNMERGE_VALUES %39:_(s16)
.. Not combined, moving to instructions list
Trying to combine: %34:_(s16) = G_MERGE_VALUES %35:_(s8), %38:_(s8)
.. Not combined, moving to instructions list
Trying to combine: %27:_(s16) = G_MERGE_VALUES %28:_(s8), %31:_(s8)
.. Not combined, moving to instructions list
=== New Iteration ===
Legalizing: %27:_(s16) = G_MERGE_VALUES %28:_(s8), %31:_(s8)
Applying legalizer ruleset to: 61, Tys={s16, s8, }, Opcode=61, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %34:_(s16) = G_MERGE_VALUES %35:_(s8), %38:_(s8)
Applying legalizer ruleset to: 61, Tys={s16, s8, }, Opcode=61, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %42:_(s8), %43:_(s8) = G_UNMERGE_VALUES %39:_(s16)
Applying legalizer ruleset to: 59, Tys={s8, s16, }, Opcode=59, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %44:_(s8), %45:_(s8) = G_UNMERGE_VALUES %40:_(s16)
Applying legalizer ruleset to: 59, Tys={s8, s16, }, Opcode=59, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %41:_(s16) = G_MERGE_VALUES %46:_(s8), %47:_(s8)
Applying legalizer ruleset to: 61, Tys={s16, s8, }, Opcode=61, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %49:_(s8), %50:_(s8) = G_UNMERGE_VALUES %48:_(s16)
Applying legalizer ruleset to: 59, Tys={s8, s16, }, Opcode=59, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %63:_(s8), %64:_(s8) = G_UNMERGE_VALUES %60:_(s16)
Applying legalizer ruleset to: 59, Tys={s8, s16, }, Opcode=59, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %65:_(s8), %66:_(s8) = G_UNMERGE_VALUES %61:_(s16)
Applying legalizer ruleset to: 59, Tys={s8, s16, }, Opcode=59, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %62:_(s16) = G_MERGE_VALUES %67:_(s8), %68:_(s8)
Applying legalizer ruleset to: 61, Tys={s16, s8, }, Opcode=61, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
.. No debug info was present
Generic MI Combiner for: _Z11testIndCallc
Try combining %0:_(s8) = COPY $a
Try combining %2:_(s8) = G_CONSTANT i8 0
Try combining %17:_(p0) = G_GLOBAL_VALUE @_ZTV4SubB + 4
Try combining %21:_(p0) = G_GLOBAL_VALUE @_ZTV4SubA + 4
Try combining %24:_(p0) = G_GLOBAL_VALUE @_ZN4SubB2fnEv
Try combining %26:_(p0) = G_GLOBAL_VALUE @_ZN4SubA2fnEv
Try combining %1:_(s8) = G_FREEZE %0:_
Try combining %69:_(s1) = G_CONSTANT i1 true
Try combining %70:_(s8), %71:_(s1), %72:_, %73:_, %74:_ = G_SBC %1:_, %2:_, %69:_
Try combining %3:_(s1) = COPY %74:_(s1)
Erasing: %3:_(s1) = COPY %74:_(s1)
Changing: G_BRCOND_IMM %3:_(s1), %bb.3, 1
Changed: G_BRCOND_IMM %74:_(s1), %bb.3, 1
Try combining ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Try combining %6:_(s8) = G_CONSTANT i8 2
Try combining $a = COPY %6:_(s8)
Try combining $x = COPY %2:_(s8)
Try combining JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $a, implicit $x, implicit-def $rs1
Try combining %4:_(p0) = COPY $rs1
Try combining ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Try combining %60:_(s16) = G_PTRTOINT %17:_(p0)
Try combining %63:_(s8), %64:_(s8) = G_UNMERGE_VALUES %60:_(s16)
Try combining G_BRCOND_IMM %74:_(s1), %bb.3, 1
Try combining G_BR %bb.2
Try combining %61:_(s16) = G_PTRTOINT %21:_(p0)
Try combining %65:_(s8), %66:_(s8) = G_UNMERGE_VALUES %61:_(s16)
Try combining %67:_(s8) = G_PHI %63:_(s8), %bb.1, %65:_(s8), %bb.2
Try combining %68:_(s8) = G_PHI %64:_(s8), %bb.1, %66:_(s8), %bb.2
Try combining %62:_(s16) = G_MERGE_VALUES %67:_(s8), %68:_(s8)
Try combining %8:_(p0) = G_INTTOPTR %62:_(s16)
Try combining %9:_(s8) = G_FREEZE %0:_
Try combining %54:_(s1) = G_CONSTANT i1 true
Try combining %55:_(s8), %56:_(s1), %57:_, %58:_, %59:_ = G_SBC %9:_, %2:_, %54:_
Try combining %10:_(s1) = COPY %59:_(s1)
Erasing: %10:_(s1) = COPY %59:_(s1)
Changing: G_BRCOND_IMM %10:_(s1), %bb.5, 1
Changed: G_BRCOND_IMM %59:_(s1), %bb.5, 1
Try combining %48:_(s16) = G_PTRTOINT %8:_(p0)
Creating: COPY
Erasing: %48:_(s16) = G_PTRTOINT %8:_(p0)
Created: %48:_(s16) = COPY %62:_(s16)
Try combining %48:_(s16) = COPY %62:_(s16)
Erasing: %48:_(s16) = COPY %62:_(s16)
Changing: %49:_(s8), %50:_(s8) = G_UNMERGE_VALUES %48:_(s16)
CSEInfo::Recording new MI %49:_(s8), %50:_(s8) = G_UNMERGE_VALUES %48:_(s16)
Changed: %49:_(s8), %50:_(s8) = G_UNMERGE_VALUES %62:_(s16)
CSEInfo::Recording new MI %49:_(s8), %50:_(s8) = G_UNMERGE_VALUES %62:_(s16)
Try combining %49:_(s8), %50:_(s8) = G_UNMERGE_VALUES %62:_(s16)
Changing: G_STORE %49:_(s8), %4:_(p0) :: (store 1 into %ir.0, !tbaa !2)
Changed: G_STORE %67:_(s8), %4:_(p0) :: (store 1 into %ir.0, !tbaa !2)
Changing: G_STORE %50:_(s8), %51:_(p0) :: (store 1 into %ir.0 + 1, !tbaa !2)
Changed: G_STORE %68:_(s8), %51:_(p0) :: (store 1 into %ir.0 + 1, !tbaa !2)
Erasing: %67:_(s8), %68:_(s8) = G_UNMERGE_VALUES %62:_(s16)
Try combining G_STORE %67:_(s8), %4:_(p0) :: (store 1 into %ir.0, !tbaa !2)
Try combining %53:_(s8) = G_CONSTANT i8 1
Try combining %51:_(p0) = G_INDEX %4:_, %53:_(s8)
Try combining G_STORE %68:_(s8), %51:_(p0) :: (store 1 into %ir.0 + 1, !tbaa !2)
Try combining %39:_(s16) = G_PTRTOINT %24:_(p0)
Try combining %42:_(s8), %43:_(s8) = G_UNMERGE_VALUES %39:_(s16)
Try combining G_BRCOND_IMM %59:_(s1), %bb.5, 1
Try combining G_BR %bb.4
Try combining %40:_(s16) = G_PTRTOINT %26:_(p0)
Try combining %44:_(s8), %45:_(s8) = G_UNMERGE_VALUES %40:_(s16)
Try combining %46:_(s8) = G_PHI %42:_(s8), %bb.3, %44:_(s8), %bb.4
Try combining %47:_(s8) = G_PHI %43:_(s8), %bb.3, %45:_(s8), %bb.4
Try combining %41:_(s16) = G_MERGE_VALUES %46:_(s8), %47:_(s8)
Try combining %11:_(p0) = G_INTTOPTR %41:_(s16)
Try combining $rs8 = COPY %11:_(p0)
Try combining ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Try combining $rs1 = COPY %4:_(p0)
Try combining JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
Try combining ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Try combining %35:_(s8) = G_LOAD %4:_(p0) :: (load 1 from %ir.3, !tbaa !2)
Try combining %32:_(s8) = G_CONSTANT i8 1
Try combining %36:_(p0) = G_INDEX %4:_, %32:_(s8)
Try combining %38:_(s8) = G_LOAD %36:_(p0) :: (load 1 from %ir.3 + 1, !tbaa !2)
Try combining %34:_(s16) = G_MERGE_VALUES %35:_(s8), %38:_(s8)
Try combining %12:_(p0) = G_INTTOPTR %34:_(s16)
Try combining %33:_(s8) = G_CONSTANT i8 2
Try combining %14:_(p0) = G_INDEX %12:_, %33:_(s8)
Try combining %28:_(s8) = G_LOAD %14:_(p0) :: (load 1 from %ir.vfn3)
Try combining %29:_(p0) = G_INDEX %14:_, %32:_(s8)
Try combining %31:_(s8) = G_LOAD %29:_(p0) :: (load 1 from %ir.vfn3 + 1)
Try combining %27:_(s16) = G_MERGE_VALUES %28:_(s8), %31:_(s8)
Try combining %15:_(p0) = G_INTTOPTR %27:_(s16)
Try combining $rs8 = COPY %15:_(p0)
Try combining ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Try combining $rs1 = COPY %4:_(p0)
Try combining JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
Try combining ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Try combining RTS
%8:_(p0) = G_INTTOPTR %62:_(s16)
Is dead; erasing.
Erasing: %8:_(p0) = G_INTTOPTR %62:_(s16)
%62:_(s16) = G_MERGE_VALUES %67:_(s8), %68:_(s8)
Is dead; erasing.
Erasing: %62:_(s16) = G_MERGE_VALUES %67:_(s8), %68:_(s8)
Try combining %0:_(s8) = COPY $a
Try combining %2:_(s8) = G_CONSTANT i8 0
Try combining %17:_(p0) = G_GLOBAL_VALUE @_ZTV4SubB + 4
Try combining %21:_(p0) = G_GLOBAL_VALUE @_ZTV4SubA + 4
Try combining %24:_(p0) = G_GLOBAL_VALUE @_ZN4SubB2fnEv
Try combining %26:_(p0) = G_GLOBAL_VALUE @_ZN4SubA2fnEv
Try combining %1:_(s8) = G_FREEZE %0:_
Try combining %69:_(s1) = G_CONSTANT i1 true
Try combining %70:_(s8), %71:_(s1), %72:_, %73:_, %74:_ = G_SBC %1:_, %2:_, %69:_
Try combining ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Try combining %6:_(s8) = G_CONSTANT i8 2
Try combining $a = COPY %6:_(s8)
Try combining $x = COPY %2:_(s8)
Try combining JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $a, implicit $x, implicit-def $rs1
Try combining %4:_(p0) = COPY $rs1
Try combining ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Try combining %60:_(s16) = G_PTRTOINT %17:_(p0)
Try combining %63:_(s8), %64:_(s8) = G_UNMERGE_VALUES %60:_(s16)
Try combining G_BRCOND_IMM %74:_(s1), %bb.3, 1
Try combining G_BR %bb.2
Try combining %61:_(s16) = G_PTRTOINT %21:_(p0)
Try combining %65:_(s8), %66:_(s8) = G_UNMERGE_VALUES %61:_(s16)
Try combining %67:_(s8) = G_PHI %63:_(s8), %bb.1, %65:_(s8), %bb.2
Try combining %68:_(s8) = G_PHI %64:_(s8), %bb.1, %66:_(s8), %bb.2
Try combining %9:_(s8) = G_FREEZE %0:_
Try combining %54:_(s1) = G_CONSTANT i1 true
Try combining %55:_(s8), %56:_(s1), %57:_, %58:_, %59:_ = G_SBC %9:_, %2:_, %54:_
Try combining G_STORE %67:_(s8), %4:_(p0) :: (store 1 into %ir.0, !tbaa !2)
Try combining %53:_(s8) = G_CONSTANT i8 1
Try combining %51:_(p0) = G_INDEX %4:_, %53:_(s8)
Try combining G_STORE %68:_(s8), %51:_(p0) :: (store 1 into %ir.0 + 1, !tbaa !2)
Try combining %39:_(s16) = G_PTRTOINT %24:_(p0)
Try combining %42:_(s8), %43:_(s8) = G_UNMERGE_VALUES %39:_(s16)
Try combining G_BRCOND_IMM %59:_(s1), %bb.5, 1
Try combining G_BR %bb.4
Try combining %40:_(s16) = G_PTRTOINT %26:_(p0)
Try combining %44:_(s8), %45:_(s8) = G_UNMERGE_VALUES %40:_(s16)
Try combining %46:_(s8) = G_PHI %42:_(s8), %bb.3, %44:_(s8), %bb.4
Try combining %47:_(s8) = G_PHI %43:_(s8), %bb.3, %45:_(s8), %bb.4
Try combining %41:_(s16) = G_MERGE_VALUES %46:_(s8), %47:_(s8)
Try combining %11:_(p0) = G_INTTOPTR %41:_(s16)
Try combining $rs8 = COPY %11:_(p0)
Try combining ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Try combining $rs1 = COPY %4:_(p0)
Try combining JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
Try combining ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Try combining %35:_(s8) = G_LOAD %4:_(p0) :: (load 1 from %ir.3, !tbaa !2)
Try combining %32:_(s8) = G_CONSTANT i8 1
Try combining %36:_(p0) = G_INDEX %4:_, %32:_(s8)
Try combining %38:_(s8) = G_LOAD %36:_(p0) :: (load 1 from %ir.3 + 1, !tbaa !2)
Try combining %34:_(s16) = G_MERGE_VALUES %35:_(s8), %38:_(s8)
Try combining %12:_(p0) = G_INTTOPTR %34:_(s16)
Try combining %33:_(s8) = G_CONSTANT i8 2
Try combining %14:_(p0) = G_INDEX %12:_, %33:_(s8)
Try combining %28:_(s8) = G_LOAD %14:_(p0) :: (load 1 from %ir.vfn3)
Try combining %29:_(p0) = G_INDEX %14:_, %32:_(s8)
Try combining %31:_(s8) = G_LOAD %29:_(p0) :: (load 1 from %ir.vfn3 + 1)
Try combining %27:_(s16) = G_MERGE_VALUES %28:_(s8), %31:_(s8)
Try combining %15:_(p0) = G_INTTOPTR %27:_(s16)
Try combining $rs8 = COPY %15:_(p0)
Try combining ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Try combining $rs1 = COPY %4:_(p0)
Try combining JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
Try combining ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Try combining RTS
CSEInfo::CSE Hit for Opc 104 : 2
Handling G_SELECTs in: _Z11testIndCallc
Iteratively lowering G_SELECTs.
Assign register banks for: _Z11testIndCallc
Applying legalizer ruleset to: 104, Tys={s8, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 57 is aliased to 56
Applying legalizer ruleset to: 57, Tys={p0, }, Opcode=57, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 57 is aliased to 56
Applying legalizer ruleset to: 57, Tys={p0, }, Opcode=57, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 57 is aliased to 56
Applying legalizer ruleset to: 57, Tys={p0, }, Opcode=57, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 57 is aliased to 56
Applying legalizer ruleset to: 57, Tys={p0, }, Opcode=57, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 68 is aliased to 54
Applying legalizer ruleset to: 68, Tys={s8, }, Opcode=68, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 104, Tys={s1, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 104, Tys={s8, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 65, Tys={s16, p0, }, Opcode=65, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 59, Tys={s8, s16, }, Opcode=59, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 184, Tys={}, Opcode=184, MMOs={}
.. fallback to legacy rules (no rules defined)
.. (legacy) Legal
Applying legalizer ruleset to: 65, Tys={s16, p0, }, Opcode=65, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 59, Tys={s8, s16, }, Opcode=59, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 55, Tys={s8, }, Opcode=55, MMOs={}
.. no match
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 55, Tys={s8, }, Opcode=55, MMOs={}
.. no match
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 68 is aliased to 54
Applying legalizer ruleset to: 68, Tys={s8, }, Opcode=68, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 104, Tys={s1, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 80 is aliased to 74
Applying legalizer ruleset to: 80, Tys={s8, p0, }, Opcode=80, MMOs={8, }
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 104, Tys={s8, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 80 is aliased to 74
Applying legalizer ruleset to: 80, Tys={s8, p0, }, Opcode=80, MMOs={8, }
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 65, Tys={s16, p0, }, Opcode=65, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 59, Tys={s8, s16, }, Opcode=59, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 184, Tys={}, Opcode=184, MMOs={}
.. fallback to legacy rules (no rules defined)
.. (legacy) Legal
Applying legalizer ruleset to: 65, Tys={s16, p0, }, Opcode=65, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 59, Tys={s8, s16, }, Opcode=59, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 55, Tys={s8, }, Opcode=55, MMOs={}
.. no match
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 55, Tys={s8, }, Opcode=55, MMOs={}
.. no match
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 61, Tys={s16, s8, }, Opcode=61, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 66, Tys={p0, s16, }, Opcode=66, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 74, Tys={s8, p0, }, Opcode=74, MMOs={8, }
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 104, Tys={s8, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 74, Tys={s8, p0, }, Opcode=74, MMOs={8, }
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 61, Tys={s16, s8, }, Opcode=61, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 66, Tys={p0, s16, }, Opcode=66, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 104, Tys={s8, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 74, Tys={s8, p0, }, Opcode=74, MMOs={8, }
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 74, Tys={s8, p0, }, Opcode=74, MMOs={8, }
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 61, Tys={s16, s8, }, Opcode=61, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 66, Tys={p0, s16, }, Opcode=66, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Assign: %0:_(s8) = COPY $a
Evaluating mapping cost for: %0:_(s8) = COPY $a
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Assign: %2:_(s8) = G_CONSTANT i8 0
Evaluating mapping cost for: %2:_(s8) = G_CONSTANT i8 0
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 is not a register, nothing to be done
Assign: %17:_(p0) = G_GLOBAL_VALUE @_ZTV4SubB + 4
Evaluating mapping cost for: %17:_(p0) = G_GLOBAL_VALUE @_ZTV4SubB + 4
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 is not a register, nothing to be done
Assign: %21:_(p0) = G_GLOBAL_VALUE @_ZTV4SubA + 4
Evaluating mapping cost for: %21:_(p0) = G_GLOBAL_VALUE @_ZTV4SubA + 4
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 is not a register, nothing to be done
Assign: %24:_(p0) = G_GLOBAL_VALUE @_ZN4SubB2fnEv
Evaluating mapping cost for: %24:_(p0) = G_GLOBAL_VALUE @_ZN4SubB2fnEv
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 is not a register, nothing to be done
Assign: %26:_(p0) = G_GLOBAL_VALUE @_ZN4SubA2fnEv
Evaluating mapping cost for: %26:_(p0) = G_GLOBAL_VALUE @_ZN4SubA2fnEv
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 is not a register, nothing to be done
Assign: %1:_(s8) = G_FREEZE %0:any
Evaluating mapping cost for: %1:_(s8) = G_FREEZE %0:any
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
Assign: %69:_(s1) = G_CONSTANT i1 true
Evaluating mapping cost for: %69:_(s1) = G_CONSTANT i1 true
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 is not a register, nothing to be done
Assign: %70:_(s8), %71:_(s1), %72:_, %73:_, %74:_ = G_SBC %1:any, %2:any, %69:any
Evaluating mapping cost for: %70:_(s8), %71:_(s1), %72:_, %73:_, %74:_ = G_SBC %1:any, %2:any, %69:any
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 3 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 4 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 5 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 6 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 7 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: none against Any
=> is free (simple assignment).
Opd2
Does assignment already match: none against Any
=> is free (simple assignment).
Opd3
Does assignment already match: none against Any
=> is free (simple assignment).
Opd4
Does assignment already match: none against Any
=> is free (simple assignment).
Opd5
Does assignment already match: Any against Any
=> is free (match).
Opd6
Does assignment already match: Any against Any
=> is free (match).
Opd7
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 3 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 4 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 5 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 6 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 7 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
OpIdx 3 has not been repaired, nothing to be done
OpIdx 4 has not been repaired, nothing to be done
OpIdx 5 has not been repaired, nothing to be done
OpIdx 6 has not been repaired, nothing to be done
OpIdx 7 has not been repaired, nothing to be done
Assign: %6:_(s8) = G_CONSTANT i8 2
Evaluating mapping cost for: %6:_(s8) = G_CONSTANT i8 2
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 is not a register, nothing to be done
Assign: $a = COPY %6:any(s8)
Evaluating mapping cost for: $a = COPY %6:any(s8)
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Opd0
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Assign: $x = COPY %2:any(s8)
Evaluating mapping cost for: $x = COPY %2:any(s8)
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Opd0
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Assign: %4:_(p0) = COPY $rs1
Evaluating mapping cost for: %4:_(p0) = COPY $rs1
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Assign: %60:_(s16) = G_PTRTOINT %17:any(p0)
Evaluating mapping cost for: %60:_(s16) = G_PTRTOINT %17:any(p0)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
Assign: %63:_(s8), %64:_(s8) = G_UNMERGE_VALUES %60:any(s16)
Evaluating mapping cost for: %63:_(s8), %64:_(s8) = G_UNMERGE_VALUES %60:any(s16)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: none against Any
=> is free (simple assignment).
Opd2
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: G_BRCOND_IMM %74:any(s1), %bb.3, 1
Evaluating mapping cost for: G_BRCOND_IMM %74:any(s1), %bb.3, 1
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }, { Idx: 2 Map: #BreakDown: 0 }
Opd0
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }, { Idx: 2 Map: #BreakDown: 0 }
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 is not a register, nothing to be done
OpIdx 2 is not a register, nothing to be done
Assign: G_BR %bb.2
Evaluating mapping cost for: G_BR %bb.2
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 0 }
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 0 }
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping:
Applying default-like mapping
OpIdx 0 is not a register, nothing to be done
Assign: %61:_(s16) = G_PTRTOINT %21:any(p0)
Evaluating mapping cost for: %61:_(s16) = G_PTRTOINT %21:any(p0)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
Assign: %65:_(s8), %66:_(s8) = G_UNMERGE_VALUES %61:any(s16)
Evaluating mapping cost for: %65:_(s8), %66:_(s8) = G_UNMERGE_VALUES %61:any(s16)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: none against Any
=> is free (simple assignment).
Opd2
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: %67:_(s8) = G_PHI %63:any(s8), %bb.1, %65:any(s8), %bb.2
Evaluating mapping cost for: %67:_(s8) = G_PHI %63:any(s8), %bb.1, %65:any(s8), %bb.2
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Assign: %68:_(s8) = G_PHI %64:any(s8), %bb.1, %66:any(s8), %bb.2
Evaluating mapping cost for: %68:_(s8) = G_PHI %64:any(s8), %bb.1, %66:any(s8), %bb.2
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Assign: %9:_(s8) = G_FREEZE %0:any
Evaluating mapping cost for: %9:_(s8) = G_FREEZE %0:any
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
Assign: %54:_(s1) = G_CONSTANT i1 true
Evaluating mapping cost for: %54:_(s1) = G_CONSTANT i1 true
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 is not a register, nothing to be done
Assign: %55:_(s8), %56:_(s1), %57:_, %58:_, %59:_ = G_SBC %9:any, %2:any, %54:any
Evaluating mapping cost for: %55:_(s8), %56:_(s1), %57:_, %58:_, %59:_ = G_SBC %9:any, %2:any, %54:any
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 3 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 4 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 5 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 6 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 7 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: none against Any
=> is free (simple assignment).
Opd2
Does assignment already match: none against Any
=> is free (simple assignment).
Opd3
Does assignment already match: none against Any
=> is free (simple assignment).
Opd4
Does assignment already match: none against Any
=> is free (simple assignment).
Opd5
Does assignment already match: Any against Any
=> is free (match).
Opd6
Does assignment already match: Any against Any
=> is free (match).
Opd7
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 3 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 4 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 5 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 6 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 7 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
OpIdx 3 has not been repaired, nothing to be done
OpIdx 4 has not been repaired, nothing to be done
OpIdx 5 has not been repaired, nothing to be done
OpIdx 6 has not been repaired, nothing to be done
OpIdx 7 has not been repaired, nothing to be done
Assign: G_STORE %67:any(s8), %4:any(p0) :: (store 1 into %ir.0, !tbaa !2)
Evaluating mapping cost for: G_STORE %67:any(s8), %4:any(p0) :: (store 1 into %ir.0, !tbaa !2)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: Any against Any
=> is free (match).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
Assign: %53:_(s8) = G_CONSTANT i8 1
Evaluating mapping cost for: %53:_(s8) = G_CONSTANT i8 1
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 is not a register, nothing to be done
Assign: %51:_(p0) = G_INDEX %4:any, %53:any(s8)
Evaluating mapping cost for: %51:_(p0) = G_INDEX %4:any, %53:any(s8)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Opd2
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: G_STORE %68:any(s8), %51:any(p0) :: (store 1 into %ir.0 + 1, !tbaa !2)
Evaluating mapping cost for: G_STORE %68:any(s8), %51:any(p0) :: (store 1 into %ir.0 + 1, !tbaa !2)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: Any against Any
=> is free (match).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
Assign: %39:_(s16) = G_PTRTOINT %24:any(p0)
Evaluating mapping cost for: %39:_(s16) = G_PTRTOINT %24:any(p0)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
Assign: %42:_(s8), %43:_(s8) = G_UNMERGE_VALUES %39:any(s16)
Evaluating mapping cost for: %42:_(s8), %43:_(s8) = G_UNMERGE_VALUES %39:any(s16)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: none against Any
=> is free (simple assignment).
Opd2
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: G_BRCOND_IMM %59:any(s1), %bb.5, 1
Evaluating mapping cost for: G_BRCOND_IMM %59:any(s1), %bb.5, 1
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }, { Idx: 2 Map: #BreakDown: 0 }
Opd0
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 0], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }, { Idx: 2 Map: #BreakDown: 0 }
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 is not a register, nothing to be done
OpIdx 2 is not a register, nothing to be done
Assign: G_BR %bb.4
Evaluating mapping cost for: G_BR %bb.4
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 0 }
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 0 }
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping:
Applying default-like mapping
OpIdx 0 is not a register, nothing to be done
Assign: %40:_(s16) = G_PTRTOINT %26:any(p0)
Evaluating mapping cost for: %40:_(s16) = G_PTRTOINT %26:any(p0)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
Assign: %44:_(s8), %45:_(s8) = G_UNMERGE_VALUES %40:any(s16)
Evaluating mapping cost for: %44:_(s8), %45:_(s8) = G_UNMERGE_VALUES %40:any(s16)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: none against Any
=> is free (simple assignment).
Opd2
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: %46:_(s8) = G_PHI %42:any(s8), %bb.3, %44:any(s8), %bb.4
Evaluating mapping cost for: %46:_(s8) = G_PHI %42:any(s8), %bb.3, %44:any(s8), %bb.4
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Assign: %47:_(s8) = G_PHI %43:any(s8), %bb.3, %45:any(s8), %bb.4
Evaluating mapping cost for: %47:_(s8) = G_PHI %43:any(s8), %bb.3, %45:any(s8), %bb.4
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Assign: %41:_(s16) = G_MERGE_VALUES %46:any(s8), %47:any(s8)
Evaluating mapping cost for: %41:_(s16) = G_MERGE_VALUES %46:any(s8), %47:any(s8)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Opd2
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: %11:_(p0) = G_INTTOPTR %41:any(s16)
Evaluating mapping cost for: %11:_(p0) = G_INTTOPTR %41:any(s16)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
Assign: $rs8 = COPY %11:any(p0)
Evaluating mapping cost for: $rs8 = COPY %11:any(p0)
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Assign: $rs1 = COPY %4:any(p0)
Evaluating mapping cost for: $rs1 = COPY %4:any(p0)
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Assign: %35:_(s8) = G_LOAD %4:any(p0) :: (load 1 from %ir.3, !tbaa !2)
Evaluating mapping cost for: %35:_(s8) = G_LOAD %4:any(p0) :: (load 1 from %ir.3, !tbaa !2)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
Assign: %32:_(s8) = G_CONSTANT i8 1
Evaluating mapping cost for: %32:_(s8) = G_CONSTANT i8 1
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 is not a register, nothing to be done
Assign: %36:_(p0) = G_INDEX %4:any, %32:any(s8)
Evaluating mapping cost for: %36:_(p0) = G_INDEX %4:any, %32:any(s8)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Opd2
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: %38:_(s8) = G_LOAD %36:any(p0) :: (load 1 from %ir.3 + 1, !tbaa !2)
Evaluating mapping cost for: %38:_(s8) = G_LOAD %36:any(p0) :: (load 1 from %ir.3 + 1, !tbaa !2)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
Assign: %34:_(s16) = G_MERGE_VALUES %35:any(s8), %38:any(s8)
Evaluating mapping cost for: %34:_(s16) = G_MERGE_VALUES %35:any(s8), %38:any(s8)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Opd2
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: %12:_(p0) = G_INTTOPTR %34:any(s16)
Evaluating mapping cost for: %12:_(p0) = G_INTTOPTR %34:any(s16)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
Assign: %33:_(s8) = G_CONSTANT i8 2
Evaluating mapping cost for: %33:_(s8) = G_CONSTANT i8 2
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 0 }
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 is not a register, nothing to be done
Assign: %14:_(p0) = G_INDEX %12:any, %33:any(s8)
Evaluating mapping cost for: %14:_(p0) = G_INDEX %12:any, %33:any(s8)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Opd2
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: %28:_(s8) = G_LOAD %14:any(p0) :: (load 1 from %ir.vfn3)
Evaluating mapping cost for: %28:_(s8) = G_LOAD %14:any(p0) :: (load 1 from %ir.vfn3)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
Assign: %29:_(p0) = G_INDEX %14:any, %32:any(s8)
Evaluating mapping cost for: %29:_(p0) = G_INDEX %14:any, %32:any(s8)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Opd2
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: %31:_(s8) = G_LOAD %29:any(p0) :: (load 1 from %ir.vfn3 + 1)
Evaluating mapping cost for: %31:_(s8) = G_LOAD %29:any(p0) :: (load 1 from %ir.vfn3 + 1)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
Assign: %27:_(s16) = G_MERGE_VALUES %28:any(s8), %31:any(s8)
Evaluating mapping cost for: %27:_(s16) = G_MERGE_VALUES %28:any(s8), %31:any(s8)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Opd2
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}, { Idx: 2 Map: #BreakDown: 1 [[0, 7], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: %15:_(p0) = G_INTTOPTR %27:any(s16)
Evaluating mapping cost for: %15:_(p0) = G_INTTOPTR %27:any(s16)
With: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Opd1
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 1 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}, { Idx: 1 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 1 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
Assign: $rs8 = COPY %15:any(p0)
Evaluating mapping cost for: $rs8 = COPY %15:any(p0)
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Assign: $rs1 = COPY %4:any(p0)
Evaluating mapping cost for: $rs1 = COPY %4:any(p0)
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Localize instructions for: _Z11testIndCallc
Should localize: %6:any(s8) = G_CONSTANT i8 2
Checking use: $a = COPY %6:any(s8)
#Opd: 1
Should localize: %69:any(s1) = G_CONSTANT i1 true
Checking use: %70:any(s8), %71:any(s1), %72:any, %73:any, %74:any = G_SBC %1:any, %2:any, %69:any
#Opd: 7
Should localize: %26:any(p0) = G_GLOBAL_VALUE @_ZN4SubA2fnEv
Checking use: %40:any(s16) = G_PTRTOINT %26:any(p0)
#Opd: 1
Fixing non-local use
Inserted: %75:any(p0) = G_GLOBAL_VALUE @_ZN4SubA2fnEv
Update use with: %75
Should localize: %24:any(p0) = G_GLOBAL_VALUE @_ZN4SubB2fnEv
Checking use: %39:any(s16) = G_PTRTOINT %24:any(p0)
#Opd: 1
Fixing non-local use
Inserted: %76:any(p0) = G_GLOBAL_VALUE @_ZN4SubB2fnEv
Update use with: %76
Should localize: %21:any(p0) = G_GLOBAL_VALUE @_ZTV4SubA + 4
Checking use: %61:any(s16) = G_PTRTOINT %21:any(p0)
#Opd: 1
Fixing non-local use
Inserted: %77:any(p0) = G_GLOBAL_VALUE @_ZTV4SubA + 4
Update use with: %77
Should localize: %17:any(p0) = G_GLOBAL_VALUE @_ZTV4SubB + 4
Checking use: %60:any(s16) = G_PTRTOINT %17:any(p0)
#Opd: 1
Should localize: %2:any(s8) = G_CONSTANT i8 0
Checking use: $x = COPY %2:any(s8)
#Opd: 1
Checking use: %55:any(s8), %56:any(s1), %57:any, %58:any, %59:any = G_SBC %9:any, %2:any, %54:any
#Opd: 6
Fixing non-local use
Inserted: %78:any(s8) = G_CONSTANT i8 0
Update use with: %78
Checking use: %70:any(s8), %71:any(s1), %72:any, %73:any, %74:any = G_SBC %1:any, %2:any, %69:any
#Opd: 6
Intra-block: moving %6:any(s8) = G_CONSTANT i8 2
before $a = COPY %6:any(s8)
Intra-block: moving %69:any(s1) = G_CONSTANT i1 true
before %70:any(s8), %71:any(s1), %72:any, %73:any, %74:any = G_SBC %1:any, %2:any, %69:any
Intra-block: moving %75:any(p0) = G_GLOBAL_VALUE @_ZN4SubA2fnEv
before %40:any(s16) = G_PTRTOINT %75:any(p0)
Intra-block: moving %76:any(p0) = G_GLOBAL_VALUE @_ZN4SubB2fnEv
before %39:any(s16) = G_PTRTOINT %76:any(p0)
Intra-block: moving %77:any(p0) = G_GLOBAL_VALUE @_ZTV4SubA + 4
before %61:any(s16) = G_PTRTOINT %77:any(p0)
Intra-block: moving %17:any(p0) = G_GLOBAL_VALUE @_ZTV4SubB + 4
before %60:any(s16) = G_PTRTOINT %17:any(p0)
Intra-block: moving %2:any(s8) = G_CONSTANT i8 0
before %70:any(s8), %71:any(s1), %72:any, %73:any, %74:any = G_SBC %1:any, %2:any, %69:any
Intra-block: moving %78:any(s8) = G_CONSTANT i8 0
before %55:any(s8), %56:any(s1), %57:any, %58:any, %59:any = G_SBC %9:any, %78:any, %54:any
Selecting function: _Z11testIndCallc
.. opcode 57 is aliased to 56
Applying legalizer ruleset to: 57, Tys={p0, }, Opcode=57, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 57 is aliased to 56
Applying legalizer ruleset to: 57, Tys={p0, }, Opcode=57, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 57 is aliased to 56
Applying legalizer ruleset to: 57, Tys={p0, }, Opcode=57, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 68 is aliased to 54
Applying legalizer ruleset to: 68, Tys={s8, }, Opcode=68, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 104, Tys={s1, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 104, Tys={s8, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 104, Tys={s8, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 57 is aliased to 56
Applying legalizer ruleset to: 57, Tys={p0, }, Opcode=57, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 65, Tys={s16, p0, }, Opcode=65, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 59, Tys={s8, s16, }, Opcode=59, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 184, Tys={}, Opcode=184, MMOs={}
.. fallback to legacy rules (no rules defined)
.. (legacy) Legal
.. opcode 57 is aliased to 56
Applying legalizer ruleset to: 57, Tys={p0, }, Opcode=57, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 65, Tys={s16, p0, }, Opcode=65, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 59, Tys={s8, s16, }, Opcode=59, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 55, Tys={s8, }, Opcode=55, MMOs={}
.. no match
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 55, Tys={s8, }, Opcode=55, MMOs={}
.. no match
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 68 is aliased to 54
Applying legalizer ruleset to: 68, Tys={s8, }, Opcode=68, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 104, Tys={s1, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 104, Tys={s8, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 80 is aliased to 74
Applying legalizer ruleset to: 80, Tys={s8, p0, }, Opcode=80, MMOs={8, }
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 104, Tys={s8, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 80 is aliased to 74
Applying legalizer ruleset to: 80, Tys={s8, p0, }, Opcode=80, MMOs={8, }
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 57 is aliased to 56
Applying legalizer ruleset to: 57, Tys={p0, }, Opcode=57, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 65, Tys={s16, p0, }, Opcode=65, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 59, Tys={s8, s16, }, Opcode=59, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 184, Tys={}, Opcode=184, MMOs={}
.. fallback to legacy rules (no rules defined)
.. (legacy) Legal
.. opcode 57 is aliased to 56
Applying legalizer ruleset to: 57, Tys={p0, }, Opcode=57, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 65, Tys={s16, p0, }, Opcode=65, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 59, Tys={s8, s16, }, Opcode=59, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 55, Tys={s8, }, Opcode=55, MMOs={}
.. no match
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 55, Tys={s8, }, Opcode=55, MMOs={}
.. no match
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 61, Tys={s16, s8, }, Opcode=61, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 66, Tys={p0, s16, }, Opcode=66, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 74, Tys={s8, p0, }, Opcode=74, MMOs={8, }
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 104, Tys={s8, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 74, Tys={s8, p0, }, Opcode=74, MMOs={8, }
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 61, Tys={s16, s8, }, Opcode=61, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 66, Tys={p0, s16, }, Opcode=66, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 104, Tys={s8, }, Opcode=104, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 74, Tys={s8, p0, }, Opcode=74, MMOs={8, }
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 74, Tys={s8, p0, }, Opcode=74, MMOs={8, }
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 61, Tys={s16, s8, }, Opcode=61, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: 66, Tys={p0, s16, }, Opcode=66, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Selecting:
RTS
Into:
RTS
Selecting:
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Into:
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Selecting:
JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
Into:
JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
Selecting:
$rs1 = COPY %4:any(p0)
Into:
$rs1 = COPY %4:any(p0)
Selecting:
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Into:
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Selecting:
$rs8 = COPY %15:any(p0)
Into:
$rs8 = COPY %15:any(p0)
Selecting:
%15:any(p0) = G_INTTOPTR %27:any(s16)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=66
1272: GIM_Reject
1272: Rejected
Converting operand: %15:any
Converting operand: %27:any
Into:
%15:imag16(p0) = COPY %27:any(s16)
Selecting:
%27:any(s16) = G_MERGE_VALUES %28:any(s8), %31:any(s8)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=61
1272: GIM_Reject
1272: Rejected
Into:
%27:imag16(s16) = REG_SEQUENCE %28:any(s8), %subreg.sublo, %31:any(s8), %subreg.subhi
Selecting:
%31:any(s8) = G_LOAD %29:any(p0) :: (load 1 from %ir.vfn3 + 1)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=74
1272: GIM_Reject
1272: Rejected
Converting operand: %31:any
Converting operand: %14:any
Converting operand: %32:any
Into:
%31:ac(s8) = LDYIndir %14:imag16(p0), %32:yc(s8) :: (load 1 from %ir.vfn3 + 1)
Selecting:
%29:any(p0) = G_INDEX %14:imag16, %32:yc(s8)
Is dead; erasing.
Selecting:
%28:any(s8) = G_LOAD %14:imag16(p0) :: (load 1 from %ir.vfn3)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=74
1272: GIM_Reject
1272: Rejected
Converting operand: %28:any
Converting operand: %12:any
Converting operand: %33:any
Into:
%28:ac(s8) = LDYIndir %12:imag16(p0), %33:yc(s8) :: (load 1 from %ir.vfn3)
Selecting:
%14:imag16(p0) = G_INDEX %12:imag16, %33:yc(s8)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=259
1272: GIM_Reject
1272: Rejected
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=122
1272: GIM_Reject
1272: Rejected
Converting operand: %85:any
Converting operand: %86:any
Converting operand: %87:_
Converting operand: %80:any(tied-def 0)
Converting operand: %83:any(tied-def 0)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=122
1272: GIM_Reject
1272: Rejected
Converting operand: %82:any
Converting operand: %83:cc
Converting operand: %88:_
Converting operand: %79:any(tied-def 0)
Converting operand: %81:any(tied-def 0)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=104
1197: GIM_SwitchType(MIs[0]->getOperand(0), [0, 2), Default=1243, JumpTable...) // Got=s1
1200: Begin try-block
1205: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=1)
1208: GIR_BuildMI(OutMIs[0], 273)
1212: GIR_Copy(OutMIs[0], MIs[0], 0)
1215: GIR_CopyConstantAsSImm(OutMIs[0], MIs[0])
1217: GIR_EraseFromParent(MIs[0])
Converting operand: %81:cc
1219: GIR_ConstrainSelectedInstOperands(OutMIs[0])
1220: GIR_Done
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=59
1272: GIM_Reject
1272: Rejected
Into:
%79:ac(s8) = COPY %12.sublo:imag16(p0)
%80:ac(s8) = COPY %12.subhi:imag16(p0)
%81:cc(s1) = LDImm1 0
%82:ac(s8), %83:cc(s1), %88:vc(s1) = ADCImm %79:ac(tied-def 0)(s8), 2, %81:cc(tied-def 1)(s1)
%85:ac(s8), %86:cc(s1), %87:vc(s1) = ADCImm %80:ac(tied-def 0)(s8), 0, %83:cc(tied-def 1)(s1)
%14:imag16(p0) = REG_SEQUENCE %82:ac(s8), %subreg.sublo, %85:ac(s8), %subreg.subhi
Selecting:
%33:yc(s8) = G_CONSTANT i8 2
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=104
1197: GIM_SwitchType(MIs[0]->getOperand(0), [0, 2), Default=1243, JumpTable...) // Got=s8
1222: Begin try-block
1227: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=11)
1230: GIR_BuildMI(OutMIs[0], 272)
1234: GIR_Copy(OutMIs[0], MIs[0], 0)
1237: GIR_CopyConstantAsSImm(OutMIs[0], MIs[0])
1239: GIR_EraseFromParent(MIs[0])
Converting operand: %33:yc
1241: GIR_ConstrainSelectedInstOperands(OutMIs[0])
1242: GIR_Done
Into:
%33:yc(s8) = LDImm 2
Selecting:
%12:imag16(p0) = G_INTTOPTR %34:any(s16)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=66
1272: GIM_Reject
1272: Rejected
Converting operand: %12:imag16
Converting operand: %34:any
Into:
%12:imag16(p0) = COPY %34:any(s16)
Selecting:
%34:any(s16) = G_MERGE_VALUES %35:any(s8), %38:any(s8)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=61
1272: GIM_Reject
1272: Rejected
Into:
%34:imag16(s16) = REG_SEQUENCE %35:any(s8), %subreg.sublo, %38:any(s8), %subreg.subhi
Selecting:
%38:any(s8) = G_LOAD %36:any(p0) :: (load 1 from %ir.3 + 1, !tbaa !2)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=74
1272: GIM_Reject
1272: Rejected
Converting operand: %38:any
Converting operand: %4:any
Converting operand: %32:yc
Into:
%38:ac(s8) = LDYIndir %4:imag16(p0), %32:yc(s8) :: (load 1 from %ir.3 + 1, !tbaa !2)
Selecting:
%36:any(p0) = G_INDEX %4:imag16, %32:yc(s8)
Is dead; erasing.
Selecting:
%32:yc(s8) = G_CONSTANT i8 1
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=104
1197: GIM_SwitchType(MIs[0]->getOperand(0), [0, 2), Default=1243, JumpTable...) // Got=s8
1222: Begin try-block
1227: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=11)
1230: GIR_BuildMI(OutMIs[0], 272)
1234: GIR_Copy(OutMIs[0], MIs[0], 0)
1237: GIR_CopyConstantAsSImm(OutMIs[0], MIs[0])
1239: GIR_EraseFromParent(MIs[0])
Converting operand: %32:yc
1241: GIR_ConstrainSelectedInstOperands(OutMIs[0])
1242: GIR_Done
Into:
%32:yc(s8) = LDImm 1
Selecting:
%35:any(s8) = G_LOAD %4:imag16(p0) :: (load 1 from %ir.3, !tbaa !2)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=74
1272: GIM_Reject
1272: Rejected
Converting operand: %35:any
Converting operand: %4:imag16
Converting operand: %89:_
Into:
%89:yc(s8) = LDImm 0
%35:ac(s8) = LDYIndir %4:imag16(p0), %89:yc(s8) :: (load 1 from %ir.3, !tbaa !2)
Selecting:
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Into:
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Selecting:
JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
Into:
JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
Selecting:
$rs1 = COPY %4:imag16(p0)
Into:
$rs1 = COPY %4:imag16(p0)
Selecting:
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Into:
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Selecting:
$rs8 = COPY %11:any(p0)
Into:
$rs8 = COPY %11:any(p0)
Selecting:
%11:any(p0) = G_INTTOPTR %41:any(s16)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=66
1272: GIM_Reject
1272: Rejected
Converting operand: %11:any
Converting operand: %41:any
Into:
%11:imag16(p0) = COPY %41:any(s16)
Selecting:
%41:any(s16) = G_MERGE_VALUES %46:any(s8), %47:any(s8)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=61
1272: GIM_Reject
1272: Rejected
Into:
%41:imag16(s16) = REG_SEQUENCE %46:any(s8), %subreg.sublo, %47:any(s8), %subreg.subhi
Selecting:
%47:any(s8) = G_PHI %43:any(s8), %bb.3, %45:any(s8), %bb.4
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=55
1272: GIM_Reject
1272: Rejected
Converting operand: %47:any
Converting operand: %43:any
Converting operand: %45:any
Into:
%47:anyi8(s8) = PHI %43:any(s8), %bb.3, %45:any(s8), %bb.4
Selecting:
%46:any(s8) = G_PHI %42:any(s8), %bb.3, %44:any(s8), %bb.4
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=55
1272: GIM_Reject
1272: Rejected
Converting operand: %46:any
Converting operand: %42:any
Converting operand: %44:any
Into:
%46:anyi8(s8) = PHI %42:any(s8), %bb.3, %44:any(s8), %bb.4
Selecting:
%44:any(s8), %45:any(s8) = G_UNMERGE_VALUES %40:any(s16)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=59
1272: GIM_Reject
1272: Rejected
Into:
%44:anyi8(s8) = COPY %40.sublo:any(s16)
%45:anyi8(s8) = COPY %40.subhi:any(s16)
Selecting:
%40:any(s16) = G_PTRTOINT %75:any(p0)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=65
1272: GIM_Reject
1272: Rejected
Converting operand: %40:any
Converting operand: %75:any
Into:
%40:imag16(s16) = COPY %75:any(p0)
Selecting:
%75:any(p0) = G_GLOBAL_VALUE @_ZN4SubA2fnEv
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=57
1272: GIM_Reject
1272: Rejected
Converting operand: %90:_
Converting operand: %91:_
Into:
%90:gpr(s8) = LDImm target-flags(lo) @_ZN4SubA2fnEv
%91:gpr(s8) = LDImm target-flags(hi) @_ZN4SubA2fnEv
%75:imag16(p0) = REG_SEQUENCE %90:gpr(s8), %subreg.sublo, %91:gpr(s8), %subreg.subhi
Selecting:
G_BR %bb.4
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=184
1245: Begin try-block
1249: GIM_CheckIsMBB(MIs[0]->getOperand(0))
1250: Begin try-block
1253: GIM_CheckFeatures(ExpectedBitsetID=1)
1253: Rejected
1260: Resume at 1260 (2 try-blocks remain)
1261: Begin try-block
1266: GIR_MutateOpcode(OutMIs[0], MIs[0], 264)
1268: GIR_ConstrainSelectedInstOperands(OutMIs[0])
1269: GIR_Done
Into:
JMP %bb.4
Selecting:
G_BRCOND_IMM %59:any(s1), %bb.5, 1
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=258
1272: GIM_Reject
1272: Rejected
Converting operand: %92:_
Converting operand: %9:any
Into:
%92:cc(s1) = CMPImmTerm %9:gpr(s8), 0, implicit-def $nz
BR %bb.5, $z, 1
Selecting:
%42:any(s8), %43:any(s8) = G_UNMERGE_VALUES %39:any(s16)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=59
1272: GIM_Reject
1272: Rejected
Into:
%42:anyi8(s8) = COPY %39.sublo:any(s16)
%43:anyi8(s8) = COPY %39.subhi:any(s16)
Selecting:
%39:any(s16) = G_PTRTOINT %76:any(p0)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=65
1272: GIM_Reject
1272: Rejected
Converting operand: %39:any
Converting operand: %76:any
Into:
%39:imag16(s16) = COPY %76:any(p0)
Selecting:
%76:any(p0) = G_GLOBAL_VALUE @_ZN4SubB2fnEv
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=57
1272: GIM_Reject
1272: Rejected
Converting operand: %93:_
Converting operand: %94:_
Into:
%93:gpr(s8) = LDImm target-flags(lo) @_ZN4SubB2fnEv
%94:gpr(s8) = LDImm target-flags(hi) @_ZN4SubB2fnEv
%76:imag16(p0) = REG_SEQUENCE %93:gpr(s8), %subreg.sublo, %94:gpr(s8), %subreg.subhi
Selecting:
G_STORE %68:any(s8), %51:any(p0) :: (store 1 into %ir.0 + 1, !tbaa !2)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=80
1272: GIM_Reject
1272: Rejected
Converting operand: %68:any
Converting operand: %4:imag16
Converting operand: %53:any
Into:
STYIndir %68:ac(s8), %4:imag16(p0), %53:yc(s8) :: (store 1 into %ir.0 + 1, !tbaa !2)
Selecting:
%51:any(p0) = G_INDEX %4:imag16, %53:yc(s8)
Is dead; erasing.
Selecting:
%53:yc(s8) = G_CONSTANT i8 1
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=104
1197: GIM_SwitchType(MIs[0]->getOperand(0), [0, 2), Default=1243, JumpTable...) // Got=s8
1222: Begin try-block
1227: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=11)
1230: GIR_BuildMI(OutMIs[0], 272)
1234: GIR_Copy(OutMIs[0], MIs[0], 0)
1237: GIR_CopyConstantAsSImm(OutMIs[0], MIs[0])
1239: GIR_EraseFromParent(MIs[0])
Converting operand: %53:yc
1241: GIR_ConstrainSelectedInstOperands(OutMIs[0])
1242: GIR_Done
Into:
%53:yc(s8) = LDImm 1
Selecting:
G_STORE %67:any(s8), %4:imag16(p0) :: (store 1 into %ir.0, !tbaa !2)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=80
1272: GIM_Reject
1272: Rejected
Converting operand: %67:any
Converting operand: %4:imag16
Converting operand: %95:_
Into:
%95:yc(s8) = LDImm 0
STYIndir %67:ac(s8), %4:imag16(p0), %95:yc(s8) :: (store 1 into %ir.0, !tbaa !2)
Selecting:
%55:any(s8), %56:any(s1), %57:any, %58:any, %59:any = G_SBC %9:gpr, %78:any, %54:any
Is dead; erasing.
Selecting:
%78:any(s8) = G_CONSTANT i8 0
Is dead; erasing.
Selecting:
%54:any(s1) = G_CONSTANT i1 true
Is dead; erasing.
Selecting:
%9:gpr(s8) = G_FREEZE %0:any
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=68
1272: GIM_Reject
1272: Rejected
Converting operand: %9:gpr
Converting operand: %0:any
Into:
%9:gpr(s8) = COPY %0:any(s8)
Selecting:
%68:ac(s8) = G_PHI %64:any(s8), %bb.1, %66:any(s8), %bb.2
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=55
1272: GIM_Reject
1272: Rejected
Converting operand: %68:ac
Converting operand: %64:any
Converting operand: %66:any
Into:
%68:ac(s8) = PHI %64:any(s8), %bb.1, %66:any(s8), %bb.2
Selecting:
%67:ac(s8) = G_PHI %63:any(s8), %bb.1, %65:any(s8), %bb.2
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=55
1272: GIM_Reject
1272: Rejected
Converting operand: %67:ac
Converting operand: %63:any
Converting operand: %65:any
Into:
%67:ac(s8) = PHI %63:any(s8), %bb.1, %65:any(s8), %bb.2
Selecting:
%65:any(s8), %66:any(s8) = G_UNMERGE_VALUES %61:any(s16)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=59
1272: GIM_Reject
1272: Rejected
Into:
%65:anyi8(s8) = COPY %61.sublo:any(s16)
%66:anyi8(s8) = COPY %61.subhi:any(s16)
Selecting:
%61:any(s16) = G_PTRTOINT %77:any(p0)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=65
1272: GIM_Reject
1272: Rejected
Converting operand: %61:any
Converting operand: %77:any
Into:
%61:imag16(s16) = COPY %77:any(p0)
Selecting:
%77:any(p0) = G_GLOBAL_VALUE @_ZTV4SubA + 4
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=57
1272: GIM_Reject
1272: Rejected
Converting operand: %96:_
Converting operand: %97:_
Into:
%96:gpr(s8) = LDImm target-flags(lo) @_ZTV4SubA + 4
%97:gpr(s8) = LDImm target-flags(hi) @_ZTV4SubA + 4
%77:imag16(p0) = REG_SEQUENCE %96:gpr(s8), %subreg.sublo, %97:gpr(s8), %subreg.subhi
Selecting:
G_BR %bb.2
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=184
1245: Begin try-block
1249: GIM_CheckIsMBB(MIs[0]->getOperand(0))
1250: Begin try-block
1253: GIM_CheckFeatures(ExpectedBitsetID=1)
1253: Rejected
1260: Resume at 1260 (2 try-blocks remain)
1261: Begin try-block
1266: GIR_MutateOpcode(OutMIs[0], MIs[0], 264)
1268: GIR_ConstrainSelectedInstOperands(OutMIs[0])
1269: GIR_Done
Into:
JMP %bb.2
Selecting:
G_BRCOND_IMM %74:any(s1), %bb.3, 1
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=258
1272: GIM_Reject
1272: Rejected
Converting operand: %98:_
Converting operand: %1:any
Into:
%98:cc(s1) = CMPImmTerm %1:gpr(s8), 0, implicit-def $nz
BR %bb.3, $z, 1
Selecting:
%63:any(s8), %64:any(s8) = G_UNMERGE_VALUES %60:any(s16)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=59
1272: GIM_Reject
1272: Rejected
Into:
%63:anyi8(s8) = COPY %60.sublo:any(s16)
%64:anyi8(s8) = COPY %60.subhi:any(s16)
Selecting:
%60:any(s16) = G_PTRTOINT %17:any(p0)
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=65
1272: GIM_Reject
1272: Rejected
Converting operand: %60:any
Converting operand: %17:any
Into:
%60:imag16(s16) = COPY %17:any(p0)
Selecting:
%17:any(p0) = G_GLOBAL_VALUE @_ZTV4SubB + 4
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=57
1272: GIM_Reject
1272: Rejected
Converting operand: %99:_
Converting operand: %100:_
Into:
%99:gpr(s8) = LDImm target-flags(lo) @_ZTV4SubB + 4
%100:gpr(s8) = LDImm target-flags(hi) @_ZTV4SubB + 4
%17:imag16(p0) = REG_SEQUENCE %99:gpr(s8), %subreg.sublo, %100:gpr(s8), %subreg.subhi
Selecting:
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Into:
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Selecting:
%4:imag16(p0) = COPY $rs1
Into:
%4:imag16(p0) = COPY $rs1
Selecting:
JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $a, implicit $x, implicit-def $rs1
Into:
JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $a, implicit $x, implicit-def $rs1
Selecting:
$x = COPY %2:any(s8)
Into:
$x = COPY %2:any(s8)
Selecting:
$a = COPY %6:any(s8)
Into:
$a = COPY %6:any(s8)
Selecting:
%6:any(s8) = G_CONSTANT i8 2
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=104
1197: GIM_SwitchType(MIs[0]->getOperand(0), [0, 2), Default=1243, JumpTable...) // Got=s8
1222: Begin try-block
1227: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=11)
1230: GIR_BuildMI(OutMIs[0], 272)
1234: GIR_Copy(OutMIs[0], MIs[0], 0)
1237: GIR_CopyConstantAsSImm(OutMIs[0], MIs[0])
1239: GIR_EraseFromParent(MIs[0])
Converting operand: %6:any
1241: GIR_ConstrainSelectedInstOperands(OutMIs[0])
1242: GIR_Done
Into:
%6:gpr(s8) = LDImm 2
Selecting:
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Into:
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Selecting:
%70:any(s8), %71:any(s1), %72:any, %73:any, %74:any = G_SBC %1:gpr, %2:any, %69:any
Is dead; erasing.
Selecting:
%2:any(s8) = G_CONSTANT i8 0
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=104
1197: GIM_SwitchType(MIs[0]->getOperand(0), [0, 2), Default=1243, JumpTable...) // Got=s8
1222: Begin try-block
1227: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=11)
1230: GIR_BuildMI(OutMIs[0], 272)
1234: GIR_Copy(OutMIs[0], MIs[0], 0)
1237: GIR_CopyConstantAsSImm(OutMIs[0], MIs[0])
1239: GIR_EraseFromParent(MIs[0])
Converting operand: %2:any
1241: GIR_ConstrainSelectedInstOperands(OutMIs[0])
1242: GIR_Done
Into:
%2:gpr(s8) = LDImm 0
Selecting:
%69:any(s1) = G_CONSTANT i1 true
Is dead; erasing.
Selecting:
%1:gpr(s8) = G_FREEZE %0:any
5: GIM_SwitchOpcode(MIs[0], [42, 185), Default=1271, JumpTable...) // Got=68
1272: GIM_Reject
1272: Rejected
Converting operand: %1:gpr
Converting operand: %0:any
Into:
%1:gpr(s8) = COPY %0:any(s8)
Selecting:
%26:any(p0) = G_GLOBAL_VALUE @_ZN4SubA2fnEv
Is dead; erasing.
Selecting:
%24:any(p0) = G_GLOBAL_VALUE @_ZN4SubB2fnEv
Is dead; erasing.
Selecting:
%21:any(p0) = G_GLOBAL_VALUE @_ZTV4SubA + 4
Is dead; erasing.
Selecting:
%0:any(s8) = COPY $a
Into:
%0:anyi8(s8) = COPY $a
Rules covered by selecting function: _Z11testIndCallc:
# Machine code for function _Z11testIndCallc: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
0B bb.1.entry:
successors: %bb.3(0x30000000), %bb.2(0x50000000); %bb.3(37.50%), %bb.2(62.50%)
liveins: $a
16B %0:anyi8 = COPY $a
32B %1:gpr = COPY %0:anyi8
48B %2:gpr = LDImm 0
64B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
80B %6:gpr = LDImm 2
96B $a = COPY %6:gpr
112B $x = COPY %2:gpr
128B JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $a, implicit $x, implicit-def $rs1
144B %4:imag16 = COPY $rs1
160B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
176B %99:gpr = LDImm target-flags(lo) @_ZTV4SubB + 4
192B %100:gpr = LDImm target-flags(hi) @_ZTV4SubB + 4
208B %17:imag16 = REG_SEQUENCE %99:gpr, %subreg.sublo, %100:gpr, %subreg.subhi
224B %63:anyi8 = COPY %99:gpr
240B %64:anyi8 = COPY %100:gpr
256B %98:cc = CMPImmTerm %1:gpr, 0, implicit-def $nz
272B BR %bb.3, $z, 1
288B JMP %bb.2
304B bb.2.select.false:
; predecessors: %bb.1
successors: %bb.3(0x80000000); %bb.3(100.00%)
320B %96:gpr = LDImm target-flags(lo) @_ZTV4SubA + 4
336B %97:gpr = LDImm target-flags(hi) @_ZTV4SubA + 4
352B %77:imag16 = REG_SEQUENCE %96:gpr, %subreg.sublo, %97:gpr, %subreg.subhi
368B %65:anyi8 = COPY %96:gpr
384B %66:anyi8 = COPY %97:gpr
400B bb.3.select.end:
; predecessors: %bb.1, %bb.2
successors: %bb.5(0x30000000), %bb.4(0x50000000); %bb.5(37.50%), %bb.4(62.50%)
416B %67:ac = PHI %63:anyi8, %bb.1, %65:anyi8, %bb.2
432B %68:ac = PHI %64:anyi8, %bb.1, %66:anyi8, %bb.2
448B %9:gpr = COPY %0:anyi8
464B %95:yc = LDImm 0
480B STYIndir %67:ac, %4:imag16, %95:yc :: (store 1 into %ir.0, !tbaa !2)
496B %53:yc = LDImm 1
512B STYIndir %68:ac, %4:imag16, %53:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
528B %93:gpr = LDImm target-flags(lo) @_ZN4SubB2fnEv
544B %94:gpr = LDImm target-flags(hi) @_ZN4SubB2fnEv
560B %76:imag16 = REG_SEQUENCE %93:gpr, %subreg.sublo, %94:gpr, %subreg.subhi
576B %42:anyi8 = COPY %93:gpr
592B %43:anyi8 = COPY %94:gpr
608B %92:cc = CMPImmTerm %9:gpr, 0, implicit-def $nz
624B BR %bb.5, $z, 1
640B JMP %bb.4
656B bb.4.select.false9:
; predecessors: %bb.3
successors: %bb.5(0x80000000); %bb.5(100.00%)
672B %90:gpr = LDImm target-flags(lo) @_ZN4SubA2fnEv
688B %91:gpr = LDImm target-flags(hi) @_ZN4SubA2fnEv
704B %75:imag16 = REG_SEQUENCE %90:gpr, %subreg.sublo, %91:gpr, %subreg.subhi
720B %44:anyi8 = COPY %90:gpr
736B %45:anyi8 = COPY %91:gpr
752B bb.5.select.end8:
; predecessors: %bb.3, %bb.4
768B %46:anyi8 = PHI %42:anyi8, %bb.3, %44:anyi8, %bb.4
784B %47:anyi8 = PHI %43:anyi8, %bb.3, %45:anyi8, %bb.4
800B %41:imag16 = REG_SEQUENCE %46:anyi8, %subreg.sublo, %47:anyi8, %subreg.subhi
816B $rs8 = COPY %41:imag16
832B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
848B $rs1 = COPY %4:imag16
864B JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
880B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
896B %89:yc = LDImm 0
912B %35:ac = LDYIndir %4:imag16, %89:yc :: (load 1 from %ir.3, !tbaa !2)
928B %32:yc = LDImm 1
944B %38:ac = LDYIndir %4:imag16, %32:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
960B %34:imag16 = REG_SEQUENCE %35:ac, %subreg.sublo, %38:ac, %subreg.subhi
976B %33:yc = LDImm 2
992B %81:cc = LDImm1 0
1008B %82:ac, %83:cc, %88:vc = ADCImm %35:ac(tied-def 0), 2, %81:cc(tied-def 1)
1024B %85:ac, %86:cc, %87:vc = ADCImm %38:ac(tied-def 0), 0, %83:cc(tied-def 1)
1040B %14:imag16 = REG_SEQUENCE %82:ac, %subreg.sublo, %85:ac, %subreg.subhi
1056B %28:ac = LDYIndir %34:imag16, %33:yc :: (load 1 from %ir.vfn3)
1072B %31:ac = LDYIndir %14:imag16, %32:yc :: (load 1 from %ir.vfn3 + 1)
1088B %27:imag16 = REG_SEQUENCE %28:ac, %subreg.sublo, %31:ac, %subreg.subhi
1104B $rs8 = COPY %27:imag16
1120B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
1136B $rs1 = COPY %4:imag16
1152B JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
1168B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
1184B RTS
# End machine code for function _Z11testIndCallc.
********** Stack Coloring **********
********** Function: _Z11testIndCallc
DeadMachineInstructionElim: DELETING: %75:imag16 = REG_SEQUENCE %90:gpr, %subreg.sublo, %91:gpr, %subreg.subhi
DeadMachineInstructionElim: DELETING: %76:imag16 = REG_SEQUENCE %93:gpr, %subreg.sublo, %94:gpr, %subreg.subhi
DeadMachineInstructionElim: DELETING: %77:imag16 = REG_SEQUENCE %96:gpr, %subreg.sublo, %97:gpr, %subreg.subhi
DeadMachineInstructionElim: DELETING: %17:imag16 = REG_SEQUENCE %99:gpr, %subreg.sublo, %100:gpr, %subreg.subhi
block-frequency: _Z11testIndCallc
=================================
reverse-post-order-traversal
- 0: BB1[entry]
- 1: BB2[select.false]
- 2: BB3[select.end]
- 3: BB4[select.false9]
- 4: BB5[select.end8]
loop-detection
compute-mass-in-function
- node: BB1[entry]
=> [ local ] weight = 805306368, succ = BB3[select.end]
=> [ local ] weight = 1342177280, succ = BB2[select.false]
=> mass: ffffffffffffffff
=> assign 9fffffffffffffff (6000000000000000) to BB2[select.false]
=> assign 6000000000000000 (0000000000000000) to BB3[select.end]
- node: BB2[select.false]
=> [ local ] weight = 2147483648, succ = BB3[select.end]
=> mass: 9fffffffffffffff
=> assign 9fffffffffffffff (0000000000000000) to BB3[select.end]
- node: BB3[select.end]
=> [ local ] weight = 805306368, succ = BB5[select.end8]
=> [ local ] weight = 1342177280, succ = BB4[select.false9]
=> mass: ffffffffffffffff
=> assign 9fffffffffffffff (6000000000000000) to BB4[select.false9]
=> assign 6000000000000000 (0000000000000000) to BB5[select.end8]
- node: BB4[select.false9]
=> [ local ] weight = 2147483648, succ = BB5[select.end8]
=> mass: 9fffffffffffffff
=> assign 9fffffffffffffff (0000000000000000) to BB5[select.end8]
- node: BB5[select.end8]
=> mass: ffffffffffffffff
float-to-int: min = 0.625, max = 1.0, factor = 12.8
- BB1[entry]: float = 1.0, scaled = 12.8, int = 12
- BB2[select.false]: float = 0.625, scaled = 8.0, int = 8
- BB3[select.end]: float = 1.0, scaled = 12.8, int = 12
- BB4[select.false9]: float = 0.625, scaled = 8.0, int = 8
- BB5[select.end8]: float = 1.0, scaled = 12.8, int = 12
block-frequency-info: _Z11testIndCallc
- BB1[entry]: float = 1.0, int = 12
- BB2[select.false]: float = 0.625, int = 8
- BB3[select.end]: float = 1.0, int = 12
- BB4[select.false9]: float = 0.625, int = 8
- BB5[select.end8]: float = 1.0, int = 12
******** Pre-regalloc Machine LICM: _Z11testIndCallc ********
block-frequency: _Z11testIndCallc
=================================
reverse-post-order-traversal
- 0: BB1[entry]
- 1: BB2[select.false]
- 2: BB3[select.end]
- 3: BB4[select.false9]
- 4: BB5[select.end8]
loop-detection
compute-mass-in-function
- node: BB1[entry]
=> [ local ] weight = 805306368, succ = BB3[select.end]
=> [ local ] weight = 1342177280, succ = BB2[select.false]
=> mass: ffffffffffffffff
=> assign 9fffffffffffffff (6000000000000000) to BB2[select.false]
=> assign 6000000000000000 (0000000000000000) to BB3[select.end]
- node: BB2[select.false]
=> [ local ] weight = 2147483648, succ = BB3[select.end]
=> mass: 9fffffffffffffff
=> assign 9fffffffffffffff (0000000000000000) to BB3[select.end]
- node: BB3[select.end]
=> [ local ] weight = 805306368, succ = BB5[select.end8]
=> [ local ] weight = 1342177280, succ = BB4[select.false9]
=> mass: ffffffffffffffff
=> assign 9fffffffffffffff (6000000000000000) to BB4[select.false9]
=> assign 6000000000000000 (0000000000000000) to BB5[select.end8]
- node: BB4[select.false9]
=> [ local ] weight = 2147483648, succ = BB5[select.end8]
=> mass: 9fffffffffffffff
=> assign 9fffffffffffffff (0000000000000000) to BB5[select.end8]
- node: BB5[select.end8]
=> mass: ffffffffffffffff
float-to-int: min = 0.625, max = 1.0, factor = 12.8
- BB1[entry]: float = 1.0, scaled = 12.8, int = 12
- BB2[select.false]: float = 0.625, scaled = 8.0, int = 8
- BB3[select.end]: float = 1.0, scaled = 12.8, int = 12
- BB4[select.false9]: float = 0.625, scaled = 8.0, int = 8
- BB5[select.end8]: float = 1.0, scaled = 12.8, int = 12
block-frequency-info: _Z11testIndCallc
- BB1[entry]: float = 1.0, int = 12
- BB2[select.false]: float = 0.625, int = 8
- BB3[select.end]: float = 1.0, int = 12
- BB4[select.false9]: float = 0.625, int = 8
- BB5[select.end8]: float = 1.0, int = 12
Entering: entry
Entering: select.false
Exiting: select.false
Entering: select.end
Examining: %95:yc = LDImm 0
*** Found a common subexpression: %2:gpr = LDImm 0
Entering: select.false9
Exiting: select.false9
Entering: select.end8
Examining: %89:yc = LDImm 0
*** Found a common subexpression: %2:yc = LDImm 0
*** Not profitable, avoid CSE!
Examining: %32:yc = LDImm 1
*** Found a common subexpression: %53:yc = LDImm 1
Examining: %33:yc = LDImm 2
*** Found a common subexpression: %6:gpr = LDImm 2
*** Not profitable, avoid CSE!
Exiting: select.end8
Exiting: select.end
Exiting: entry
Looking for trivial roots
Found a new trivial root: %bb.5
Last visited node: %bb.1
Looking for non-trivial roots
Total: 5, Num: 6
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.5
3: %bb.4
4: %bb.3
5: %bb.2
6: %bb.1
Found roots: %bb.5
******** Machine Sinking ********
Sink instr %64:anyi8 = COPY %100:gpr
into block bb.3.select.end:
; predecessors: %bb.1, %bb.2
successors: %bb.5(0x30000000), %bb.4(0x50000000); %bb.5(37.50%), %bb.4(62.50%)
%67:ac = PHI %63:anyi8, %bb.1, %65:anyi8, %bb.2
%68:ac = PHI %64:anyi8, %bb.1, %66:anyi8, %bb.2
%9:gpr = COPY %0:anyi8
STYIndir %67:ac, %4:imag16, %2:yc :: (store 1 into %ir.0, !tbaa !2)
%53:yc = LDImm 1
STYIndir %68:ac, %4:imag16, %53:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
%93:gpr = LDImm target-flags(lo) @_ZN4SubB2fnEv
%94:gpr = LDImm target-flags(hi) @_ZN4SubB2fnEv
%42:anyi8 = COPY %93:gpr
%43:anyi8 = COPY %94:gpr
%92:cc = CMPImmTerm %9:gpr, 0, implicit-def $nz
BR %bb.5, $z, 1
JMP %bb.4
Sinking along critical edge.
Sink instr %63:anyi8 = COPY %99:gpr
into block bb.3.select.end:
; predecessors: %bb.1, %bb.2
successors: %bb.5(0x30000000), %bb.4(0x50000000); %bb.5(37.50%), %bb.4(62.50%)
%67:ac = PHI %63:anyi8, %bb.1, %65:anyi8, %bb.2
%68:ac = PHI %64:anyi8, %bb.1, %66:anyi8, %bb.2
%9:gpr = COPY %0:anyi8
STYIndir %67:ac, %4:imag16, %2:yc :: (store 1 into %ir.0, !tbaa !2)
%53:yc = LDImm 1
STYIndir %68:ac, %4:imag16, %53:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
%93:gpr = LDImm target-flags(lo) @_ZN4SubB2fnEv
%94:gpr = LDImm target-flags(hi) @_ZN4SubB2fnEv
%42:anyi8 = COPY %93:gpr
%43:anyi8 = COPY %94:gpr
%92:cc = CMPImmTerm %9:gpr, 0, implicit-def $nz
BR %bb.5, $z, 1
JMP %bb.4
Sinking along critical edge.
Sink instr %43:anyi8 = COPY %94:gpr
into block bb.5.select.end8:
; predecessors: %bb.3, %bb.4
%46:anyi8 = PHI %42:anyi8, %bb.3, %44:anyi8, %bb.4
%47:anyi8 = PHI %43:anyi8, %bb.3, %45:anyi8, %bb.4
%41:imag16 = REG_SEQUENCE %46:anyi8, %subreg.sublo, %47:anyi8, %subreg.subhi
$rs8 = COPY %41:imag16
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
$rs1 = COPY %4:imag16
JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
%89:yc = LDImm 0
%35:ac = LDYIndir %4:imag16, %89:yc :: (load 1 from %ir.3, !tbaa !2)
%38:ac = LDYIndir %4:imag16, %53:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
%34:imag16 = REG_SEQUENCE %35:ac, %subreg.sublo, %38:ac, %subreg.subhi
%33:yc = LDImm 2
%81:cc = LDImm1 0
%82:ac, %83:cc, %88:vc = ADCImm %35:ac(tied-def 0), 2, %81:cc(tied-def 1)
%85:ac, %86:cc, %87:vc = ADCImm %38:ac(tied-def 0), 0, %83:cc(tied-def 1)
%14:imag16 = REG_SEQUENCE %82:ac, %subreg.sublo, %85:ac, %subreg.subhi
%28:ac = LDYIndir %34:imag16, %33:yc :: (load 1 from %ir.vfn3)
%31:ac = LDYIndir %14:imag16, %53:yc :: (load 1 from %ir.vfn3 + 1)
%27:imag16 = REG_SEQUENCE %28:ac, %subreg.sublo, %31:ac, %subreg.subhi
$rs8 = COPY %27:imag16
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
$rs1 = COPY %4:imag16
JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
RTS
Sinking along critical edge.
Sink instr %42:anyi8 = COPY %93:gpr
into block bb.5.select.end8:
; predecessors: %bb.3, %bb.4
%46:anyi8 = PHI %42:anyi8, %bb.3, %44:anyi8, %bb.4
%47:anyi8 = PHI %43:anyi8, %bb.3, %45:anyi8, %bb.4
%41:imag16 = REG_SEQUENCE %46:anyi8, %subreg.sublo, %47:anyi8, %subreg.subhi
$rs8 = COPY %41:imag16
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
$rs1 = COPY %4:imag16
JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
%89:yc = LDImm 0
%35:ac = LDYIndir %4:imag16, %89:yc :: (load 1 from %ir.3, !tbaa !2)
%38:ac = LDYIndir %4:imag16, %53:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
%34:imag16 = REG_SEQUENCE %35:ac, %subreg.sublo, %38:ac, %subreg.subhi
%33:yc = LDImm 2
%81:cc = LDImm1 0
%82:ac, %83:cc, %88:vc = ADCImm %35:ac(tied-def 0), 2, %81:cc(tied-def 1)
%85:ac, %86:cc, %87:vc = ADCImm %38:ac(tied-def 0), 0, %83:cc(tied-def 1)
%14:imag16 = REG_SEQUENCE %82:ac, %subreg.sublo, %85:ac, %subreg.subhi
%28:ac = LDYIndir %34:imag16, %33:yc :: (load 1 from %ir.vfn3)
%31:ac = LDYIndir %14:imag16, %53:yc :: (load 1 from %ir.vfn3 + 1)
%27:imag16 = REG_SEQUENCE %28:ac, %subreg.sublo, %31:ac, %subreg.subhi
$rs8 = COPY %27:imag16
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
$rs1 = COPY %4:imag16
JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
RTS
Sinking along critical edge.
Splitting critical edge: %bb.1 -- %bb.6 -- %bb.3
Updating terminators on %bb.1
*** Splitting critical edge: %bb.1 -- %bb.6 -- %bb.3
Splitting critical edge: %bb.3 -- %bb.7 -- %bb.5
Updating terminators on %bb.3
*** Splitting critical edge: %bb.3 -- %bb.7 -- %bb.5
Sink instr %64:anyi8 = COPY %100:gpr
into block bb.6:
; predecessors: %bb.1
successors: %bb.3(0x80000000); %bb.3(100.00%)
JMP %bb.3
Sink instr %63:anyi8 = COPY %99:gpr
into block bb.6:
; predecessors: %bb.1
successors: %bb.3(0x80000000); %bb.3(100.00%)
%64:anyi8 = COPY %100:gpr
JMP %bb.3
Sink instr %100:gpr = LDImm target-flags(hi) @_ZTV4SubB + 4
into block bb.6:
; predecessors: %bb.1
successors: %bb.3(0x80000000); %bb.3(100.00%)
%63:anyi8 = COPY %99:gpr
%64:anyi8 = COPY %100:gpr
JMP %bb.3
Sink instr %99:gpr = LDImm target-flags(lo) @_ZTV4SubB + 4
into block bb.6:
; predecessors: %bb.1
successors: %bb.3(0x80000000); %bb.3(100.00%)
%100:gpr = LDImm target-flags(hi) @_ZTV4SubB + 4
%63:anyi8 = COPY %99:gpr
%64:anyi8 = COPY %100:gpr
JMP %bb.3
Sink instr %43:anyi8 = COPY %94:gpr
into block bb.7:
; predecessors: %bb.3
successors: %bb.5(0x80000000); %bb.5(100.00%)
JMP %bb.5
Sink instr %42:anyi8 = COPY %93:gpr
into block bb.7:
; predecessors: %bb.3
successors: %bb.5(0x80000000); %bb.5(100.00%)
%43:anyi8 = COPY %94:gpr
JMP %bb.5
Sink instr %94:gpr = LDImm target-flags(hi) @_ZN4SubB2fnEv
into block bb.7:
; predecessors: %bb.3
successors: %bb.5(0x80000000); %bb.5(100.00%)
%42:anyi8 = COPY %93:gpr
%43:anyi8 = COPY %94:gpr
JMP %bb.5
Sink instr %93:gpr = LDImm target-flags(lo) @_ZN4SubB2fnEv
into block bb.7:
; predecessors: %bb.3
successors: %bb.5(0x80000000); %bb.5(100.00%)
%94:gpr = LDImm target-flags(hi) @_ZN4SubB2fnEv
%42:anyi8 = COPY %93:gpr
%43:anyi8 = COPY %94:gpr
JMP %bb.5
********** PEEPHOLE OPTIMIZER **********
********** Function: _Z11testIndCallc
Encountered load fold barrier on JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $a, implicit $x, implicit-def $rs1
Encountered load fold barrier on STYIndir %67:ac, %4:imag16, %2:yc :: (store 1 into %ir.0, !tbaa !2)
Encountered load fold barrier on STYIndir %68:ac, %4:imag16, %53:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
Encountered load fold barrier on JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
Encountered load fold barrier on JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
Copy across incompatible classes: %27:imag16 = REG_SEQUENCE %28:ac, %subreg.sublo, %31:ac, %subreg.subhi
Copy across incompatible classes: %27:imag16 = REG_SEQUENCE %28:ac, %subreg.sublo, %31:ac, %subreg.subhi
Copy across incompatible classes: %34:imag16 = REG_SEQUENCE %35:ac, %subreg.sublo, %38:ac, %subreg.subhi
Copy across incompatible classes: %34:imag16 = REG_SEQUENCE %35:ac, %subreg.sublo, %38:ac, %subreg.subhi
Copy across incompatible classes: %14:imag16 = REG_SEQUENCE %82:ac, %subreg.sublo, %85:ac, %subreg.subhi
Copy across incompatible classes: %14:imag16 = REG_SEQUENCE %82:ac, %subreg.sublo, %85:ac, %subreg.subhi
Defined/Used lanes:
%0 Used: 0000000000000002 Def: 0000000000000002
%1 Used: 0000000000000002 Def: 0000000000000002
%2 Used: 0000000000000002 Def: 0000000000000002
%3 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%4 Used: 0000000000000022 Def: 0000000000000022
%5 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%6 Used: 0000000000000002 Def: 0000000000000002
%7 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%8 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%9 Used: 0000000000000002 Def: 0000000000000002
%10 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%11 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%12 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%13 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%14 Used: 0000000000000022 Def: 0000000000000022
%15 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%16 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%17 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%18 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%19 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%20 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%21 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%22 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%23 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%24 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%25 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%26 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%27 Used: 0000000000000022 Def: 0000000000000022
%28 Used: 0000000000000002 Def: 0000000000000002
%29 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%30 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%31 Used: 0000000000000002 Def: 0000000000000002
%32 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%33 Used: 0000000000000002 Def: 0000000000000002
%34 Used: 0000000000000022 Def: 0000000000000022
%35 Used: 0000000000000002 Def: 0000000000000002
%36 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%37 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%38 Used: 0000000000000002 Def: 0000000000000002
%39 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%40 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%41 Used: 0000000000000022 Def: 0000000000000022
%42 Used: 0000000000000002 Def: 0000000000000002
%43 Used: 0000000000000002 Def: 0000000000000002
%44 Used: 0000000000000002 Def: 0000000000000002
%45 Used: 0000000000000002 Def: 0000000000000002
%46 Used: 0000000000000002 Def: 0000000000000002
%47 Used: 0000000000000002 Def: 0000000000000002
%48 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%49 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%50 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%51 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%52 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%53 Used: 0000000000000002 Def: 0000000000000002
%54 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%55 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%56 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%57 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%58 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%59 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%60 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%61 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%62 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%63 Used: 0000000000000002 Def: 0000000000000002
%64 Used: 0000000000000002 Def: 0000000000000002
%65 Used: 0000000000000002 Def: 0000000000000002
%66 Used: 0000000000000002 Def: 0000000000000002
%67 Used: 0000000000000002 Def: 0000000000000002
%68 Used: 0000000000000002 Def: 0000000000000002
%69 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%70 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%71 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%72 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%73 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%74 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%75 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%76 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%77 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%78 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%79 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%80 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%81 Used: 0000000000000001 Def: 0000000000000001
%82 Used: 0000000000000002 Def: 0000000000000002
%83 Used: 0000000000000001 Def: 0000000000000001
%84 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%85 Used: 0000000000000002 Def: 0000000000000002
%86 Used: 0000000000000000 Def: 0000000000000001
%87 Used: 0000000000000000 Def: 0000000000000001
%88 Used: 0000000000000000 Def: 0000000000000001
%89 Used: 0000000000000002 Def: 0000000000000002
%90 Used: 0000000000000002 Def: 0000000000000002
%91 Used: 0000000000000002 Def: 0000000000000002
%92 Used: 0000000000000000 Def: 0000000000000001
%93 Used: 0000000000000002 Def: 0000000000000002
%94 Used: 0000000000000002 Def: 0000000000000002
%95 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%96 Used: 0000000000000002 Def: 0000000000000002
%97 Used: 0000000000000002 Def: 0000000000000002
%98 Used: 0000000000000000 Def: 0000000000000001
%99 Used: 0000000000000002 Def: 0000000000000002
%100 Used: 0000000000000002 Def: 0000000000000002
Marking operand '%98:cc' as dead in %98:cc = CMPImmTerm %1:gpr, 0, implicit-def $nz
Marking operand '%92:cc' as dead in %92:cc = CMPImmTerm %9:gpr, 0, implicit-def $nz
Marking operand '%88:vc' as dead in %82:ac, %83:cc, %88:vc = ADCImm %35:ac(tied-def 0), 2, %81:cc(tied-def 1)
Marking operand '%86:cc' as dead in %85:ac, %86:cc, %87:vc = ADCImm %38:ac(tied-def 0), 0, %83:cc(tied-def 1)
Marking operand '%87:vc' as dead in %85:ac, dead %86:cc, %87:vc = ADCImm %38:ac(tied-def 0), 0, %83:cc(tied-def 1)
********** PROCESS IMPLICIT DEFS **********
********** Function: _Z11testIndCallc
********** REWRITING TWO-ADDR INSTRS **********
********** Function: _Z11testIndCallc
Inserted: undef %41.sublo:imag16 = COPY killed %46:anyi8
Inserted: %41.subhi:imag16 = COPY killed %47:anyi8
Eliminated: %41:imag16 = REG_SEQUENCE killed %46:anyi8, %subreg.sublo, killed %47:anyi8, %subreg.subhi
Inserted: undef %34.sublo:imag16 = COPY %35:ac
Inserted: %34.subhi:imag16 = COPY %38:ac
Eliminated: %34:imag16 = REG_SEQUENCE %35:ac, %subreg.sublo, %38:ac, %subreg.subhi
%82:ac, %83:cc, dead %88:vc = ADCImm killed %35:ac(tied-def 0), 2, killed %81:cc(tied-def 1)
prepend: %83:cc = COPY %81:cc
rewrite to: %82:ac, %83:cc, dead %88:vc = ADCImm killed %35:ac(tied-def 0), 2, %83:cc(tied-def 1)
prepend: %82:ac = COPY %35:ac
rewrite to: %82:ac, %83:cc, dead %88:vc = ADCImm %82:ac(tied-def 0), 2, %83:cc(tied-def 1)
%85:ac, dead %86:cc, dead %87:vc = ADCImm killed %38:ac(tied-def 0), 0, killed %83:cc(tied-def 1)
prepend: %85:ac = COPY %38:ac
rewrite to: %85:ac, dead %86:cc, dead %87:vc = ADCImm %85:ac(tied-def 0), 0, killed %83:cc(tied-def 1)
prepend: %86:cc = COPY %83:cc
rewrite to: %85:ac, dead %86:cc, dead %87:vc = ADCImm %85:ac(tied-def 0), 0, %86:cc(tied-def 1)
Inserted: undef %14.sublo:imag16 = COPY killed %82:ac
Inserted: %14.subhi:imag16 = COPY killed %85:ac
Eliminated: %14:imag16 = REG_SEQUENCE killed %82:ac, %subreg.sublo, killed %85:ac, %subreg.subhi
Inserted: undef %27.sublo:imag16 = COPY killed %28:ac
Inserted: %27.subhi:imag16 = COPY killed %31:ac
Eliminated: %27:imag16 = REG_SEQUENCE killed %28:ac, %subreg.sublo, killed %31:ac, %subreg.subhi
# Machine code for function _Z11testIndCallc: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
successors: %bb.1(0x30000000), %bb.2(0x50000000); %bb.1(37.50%), %bb.2(62.50%)
liveins: $a
16B %0:anyi8 = COPY killed $a
32B %1:gpr = COPY %0:anyi8
48B %2:yc = LDImm 0
64B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
80B %6:gpr = LDImm 2
96B $a = COPY killed %6:gpr
112B $x = COPY %2:yc
128B JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit killed $a, implicit killed $x, implicit-def $rs1
144B %4:imag16 = COPY killed $rs1
160B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
176B dead %98:cc = CMPImmTerm killed %1:gpr, 0, implicit-def dead $nz, implicit-def $z
192B BR %bb.2, killed $z, 0
208B bb.1:
; predecessors: %bb.0
successors: %bb.3(0x80000000); %bb.3(100.00%)
224B %99:gpr = LDImm target-flags(lo) @_ZTV4SubB + 4
240B %100:gpr = LDImm target-flags(hi) @_ZTV4SubB + 4
256B %63:anyi8 = COPY killed %99:gpr
272B %64:anyi8 = COPY killed %100:gpr
288B %101:ac = COPY killed %63:anyi8
304B %102:ac = COPY killed %64:anyi8
320B JMP %bb.3
336B bb.2.select.false:
; predecessors: %bb.0
successors: %bb.3(0x80000000); %bb.3(100.00%)
352B %96:gpr = LDImm target-flags(lo) @_ZTV4SubA + 4
368B %97:gpr = LDImm target-flags(hi) @_ZTV4SubA + 4
384B %65:anyi8 = COPY killed %96:gpr
400B %66:anyi8 = COPY killed %97:gpr
416B %101:ac = COPY killed %65:anyi8
432B %102:ac = COPY killed %66:anyi8
448B bb.3.select.end:
; predecessors: %bb.2, %bb.1
successors: %bb.4(0x30000000), %bb.5(0x50000000); %bb.4(37.50%), %bb.5(62.50%)
464B %68:ac = COPY killed %102:ac
480B %67:ac = COPY killed %101:ac
496B %9:gpr = COPY killed %0:anyi8
512B STYIndir killed %67:ac, %4:imag16, killed %2:yc :: (store 1 into %ir.0, !tbaa !2)
528B %53:yc = LDImm 1
544B STYIndir killed %68:ac, %4:imag16, %53:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
560B dead %92:cc = CMPImmTerm killed %9:gpr, 0, implicit-def dead $nz, implicit-def $z
576B BR %bb.5, killed $z, 0
592B bb.4:
; predecessors: %bb.3
successors: %bb.6(0x80000000); %bb.6(100.00%)
608B %93:gpr = LDImm target-flags(lo) @_ZN4SubB2fnEv
624B %94:gpr = LDImm target-flags(hi) @_ZN4SubB2fnEv
640B %42:anyi8 = COPY killed %93:gpr
656B %43:anyi8 = COPY killed %94:gpr
672B %103:anyi8 = COPY killed %42:anyi8
688B %104:anyi8 = COPY killed %43:anyi8
704B JMP %bb.6
720B bb.5.select.false9:
; predecessors: %bb.3
successors: %bb.6(0x80000000); %bb.6(100.00%)
736B %90:gpr = LDImm target-flags(lo) @_ZN4SubA2fnEv
752B %91:gpr = LDImm target-flags(hi) @_ZN4SubA2fnEv
768B %44:anyi8 = COPY killed %90:gpr
784B %45:anyi8 = COPY killed %91:gpr
800B %103:anyi8 = COPY killed %44:anyi8
816B %104:anyi8 = COPY killed %45:anyi8
832B bb.6.select.end8:
; predecessors: %bb.5, %bb.4
848B %47:anyi8 = COPY killed %104:anyi8
864B %46:anyi8 = COPY killed %103:anyi8
880B undef %41.sublo:imag16 = COPY killed %46:anyi8
896B %41.subhi:imag16 = COPY killed %47:anyi8
912B $rs8 = COPY killed %41:imag16
928B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
944B $rs1 = COPY %4:imag16
960B JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit killed $rs8, implicit killed $rs1
976B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
992B %89:yc = LDImm 0
1008B %35:ac = LDYIndir %4:imag16, killed %89:yc :: (load 1 from %ir.3, !tbaa !2)
1024B %38:ac = LDYIndir %4:imag16, %53:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
1040B undef %34.sublo:imag16 = COPY %35:ac
1056B %34.subhi:imag16 = COPY %38:ac
1072B %33:yc = LDImm 2
1088B %81:cc = LDImm1 0
1104B %83:cc = COPY killed %81:cc
1120B %82:ac = COPY killed %35:ac
1136B %82:ac, %83:cc, dead %88:vc = ADCImm %82:ac(tied-def 0), 2, %83:cc(tied-def 1)
1152B %85:ac = COPY killed %38:ac
1168B %86:cc = COPY killed %83:cc
1184B %85:ac, dead %86:cc, dead %87:vc = ADCImm %85:ac(tied-def 0), 0, %86:cc(tied-def 1)
1200B undef %14.sublo:imag16 = COPY killed %82:ac
1216B %14.subhi:imag16 = COPY killed %85:ac
1232B %28:ac = LDYIndir killed %34:imag16, killed %33:yc :: (load 1 from %ir.vfn3)
1248B %31:ac = LDYIndir killed %14:imag16, killed %53:yc :: (load 1 from %ir.vfn3 + 1)
1264B undef %27.sublo:imag16 = COPY killed %28:ac
1280B %27.subhi:imag16 = COPY killed %31:ac
1296B $rs8 = COPY killed %27:imag16
1312B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
1328B $rs1 = COPY killed %4:imag16
1344B JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit killed $rs8, implicit killed $rs1
1360B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
1376B RTS
# End machine code for function _Z11testIndCallc.
Computing live-in reg-units in ABI blocks.
0B %bb.0 ALSB#0
Created 1 new intervals.
********** INTERVALS **********
ALSB [0B,16r:0)[96r,128r:1) 0@0B-phi 1@96r
%0 [16r,496r:0) 0@16r weight:0.000000e+00
%1 [32r,176r:0) 0@32r weight:0.000000e+00
%2 [48r,512r:0) 0@48r weight:0.000000e+00
%4 [144r,1328r:0) 0@144r weight:0.000000e+00
%6 [80r,96r:0) 0@80r weight:0.000000e+00
%9 [496r,560r:0) 0@496r weight:0.000000e+00
%14 [1200r,1216r:0)[1216r,1248r:1) 0@1200r 1@1216r L0000000000000002 [1200r,1248r:0) 0@1200r L0000000000000020 [1216r,1248r:0) 0@1216r weight:0.000000e+00
%27 [1264r,1280r:0)[1280r,1296r:1) 0@1264r 1@1280r L0000000000000002 [1264r,1296r:0) 0@1264r L0000000000000020 [1280r,1296r:0) 0@1280r weight:0.000000e+00
%28 [1232r,1264r:0) 0@1232r weight:0.000000e+00
%31 [1248r,1280r:0) 0@1248r weight:0.000000e+00
%33 [1072r,1232r:0) 0@1072r weight:0.000000e+00
%34 [1040r,1056r:0)[1056r,1232r:1) 0@1040r 1@1056r L0000000000000002 [1040r,1232r:0) 0@1040r L0000000000000020 [1056r,1232r:0) 0@1056r weight:0.000000e+00
%35 [1008r,1120r:0) 0@1008r weight:0.000000e+00
%38 [1024r,1152r:0) 0@1024r weight:0.000000e+00
%41 [880r,896r:0)[896r,912r:1) 0@880r 1@896r L0000000000000002 [880r,912r:0) 0@880r L0000000000000020 [896r,912r:0) 0@896r weight:0.000000e+00
%42 [640r,672r:0) 0@640r weight:0.000000e+00
%43 [656r,688r:0) 0@656r weight:0.000000e+00
%44 [768r,800r:0) 0@768r weight:0.000000e+00
%45 [784r,816r:0) 0@784r weight:0.000000e+00
%46 [864r,880r:0) 0@864r weight:0.000000e+00
%47 [848r,896r:0) 0@848r weight:0.000000e+00
%53 [528r,1248r:0) 0@528r weight:0.000000e+00
%63 [256r,288r:0) 0@256r weight:0.000000e+00
%64 [272r,304r:0) 0@272r weight:0.000000e+00
%65 [384r,416r:0) 0@384r weight:0.000000e+00
%66 [400r,432r:0) 0@400r weight:0.000000e+00
%67 [480r,512r:0) 0@480r weight:0.000000e+00
%68 [464r,544r:0) 0@464r weight:0.000000e+00
%81 [1088r,1104r:0) 0@1088r weight:0.000000e+00
%82 [1120r,1136r:0)[1136r,1200r:1) 0@1120r 1@1136r weight:0.000000e+00
%83 [1104r,1136r:0)[1136r,1168r:1) 0@1104r 1@1136r weight:0.000000e+00
%85 [1152r,1184r:0)[1184r,1216r:1) 0@1152r 1@1184r weight:0.000000e+00
%86 [1168r,1184r:0)[1184r,1184d:1) 0@1168r 1@1184r weight:0.000000e+00
%87 [1184r,1184d:0) 0@1184r weight:0.000000e+00
%88 [1136r,1136d:0) 0@1136r weight:0.000000e+00
%89 [992r,1008r:0) 0@992r weight:0.000000e+00
%90 [736r,768r:0) 0@736r weight:0.000000e+00
%91 [752r,784r:0) 0@752r weight:0.000000e+00
%92 [560r,560d:0) 0@560r weight:0.000000e+00
%93 [608r,640r:0) 0@608r weight:0.000000e+00
%94 [624r,656r:0) 0@624r weight:0.000000e+00
%96 [352r,384r:0) 0@352r weight:0.000000e+00
%97 [368r,400r:0) 0@368r weight:0.000000e+00
%98 [176r,176d:0) 0@176r weight:0.000000e+00
%99 [224r,256r:0) 0@224r weight:0.000000e+00
%100 [240r,272r:0) 0@240r weight:0.000000e+00
%101 [288r,336B:0)[416r,448B:1)[448B,480r:2) 0@288r 1@416r 2@448B-phi weight:0.000000e+00
%102 [304r,336B:0)[432r,448B:1)[448B,464r:2) 0@304r 1@432r 2@448B-phi weight:0.000000e+00
%103 [672r,720B:0)[800r,832B:1)[832B,864r:2) 0@672r 1@800r 2@832B-phi weight:0.000000e+00
%104 [688r,720B:0)[816r,832B:1)[832B,848r:2) 0@688r 1@816r 2@832B-phi weight:0.000000e+00
RegMasks: 128r 960r 1344r
********** MACHINEINSTRS **********
# Machine code for function _Z11testIndCallc: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
successors: %bb.1(0x30000000), %bb.2(0x50000000); %bb.1(37.50%), %bb.2(62.50%)
liveins: $a
16B %0:anyi8 = COPY $a
32B %1:gpr = COPY %0:anyi8
48B %2:yc = LDImm 0
64B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
80B %6:gpr = LDImm 2
96B $a = COPY %6:gpr
112B $x = COPY %2:yc
128B JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $a, implicit killed $x, implicit-def $rs1
144B %4:imag16 = COPY killed $rs1
160B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
176B dead %98:cc = CMPImmTerm %1:gpr, 0, implicit-def dead $nz, implicit-def $z
192B BR %bb.2, killed $z, 0
208B bb.1:
; predecessors: %bb.0
successors: %bb.3(0x80000000); %bb.3(100.00%)
224B %99:gpr = LDImm target-flags(lo) @_ZTV4SubB + 4
240B %100:gpr = LDImm target-flags(hi) @_ZTV4SubB + 4
256B %63:anyi8 = COPY %99:gpr
272B %64:anyi8 = COPY %100:gpr
288B %101:ac = COPY %63:anyi8
304B %102:ac = COPY %64:anyi8
320B JMP %bb.3
336B bb.2.select.false:
; predecessors: %bb.0
successors: %bb.3(0x80000000); %bb.3(100.00%)
352B %96:gpr = LDImm target-flags(lo) @_ZTV4SubA + 4
368B %97:gpr = LDImm target-flags(hi) @_ZTV4SubA + 4
384B %65:anyi8 = COPY %96:gpr
400B %66:anyi8 = COPY %97:gpr
416B %101:ac = COPY %65:anyi8
432B %102:ac = COPY %66:anyi8
448B bb.3.select.end:
; predecessors: %bb.2, %bb.1
successors: %bb.4(0x30000000), %bb.5(0x50000000); %bb.4(37.50%), %bb.5(62.50%)
464B %68:ac = COPY %102:ac
480B %67:ac = COPY %101:ac
496B %9:gpr = COPY %0:anyi8
512B STYIndir %67:ac, %4:imag16, %2:yc :: (store 1 into %ir.0, !tbaa !2)
528B %53:yc = LDImm 1
544B STYIndir %68:ac, %4:imag16, %53:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
560B dead %92:cc = CMPImmTerm %9:gpr, 0, implicit-def dead $nz, implicit-def $z
576B BR %bb.5, killed $z, 0
592B bb.4:
; predecessors: %bb.3
successors: %bb.6(0x80000000); %bb.6(100.00%)
608B %93:gpr = LDImm target-flags(lo) @_ZN4SubB2fnEv
624B %94:gpr = LDImm target-flags(hi) @_ZN4SubB2fnEv
640B %42:anyi8 = COPY %93:gpr
656B %43:anyi8 = COPY %94:gpr
672B %103:anyi8 = COPY %42:anyi8
688B %104:anyi8 = COPY %43:anyi8
704B JMP %bb.6
720B bb.5.select.false9:
; predecessors: %bb.3
successors: %bb.6(0x80000000); %bb.6(100.00%)
736B %90:gpr = LDImm target-flags(lo) @_ZN4SubA2fnEv
752B %91:gpr = LDImm target-flags(hi) @_ZN4SubA2fnEv
768B %44:anyi8 = COPY %90:gpr
784B %45:anyi8 = COPY %91:gpr
800B %103:anyi8 = COPY %44:anyi8
816B %104:anyi8 = COPY %45:anyi8
832B bb.6.select.end8:
; predecessors: %bb.5, %bb.4
848B %47:anyi8 = COPY %104:anyi8
864B %46:anyi8 = COPY %103:anyi8
880B undef %41.sublo:imag16 = COPY %46:anyi8
896B %41.subhi:imag16 = COPY %47:anyi8
912B $rs8 = COPY %41:imag16
928B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
944B $rs1 = COPY %4:imag16
960B JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit killed $rs8, implicit killed $rs1
976B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
992B %89:yc = LDImm 0
1008B %35:ac = LDYIndir %4:imag16, %89:yc :: (load 1 from %ir.3, !tbaa !2)
1024B %38:ac = LDYIndir %4:imag16, %53:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
1040B undef %34.sublo:imag16 = COPY %35:ac
1056B %34.subhi:imag16 = COPY %38:ac
1072B %33:yc = LDImm 2
1088B %81:cc = LDImm1 0
1104B %83:cc = COPY %81:cc
1120B %82:ac = COPY %35:ac
1136B %82:ac, %83:cc, dead %88:vc = ADCImm %82:ac(tied-def 0), 2, %83:cc(tied-def 1)
1152B %85:ac = COPY %38:ac
1168B %86:cc = COPY %83:cc
1184B %85:ac, dead %86:cc, dead %87:vc = ADCImm %85:ac(tied-def 0), 0, %86:cc(tied-def 1)
1200B undef %14.sublo:imag16 = COPY %82:ac
1216B %14.subhi:imag16 = COPY %85:ac
1232B %28:ac = LDYIndir %34:imag16, %33:yc :: (load 1 from %ir.vfn3)
1248B %31:ac = LDYIndir %14:imag16, %53:yc :: (load 1 from %ir.vfn3 + 1)
1264B undef %27.sublo:imag16 = COPY %28:ac
1280B %27.subhi:imag16 = COPY %31:ac
1296B $rs8 = COPY %27:imag16
1312B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
1328B $rs1 = COPY %4:imag16
1344B JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit killed $rs8, implicit killed $rs1
1360B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
1376B RTS
# End machine code for function _Z11testIndCallc.
********** SIMPLE REGISTER COALESCING **********
********** Function: _Z11testIndCallc
********** JOINING INTERVALS ***********
select.end:
entry:
16B %0:anyi8 = COPY $a
Considering merging %0 with $a
Can only merge into reserved registers.
96B $a = COPY %6:gpr
Considering merging %6 with $a
Can only merge into reserved registers.
Remat: $a = LDImm 2
Shrink: %6 [80r,96r:0) 0@80r weight:0.000000e+00
All defs dead: 80r dead %6:gpr = LDImm 2
Shrunk: %6 [80r,80d:0) 0@80r weight:0.000000e+00
Deleting dead def 80r dead %6:gpr = LDImm 2
112B $x = COPY %2:yc
Not coalescable.
144B %4:imag16 = COPY killed $rs1
Considering merging %4 with $rs1
Can only merge into reserved registers.
:
select.false:
:
select.false9:
select.end8:
912B $rs8 = COPY %41:imag16
Considering merging %41 with $rs8
Can only merge into reserved registers.
944B $rs1 = COPY %4:imag16
Considering merging %4 with $rs1
Can only merge into reserved registers.
1296B $rs8 = COPY %27:imag16
Considering merging %27 with $rs8
Can only merge into reserved registers.
1328B $rs1 = COPY %4:imag16
Considering merging %4 with $rs1
Can only merge into reserved registers.
464B %68:ac = COPY %102:ac
Considering merging to Ac with %68 in %102
RHS = %68 [464r,544r:0) 0@464r weight:0.000000e+00
LHS = %102 [304r,336B:0)[432r,448B:1)[448B,464r:2) 0@304r 1@432r 2@448B-phi weight:0.000000e+00
merge %68:0@464r into %102:2@448B --> @448B
erased: 464r %68:ac = COPY %102:ac
AllocationOrder(Anyi8) = [ $a $x $y $rc2 $rc3 $rc4 $rc5 $rc6 $rc7 $rc8 $rc9 $rc10 $rc11 $rc12 $rc13 $rc14 $rc15 $rc16 $rc17 $rc18 $rc19 $rc20 $rc21 $rc22 $rc23 $rc24 $rc25 $rc26 $rc27 $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 $rc63 $rc64 $rc65 $rc66 $rc67 $rc68 $rc69 $rc70 $rc71 $rc72 $rc73 $rc74 $rc75 $rc76 $rc77 $rc78 $rc79 $rc80 $rc81 $rc82 $rc83 $rc84 $rc85 $rc86 $rc87 $rc88 $rc89 $rc90 $rc91 $rc92 $rc93 $rc94 $rc95 $rc96 $rc97 $rc98 $rc99 $rc100 $rc101 $rc102 $rc103 $rc104 $rc105 $rc106 $rc107 $rc108 $rc109 $rc110 $rc111 $rc112 $rc113 $rc114 $rc115 $rc116 $rc117 $rc118 $rc119 $rc120 $rc121 $rc122 $rc123 $rc124 $rc125 $rc126 $rc127 $rc128 $rc129 $rc130 $rc131 $rc132 $rc133 $rc134 $rc135 $rc136 $rc137 $rc138 $rc139 $rc140 $rc141 $rc142 $rc143 $rc144 $rc145 $rc146 $rc147 $rc148 $rc149 $rc150 $rc151 $rc152 $rc153 $rc154 $rc155 $rc156 $rc157 $rc158 $rc159 $rc160 $rc161 $rc162 $rc163 $rc164 $rc165 $rc166 $rc167 $rc168 $rc169 $rc170 $rc171 $rc172 $rc173 $rc174 $rc175 $rc176 $rc177 $rc178 $rc179 $rc180 $rc181 $rc182 $rc183 $rc184 $rc185 $rc186 $rc187 $rc188 $rc189 $rc190 $rc191 $rc192 $rc193 $rc194 $rc195 $rc196 $rc197 $rc198 $rc199 $rc200 $rc201 $rc202 $rc203 $rc204 $rc205 $rc206 $rc207 $rc208 $rc209 $rc210 $rc211 $rc212 $rc213 $rc214 $rc215 $rc216 $rc217 $rc218 $rc219 $rc220 $rc221 $rc222 $rc223 $rc224 $rc225 $rc226 $rc227 $rc228 $rc229 $rc230 $rc231 $rc232 $rc233 $rc234 $rc235 $rc236 $rc237 $rc238 $rc239 $rc240 $rc241 $rc242 $rc243 $rc244 $rc245 $rc246 $rc247 $rc248 $rc249 $rc250 $rc251 $rc252 $rc253 ]
AllocationOrder(Ac) = [ $a ] (sub-class)
updated: 544B STYIndir %102:ac, %4:imag16, %53:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
Success: %68 -> %102
Result = %102 [304r,336B:0)[432r,448B:1)[448B,544r:2) 0@304r 1@432r 2@448B-phi weight:0.000000e+00
480B %67:ac = COPY %101:ac
Considering merging to Ac with %67 in %101
RHS = %67 [480r,512r:0) 0@480r weight:0.000000e+00
LHS = %101 [288r,336B:0)[416r,448B:1)[448B,480r:2) 0@288r 1@416r 2@448B-phi weight:0.000000e+00
merge %67:0@480r into %101:2@448B --> @448B
erased: 480r %67:ac = COPY %101:ac
updated: 512B STYIndir %101:ac, %4:imag16, %2:yc :: (store 1 into %ir.0, !tbaa !2)
Success: %67 -> %101
Result = %101 [288r,336B:0)[416r,448B:1)[448B,512r:2) 0@288r 1@416r 2@448B-phi weight:0.000000e+00
496B %9:gpr = COPY %0:anyi8
Considering merging to GPR with %0 in %9
RHS = %0 [16r,496r:0) 0@16r weight:0.000000e+00
LHS = %9 [496r,560r:0) 0@496r weight:0.000000e+00
merge %9:0@496r into %0:0@16r --> @16r
erased: 496r %9:gpr = COPY %0:anyi8
AllocationOrder(GPR) = [ $a $x $y ] (sub-class)
updated: 16B %9:gpr = COPY $a
updated: 32B %1:gpr = COPY %9:gpr
Success: %0 -> %9
Result = %9 [16r,560r:0) 0@16r weight:0.000000e+00
32B %1:gpr = COPY %9:gpr
Considering merging to GPR with %9 in %1
RHS = %9 [16r,560r:0) 0@16r weight:0.000000e+00
LHS = %1 [32r,176r:0) 0@32r weight:0.000000e+00
merge %1:0@32r into %9:0@16r --> @16r
erased: 32r %1:gpr = COPY %9:gpr
updated: 16B %1:gpr = COPY $a
updated: 560B dead %92:cc = CMPImmTerm %1:gpr, 0, implicit-def dead $nz, implicit-def $z
Success: %9 -> %1
Result = %1 [16r,560r:0) 0@16r weight:0.000000e+00
256B %63:anyi8 = COPY %99:gpr
Considering merging to GPR with %99 in %63
RHS = %99 [224r,256r:0) 0@224r weight:0.000000e+00
LHS = %63 [256r,288r:0) 0@256r weight:0.000000e+00
merge %63:0@256r into %99:0@224r --> @224r
erased: 256r %63:anyi8 = COPY %99:gpr
updated: 224B %63:gpr = LDImm target-flags(lo) @_ZTV4SubB + 4
Success: %99 -> %63
Result = %63 [224r,288r:0) 0@224r weight:0.000000e+00
272B %64:anyi8 = COPY %100:gpr
Considering merging to GPR with %100 in %64
RHS = %100 [240r,272r:0) 0@240r weight:0.000000e+00
LHS = %64 [272r,304r:0) 0@272r weight:0.000000e+00
merge %64:0@272r into %100:0@240r --> @240r
erased: 272r %64:anyi8 = COPY %100:gpr
updated: 240B %64:gpr = LDImm target-flags(hi) @_ZTV4SubB + 4
Success: %100 -> %64
Result = %64 [240r,304r:0) 0@240r weight:0.000000e+00
288B %101:ac = COPY %63:gpr
Considering merging to Ac with %63 in %101
RHS = %63 [224r,288r:0) 0@224r weight:0.000000e+00
LHS = %101 [288r,336B:0)[416r,448B:1)[448B,512r:2) 0@288r 1@416r 2@448B-phi weight:0.000000e+00
merge %101:0@288r into %63:0@224r --> @224r
erased: 288r %101:ac = COPY %63:gpr
updated: 224B %101:ac = LDImm target-flags(lo) @_ZTV4SubB + 4
Success: %63 -> %101
Result = %101 [224r,336B:0)[416r,448B:1)[448B,512r:2) 0@224r 1@416r 2@448B-phi weight:0.000000e+00
304B %102:ac = COPY %64:gpr
Considering merging to Ac with %64 in %102
RHS = %64 [240r,304r:0) 0@240r weight:0.000000e+00
LHS = %102 [304r,336B:0)[432r,448B:1)[448B,544r:2) 0@304r 1@432r 2@448B-phi weight:0.000000e+00
merge %102:0@304r into %64:0@240r --> @240r
erased: 304r %102:ac = COPY %64:gpr
updated: 240B %102:ac = LDImm target-flags(hi) @_ZTV4SubB + 4
Success: %64 -> %102
Result = %102 [240r,336B:0)[432r,448B:1)[448B,544r:2) 0@240r 1@432r 2@448B-phi weight:0.000000e+00
384B %65:anyi8 = COPY %96:gpr
Considering merging to GPR with %96 in %65
RHS = %96 [352r,384r:0) 0@352r weight:0.000000e+00
LHS = %65 [384r,416r:0) 0@384r weight:0.000000e+00
merge %65:0@384r into %96:0@352r --> @352r
erased: 384r %65:anyi8 = COPY %96:gpr
updated: 352B %65:gpr = LDImm target-flags(lo) @_ZTV4SubA + 4
Success: %96 -> %65
Result = %65 [352r,416r:0) 0@352r weight:0.000000e+00
400B %66:anyi8 = COPY %97:gpr
Considering merging to GPR with %97 in %66
RHS = %97 [368r,400r:0) 0@368r weight:0.000000e+00
LHS = %66 [400r,432r:0) 0@400r weight:0.000000e+00
merge %66:0@400r into %97:0@368r --> @368r
erased: 400r %66:anyi8 = COPY %97:gpr
updated: 368B %66:gpr = LDImm target-flags(hi) @_ZTV4SubA + 4
Success: %97 -> %66
Result = %66 [368r,432r:0) 0@368r weight:0.000000e+00
416B %101:ac = COPY %65:gpr
Considering merging to Ac with %65 in %101
RHS = %65 [352r,416r:0) 0@352r weight:0.000000e+00
LHS = %101 [224r,336B:0)[416r,448B:1)[448B,512r:2) 0@224r 1@416r 2@448B-phi weight:0.000000e+00
merge %101:1@416r into %65:0@352r --> @352r
erased: 416r %101:ac = COPY %65:gpr
updated: 352B %101:ac = LDImm target-flags(lo) @_ZTV4SubA + 4
Success: %65 -> %101
Result = %101 [224r,336B:0)[352r,448B:1)[448B,512r:2) 0@224r 1@352r 2@448B-phi weight:0.000000e+00
432B %102:ac = COPY %66:gpr
Considering merging to Ac with %66 in %102
RHS = %66 [368r,432r:0) 0@368r weight:0.000000e+00
LHS = %102 [240r,336B:0)[432r,448B:1)[448B,544r:2) 0@240r 1@432r 2@448B-phi weight:0.000000e+00
merge %102:1@432r into %66:0@368r --> @368r
erased: 432r %102:ac = COPY %66:gpr
updated: 368B %102:ac = LDImm target-flags(hi) @_ZTV4SubA + 4
Success: %66 -> %102
Result = %102 [240r,336B:0)[368r,448B:1)[448B,544r:2) 0@240r 1@368r 2@448B-phi weight:0.000000e+00
640B %42:anyi8 = COPY %93:gpr
Considering merging to GPR with %93 in %42
RHS = %93 [608r,640r:0) 0@608r weight:0.000000e+00
LHS = %42 [640r,672r:0) 0@640r weight:0.000000e+00
merge %42:0@640r into %93:0@608r --> @608r
erased: 640r %42:anyi8 = COPY %93:gpr
updated: 608B %42:gpr = LDImm target-flags(lo) @_ZN4SubB2fnEv
Success: %93 -> %42
Result = %42 [608r,672r:0) 0@608r weight:0.000000e+00
656B %43:anyi8 = COPY %94:gpr
Considering merging to GPR with %94 in %43
RHS = %94 [624r,656r:0) 0@624r weight:0.000000e+00
LHS = %43 [656r,688r:0) 0@656r weight:0.000000e+00
merge %43:0@656r into %94:0@624r --> @624r
erased: 656r %43:anyi8 = COPY %94:gpr
updated: 624B %43:gpr = LDImm target-flags(hi) @_ZN4SubB2fnEv
Success: %94 -> %43
Result = %43 [624r,688r:0) 0@624r weight:0.000000e+00
672B %103:anyi8 = COPY %42:gpr
Considering merging to GPR with %42 in %103
RHS = %42 [608r,672r:0) 0@608r weight:0.000000e+00
LHS = %103 [672r,720B:0)[800r,832B:1)[832B,864r:2) 0@672r 1@800r 2@832B-phi weight:0.000000e+00
merge %103:0@672r into %42:0@608r --> @608r
erased: 672r %103:anyi8 = COPY %42:gpr
updated: 608B %103:gpr = LDImm target-flags(lo) @_ZN4SubB2fnEv
Success: %42 -> %103
Result = %103 [608r,720B:0)[800r,832B:1)[832B,864r:2) 0@608r 1@800r 2@832B-phi weight:0.000000e+00
688B %104:anyi8 = COPY %43:gpr
Considering merging to GPR with %43 in %104
RHS = %43 [624r,688r:0) 0@624r weight:0.000000e+00
LHS = %104 [688r,720B:0)[816r,832B:1)[832B,848r:2) 0@688r 1@816r 2@832B-phi weight:0.000000e+00
merge %104:0@688r into %43:0@624r --> @624r
erased: 688r %104:anyi8 = COPY %43:gpr
updated: 624B %104:gpr = LDImm target-flags(hi) @_ZN4SubB2fnEv
Success: %43 -> %104
Result = %104 [624r,720B:0)[816r,832B:1)[832B,848r:2) 0@624r 1@816r 2@832B-phi weight:0.000000e+00
768B %44:anyi8 = COPY %90:gpr
Considering merging to GPR with %90 in %44
RHS = %90 [736r,768r:0) 0@736r weight:0.000000e+00
LHS = %44 [768r,800r:0) 0@768r weight:0.000000e+00
merge %44:0@768r into %90:0@736r --> @736r
erased: 768r %44:anyi8 = COPY %90:gpr
updated: 736B %44:gpr = LDImm target-flags(lo) @_ZN4SubA2fnEv
Success: %90 -> %44
Result = %44 [736r,800r:0) 0@736r weight:0.000000e+00
784B %45:anyi8 = COPY %91:gpr
Considering merging to GPR with %91 in %45
RHS = %91 [752r,784r:0) 0@752r weight:0.000000e+00
LHS = %45 [784r,816r:0) 0@784r weight:0.000000e+00
merge %45:0@784r into %91:0@752r --> @752r
erased: 784r %45:anyi8 = COPY %91:gpr
updated: 752B %45:gpr = LDImm target-flags(hi) @_ZN4SubA2fnEv
Success: %91 -> %45
Result = %45 [752r,816r:0) 0@752r weight:0.000000e+00
800B %103:gpr = COPY %44:gpr
Considering merging to GPR with %44 in %103
RHS = %44 [736r,800r:0) 0@736r weight:0.000000e+00
LHS = %103 [608r,720B:0)[800r,832B:1)[832B,864r:2) 0@608r 1@800r 2@832B-phi weight:0.000000e+00
merge %103:1@800r into %44:0@736r --> @736r
erased: 800r %103:gpr = COPY %44:gpr
updated: 736B %103:gpr = LDImm target-flags(lo) @_ZN4SubA2fnEv
Success: %44 -> %103
Result = %103 [608r,720B:0)[736r,832B:1)[832B,864r:2) 0@608r 1@736r 2@832B-phi weight:0.000000e+00
816B %104:gpr = COPY %45:gpr
Considering merging to GPR with %45 in %104
RHS = %45 [752r,816r:0) 0@752r weight:0.000000e+00
LHS = %104 [624r,720B:0)[816r,832B:1)[832B,848r:2) 0@624r 1@816r 2@832B-phi weight:0.000000e+00
merge %104:1@816r into %45:0@752r --> @752r
erased: 816r %104:gpr = COPY %45:gpr
updated: 752B %104:gpr = LDImm target-flags(hi) @_ZN4SubA2fnEv
Success: %45 -> %104
Result = %104 [624r,720B:0)[752r,832B:1)[832B,848r:2) 0@624r 1@752r 2@832B-phi weight:0.000000e+00
848B %47:anyi8 = COPY %104:gpr
Considering merging to GPR with %47 in %104
RHS = %47 [848r,896r:0) 0@848r weight:0.000000e+00
LHS = %104 [624r,720B:0)[752r,832B:1)[832B,848r:2) 0@624r 1@752r 2@832B-phi weight:0.000000e+00
merge %47:0@848r into %104:2@832B --> @832B
erased: 848r %47:anyi8 = COPY %104:gpr
updated: 896B %41.subhi:imag16 = COPY %104:gpr
Success: %47 -> %104
Result = %104 [624r,720B:0)[752r,832B:1)[832B,896r:2) 0@624r 1@752r 2@832B-phi weight:0.000000e+00
864B %46:anyi8 = COPY %103:gpr
Considering merging to GPR with %46 in %103
RHS = %46 [864r,880r:0) 0@864r weight:0.000000e+00
LHS = %103 [608r,720B:0)[736r,832B:1)[832B,864r:2) 0@608r 1@736r 2@832B-phi weight:0.000000e+00
merge %46:0@864r into %103:2@832B --> @832B
erased: 864r %46:anyi8 = COPY %103:gpr
updated: 880B undef %41.sublo:imag16 = COPY %103:gpr
Success: %46 -> %103
Result = %103 [608r,720B:0)[736r,832B:1)[832B,880r:2) 0@608r 1@736r 2@832B-phi weight:0.000000e+00
880B undef %41.sublo:imag16 = COPY %103:gpr
Not coalescable.
896B %41.subhi:imag16 = COPY %104:gpr
Not coalescable.
1040B undef %34.sublo:imag16 = COPY %35:ac
Not coalescable.
1056B %34.subhi:imag16 = COPY %38:ac
Not coalescable.
1104B %83:cc = COPY %81:cc
Considering merging to Cc with %81 in %83
RHS = %81 [1088r,1104r:0) 0@1088r weight:0.000000e+00
LHS = %83 [1104r,1136r:0)[1136r,1168r:1) 0@1104r 1@1136r weight:0.000000e+00
merge %83:0@1104r into %81:0@1088r --> @1088r
erased: 1104r %83:cc = COPY %81:cc
AllocationOrder(Anyi1) = [ $c $alsb $xlsb $ylsb $rc2lsb $rc3lsb $rc4lsb $rc5lsb $rc6lsb $rc7lsb $rc8lsb $rc9lsb $rc10lsb $rc11lsb $rc12lsb $rc13lsb $rc14lsb $rc15lsb $rc16lsb $rc17lsb $rc18lsb $rc19lsb $rc20lsb $rc21lsb $rc22lsb $rc23lsb $rc24lsb $rc25lsb $rc26lsb $rc27lsb $v $rc30lsb $rc31lsb $rc32lsb $rc33lsb $rc34lsb $rc35lsb $rc36lsb $rc37lsb $rc38lsb $rc39lsb $rc40lsb $rc41lsb $rc42lsb $rc43lsb $rc44lsb $rc45lsb $rc46lsb $rc47lsb $rc48lsb $rc49lsb $rc50lsb $rc51lsb $rc52lsb $rc53lsb $rc54lsb $rc55lsb $rc56lsb $rc57lsb $rc58lsb $rc59lsb $rc60lsb $rc61lsb $rc62lsb $rc63lsb $rc64lsb $rc65lsb $rc66lsb $rc67lsb $rc68lsb $rc69lsb $rc70lsb $rc71lsb $rc72lsb $rc73lsb $rc74lsb $rc75lsb $rc76lsb $rc77lsb $rc78lsb $rc79lsb $rc80lsb $rc81lsb $rc82lsb $rc83lsb $rc84lsb $rc85lsb $rc86lsb $rc87lsb $rc88lsb $rc89lsb $rc90lsb $rc91lsb $rc92lsb $rc93lsb $rc94lsb $rc95lsb $rc96lsb $rc97lsb $rc98lsb $rc99lsb $rc100lsb $rc101lsb $rc102lsb $rc103lsb $rc104lsb $rc105lsb $rc106lsb $rc107lsb $rc108lsb $rc109lsb $rc110lsb $rc111lsb $rc112lsb $rc113lsb $rc114lsb $rc115lsb $rc116lsb $rc117lsb $rc118lsb $rc119lsb $rc120lsb $rc121lsb $rc122lsb $rc123lsb $rc124lsb $rc125lsb $rc126lsb $rc127lsb $rc128lsb $rc129lsb $rc130lsb $rc131lsb $rc132lsb $rc133lsb $rc134lsb $rc135lsb $rc136lsb $rc137lsb $rc138lsb $rc139lsb $rc140lsb $rc141lsb $rc142lsb $rc143lsb $rc144lsb $rc145lsb $rc146lsb $rc147lsb $rc148lsb $rc149lsb $rc150lsb $rc151lsb $rc152lsb $rc153lsb $rc154lsb $rc155lsb $rc156lsb $rc157lsb $rc158lsb $rc159lsb $rc160lsb $rc161lsb $rc162lsb $rc163lsb $rc164lsb $rc165lsb $rc166lsb $rc167lsb $rc168lsb $rc169lsb $rc170lsb $rc171lsb $rc172lsb $rc173lsb $rc174lsb $rc175lsb $rc176lsb $rc177lsb $rc178lsb $rc179lsb $rc180lsb $rc181lsb $rc182lsb $rc183lsb $rc184lsb $rc185lsb $rc186lsb $rc187lsb $rc188lsb $rc189lsb $rc190lsb $rc191lsb $rc192lsb $rc193lsb $rc194lsb $rc195lsb $rc196lsb $rc197lsb $rc198lsb $rc199lsb $rc200lsb $rc201lsb $rc202lsb $rc203lsb $rc204lsb $rc205lsb $rc206lsb $rc207lsb $rc208lsb $rc209lsb $rc210lsb $rc211lsb $rc212lsb $rc213lsb $rc214lsb $rc215lsb $rc216lsb $rc217lsb $rc218lsb $rc219lsb $rc220lsb $rc221lsb $rc222lsb $rc223lsb $rc224lsb $rc225lsb $rc226lsb $rc227lsb $rc228lsb $rc229lsb $rc230lsb $rc231lsb $rc232lsb $rc233lsb $rc234lsb $rc235lsb $rc236lsb $rc237lsb $rc238lsb $rc239lsb $rc240lsb $rc241lsb $rc242lsb $rc243lsb $rc244lsb $rc245lsb $rc246lsb $rc247lsb $rc248lsb $rc249lsb $rc250lsb $rc251lsb $rc252lsb $rc253lsb ]
AllocationOrder(Cc) = [ $c ] (sub-class)
updated: 1088B %83:cc = LDImm1 0
Success: %81 -> %83
Result = %83 [1088r,1136r:0)[1136r,1168r:1) 0@1088r 1@1136r weight:0.000000e+00
1120B %82:ac = COPY %35:ac
Considering merging to Ac with %35 in %82
RHS = %35 [1008r,1120r:0) 0@1008r weight:0.000000e+00
LHS = %82 [1120r,1136r:0)[1136r,1200r:1) 0@1120r 1@1136r weight:0.000000e+00
merge %82:0@1120r into %35:0@1008r --> @1008r
erased: 1120r %82:ac = COPY %35:ac
updated: 1008B %82:ac = LDYIndir %4:imag16, %89:yc :: (load 1 from %ir.3, !tbaa !2)
updated: 1040B undef %34.sublo:imag16 = COPY %82:ac
Success: %35 -> %82
Result = %82 [1008r,1136r:0)[1136r,1200r:1) 0@1008r 1@1136r weight:0.000000e+00
1152B %85:ac = COPY %38:ac
Considering merging to Ac with %38 in %85
RHS = %38 [1024r,1152r:0) 0@1024r weight:0.000000e+00
LHS = %85 [1152r,1184r:0)[1184r,1216r:1) 0@1152r 1@1184r weight:0.000000e+00
merge %85:0@1152r into %38:0@1024r --> @1024r
erased: 1152r %85:ac = COPY %38:ac
updated: 1024B %85:ac = LDYIndir %4:imag16, %53:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
updated: 1056B %34.subhi:imag16 = COPY %85:ac
Success: %38 -> %85
Result = %85 [1024r,1184r:0)[1184r,1216r:1) 0@1024r 1@1184r weight:0.000000e+00
1168B %86:cc = COPY %83:cc
Considering merging to Cc with %83 in %86
RHS = %83 [1088r,1136r:0)[1136r,1168r:1) 0@1088r 1@1136r weight:0.000000e+00
LHS = %86 [1168r,1184r:0)[1184r,1184d:1) 0@1168r 1@1184r weight:0.000000e+00
merge %86:0@1168r into %83:1@1136r --> @1136r
erased: 1168r %86:cc = COPY %83:cc
updated: 1088B %86:cc = LDImm1 0
updated: 1136B %82:ac, %86:cc, dead %88:vc = ADCImm %82:ac(tied-def 0), 2, %86:cc(tied-def 1)
Success: %83 -> %86
Result = %86 [1088r,1136r:2)[1136r,1184r:0)[1184r,1184d:1) 0@1136r 1@1184r 2@1088r weight:0.000000e+00
1200B undef %14.sublo:imag16 = COPY %82:ac
Not coalescable.
1216B %14.subhi:imag16 = COPY %85:ac
Not coalescable.
1264B undef %27.sublo:imag16 = COPY %28:ac
Not coalescable.
1280B %27.subhi:imag16 = COPY %31:ac
Not coalescable.
912B $rs8 = COPY %41:imag16
Considering merging %41 with $rs8
Can only merge into reserved registers.
944B $rs1 = COPY %4:imag16
Considering merging %4 with $rs1
Can only merge into reserved registers.
1296B $rs8 = COPY %27:imag16
Considering merging %27 with $rs8
Can only merge into reserved registers.
1328B $rs1 = COPY %4:imag16
Considering merging %4 with $rs1
Can only merge into reserved registers.
Trying to inflate 18 regs.
********** INTERVALS **********
ALSB [0B,16r:0)[96r,128r:1) 0@0B-phi 1@96r
%1 [16r,560r:0) 0@16r weight:0.000000e+00
%2 [48r,512r:0) 0@48r weight:0.000000e+00
%4 [144r,1328r:0) 0@144r weight:0.000000e+00
%14 [1200r,1216r:0)[1216r,1248r:1) 0@1200r 1@1216r L0000000000000002 [1200r,1248r:0) 0@1200r L0000000000000020 [1216r,1248r:0) 0@1216r weight:0.000000e+00
%27 [1264r,1280r:0)[1280r,1296r:1) 0@1264r 1@1280r L0000000000000002 [1264r,1296r:0) 0@1264r L0000000000000020 [1280r,1296r:0) 0@1280r weight:0.000000e+00
%28 [1232r,1264r:0) 0@1232r weight:0.000000e+00
%31 [1248r,1280r:0) 0@1248r weight:0.000000e+00
%33 [1072r,1232r:0) 0@1072r weight:0.000000e+00
%34 [1040r,1056r:0)[1056r,1232r:1) 0@1040r 1@1056r L0000000000000002 [1040r,1232r:0) 0@1040r L0000000000000020 [1056r,1232r:0) 0@1056r weight:0.000000e+00
%41 [880r,896r:0)[896r,912r:1) 0@880r 1@896r L0000000000000002 [880r,912r:0) 0@880r L0000000000000020 [896r,912r:0) 0@896r weight:0.000000e+00
%53 [528r,1248r:0) 0@528r weight:0.000000e+00
%82 [1008r,1136r:0)[1136r,1200r:1) 0@1008r 1@1136r weight:0.000000e+00
%85 [1024r,1184r:0)[1184r,1216r:1) 0@1024r 1@1184r weight:0.000000e+00
%86 [1088r,1136r:2)[1136r,1184r:0)[1184r,1184d:1) 0@1136r 1@1184r 2@1088r weight:0.000000e+00
%87 [1184r,1184d:0) 0@1184r weight:0.000000e+00
%88 [1136r,1136d:0) 0@1136r weight:0.000000e+00
%89 [992r,1008r:0) 0@992r weight:0.000000e+00
%92 [560r,560d:0) 0@560r weight:0.000000e+00
%98 [176r,176d:0) 0@176r weight:0.000000e+00
%101 [224r,336B:0)[352r,448B:1)[448B,512r:2) 0@224r 1@352r 2@448B-phi weight:0.000000e+00
%102 [240r,336B:0)[368r,448B:1)[448B,544r:2) 0@240r 1@368r 2@448B-phi weight:0.000000e+00
%103 [608r,720B:0)[736r,832B:1)[832B,880r:2) 0@608r 1@736r 2@832B-phi weight:0.000000e+00
%104 [624r,720B:0)[752r,832B:1)[832B,896r:2) 0@624r 1@752r 2@832B-phi weight:0.000000e+00
RegMasks: 128r 960r 1344r
********** MACHINEINSTRS **********
# Machine code for function _Z11testIndCallc: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
successors: %bb.1(0x30000000), %bb.2(0x50000000); %bb.1(37.50%), %bb.2(62.50%)
liveins: $a
16B %1:gpr = COPY $a
48B %2:yc = LDImm 0
64B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
96B $a = LDImm 2
112B $x = COPY %2:yc
128B JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $a, implicit killed $x, implicit-def $rs1
144B %4:imag16 = COPY killed $rs1
160B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
176B dead %98:cc = CMPImmTerm %1:gpr, 0, implicit-def dead $nz, implicit-def $z
192B BR %bb.2, killed $z, 0
208B bb.1:
; predecessors: %bb.0
successors: %bb.3(0x80000000); %bb.3(100.00%)
224B %101:ac = LDImm target-flags(lo) @_ZTV4SubB + 4
240B %102:ac = LDImm target-flags(hi) @_ZTV4SubB + 4
320B JMP %bb.3
336B bb.2.select.false:
; predecessors: %bb.0
successors: %bb.3(0x80000000); %bb.3(100.00%)
352B %101:ac = LDImm target-flags(lo) @_ZTV4SubA + 4
368B %102:ac = LDImm target-flags(hi) @_ZTV4SubA + 4
448B bb.3.select.end:
; predecessors: %bb.2, %bb.1
successors: %bb.4(0x30000000), %bb.5(0x50000000); %bb.4(37.50%), %bb.5(62.50%)
512B STYIndir %101:ac, %4:imag16, %2:yc :: (store 1 into %ir.0, !tbaa !2)
528B %53:yc = LDImm 1
544B STYIndir %102:ac, %4:imag16, %53:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
560B dead %92:cc = CMPImmTerm %1:gpr, 0, implicit-def dead $nz, implicit-def $z
576B BR %bb.5, killed $z, 0
592B bb.4:
; predecessors: %bb.3
successors: %bb.6(0x80000000); %bb.6(100.00%)
608B %103:gpr = LDImm target-flags(lo) @_ZN4SubB2fnEv
624B %104:gpr = LDImm target-flags(hi) @_ZN4SubB2fnEv
704B JMP %bb.6
720B bb.5.select.false9:
; predecessors: %bb.3
successors: %bb.6(0x80000000); %bb.6(100.00%)
736B %103:gpr = LDImm target-flags(lo) @_ZN4SubA2fnEv
752B %104:gpr = LDImm target-flags(hi) @_ZN4SubA2fnEv
832B bb.6.select.end8:
; predecessors: %bb.5, %bb.4
880B undef %41.sublo:imag16 = COPY %103:gpr
896B %41.subhi:imag16 = COPY %104:gpr
912B $rs8 = COPY %41:imag16
928B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
944B $rs1 = COPY %4:imag16
960B JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit killed $rs8, implicit killed $rs1
976B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
992B %89:yc = LDImm 0
1008B %82:ac = LDYIndir %4:imag16, %89:yc :: (load 1 from %ir.3, !tbaa !2)
1024B %85:ac = LDYIndir %4:imag16, %53:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
1040B undef %34.sublo:imag16 = COPY %82:ac
1056B %34.subhi:imag16 = COPY %85:ac
1072B %33:yc = LDImm 2
1088B %86:cc = LDImm1 0
1136B %82:ac, %86:cc, dead %88:vc = ADCImm %82:ac(tied-def 0), 2, %86:cc(tied-def 1)
1184B %85:ac, dead %86:cc, dead %87:vc = ADCImm %85:ac(tied-def 0), 0, %86:cc(tied-def 1)
1200B undef %14.sublo:imag16 = COPY %82:ac
1216B %14.subhi:imag16 = COPY %85:ac
1232B %28:ac = LDYIndir %34:imag16, %33:yc :: (load 1 from %ir.vfn3)
1248B %31:ac = LDYIndir %14:imag16, %53:yc :: (load 1 from %ir.vfn3 + 1)
1264B undef %27.sublo:imag16 = COPY %28:ac
1280B %27.subhi:imag16 = COPY %31:ac
1296B $rs8 = COPY %27:imag16
1312B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
1328B $rs1 = COPY %4:imag16
1344B JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit killed $rs8, implicit killed $rs1
1360B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
1376B RTS
# End machine code for function _Z11testIndCallc.
Renaming independent subregister live ranges in _Z11testIndCallc
Before MISched:
# Machine code for function _Z11testIndCallc: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
bb.0.entry:
successors: %bb.1(0x30000000), %bb.2(0x50000000); %bb.1(37.50%), %bb.2(62.50%)
liveins: $a
%1:gpr = COPY $a
%2:yc = LDImm 0
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
$a = LDImm 2
$x = COPY %2:yc
JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $a, implicit killed $x, implicit-def $rs1
%4:imag16 = COPY killed $rs1
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
dead %98:cc = CMPImmTerm %1:gpr, 0, implicit-def dead $nz, implicit-def $z
BR %bb.2, killed $z, 0
bb.1:
; predecessors: %bb.0
successors: %bb.3(0x80000000); %bb.3(100.00%)
%101:ac = LDImm target-flags(lo) @_ZTV4SubB + 4
%102:ac = LDImm target-flags(hi) @_ZTV4SubB + 4
JMP %bb.3
bb.2.select.false:
; predecessors: %bb.0
successors: %bb.3(0x80000000); %bb.3(100.00%)
%101:ac = LDImm target-flags(lo) @_ZTV4SubA + 4
%102:ac = LDImm target-flags(hi) @_ZTV4SubA + 4
bb.3.select.end:
; predecessors: %bb.2, %bb.1
successors: %bb.4(0x30000000), %bb.5(0x50000000); %bb.4(37.50%), %bb.5(62.50%)
STYIndir %101:ac, %4:imag16, %2:yc :: (store 1 into %ir.0, !tbaa !2)
%53:yc = LDImm 1
STYIndir %102:ac, %4:imag16, %53:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
dead %92:cc = CMPImmTerm %1:gpr, 0, implicit-def dead $nz, implicit-def $z
BR %bb.5, killed $z, 0
bb.4:
; predecessors: %bb.3
successors: %bb.6(0x80000000); %bb.6(100.00%)
%103:gpr = LDImm target-flags(lo) @_ZN4SubB2fnEv
%104:gpr = LDImm target-flags(hi) @_ZN4SubB2fnEv
JMP %bb.6
bb.5.select.false9:
; predecessors: %bb.3
successors: %bb.6(0x80000000); %bb.6(100.00%)
%103:gpr = LDImm target-flags(lo) @_ZN4SubA2fnEv
%104:gpr = LDImm target-flags(hi) @_ZN4SubA2fnEv
bb.6.select.end8:
; predecessors: %bb.5, %bb.4
undef %41.sublo:imag16 = COPY %103:gpr
%41.subhi:imag16 = COPY %104:gpr
$rs8 = COPY %41:imag16
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
$rs1 = COPY %4:imag16
JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit killed $rs8, implicit killed $rs1
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
%89:yc = LDImm 0
%82:ac = LDYIndir %4:imag16, %89:yc :: (load 1 from %ir.3, !tbaa !2)
%85:ac = LDYIndir %4:imag16, %53:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
undef %34.sublo:imag16 = COPY %82:ac
%34.subhi:imag16 = COPY %85:ac
%33:yc = LDImm 2
%86:cc = LDImm1 0
%82:ac, %86:cc, dead %88:vc = ADCImm %82:ac(tied-def 0), 2, %86:cc(tied-def 1)
%85:ac, dead %86:cc, dead %87:vc = ADCImm %85:ac(tied-def 0), 0, %86:cc(tied-def 1)
undef %14.sublo:imag16 = COPY %82:ac
%14.subhi:imag16 = COPY %85:ac
%28:ac = LDYIndir %34:imag16, %33:yc :: (load 1 from %ir.vfn3)
%31:ac = LDYIndir %14:imag16, %53:yc :: (load 1 from %ir.vfn3 + 1)
undef %27.sublo:imag16 = COPY %28:ac
%27.subhi:imag16 = COPY %31:ac
$rs8 = COPY %27:imag16
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
$rs1 = COPY %4:imag16
JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit killed $rs8, implicit killed $rs1
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
RTS
# End machine code for function _Z11testIndCallc.
AllocationOrder(Anyi8) = [ $a $x $y $rc2 $rc3 $rc4 $rc5 $rc6 $rc7 $rc8 $rc9 $rc10 $rc11 $rc12 $rc13 $rc14 $rc15 $rc16 $rc17 $rc18 $rc19 $rc20 $rc21 $rc22 $rc23 $rc24 $rc25 $rc26 $rc27 $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 $rc63 $rc64 $rc65 $rc66 $rc67 $rc68 $rc69 $rc70 $rc71 $rc72 $rc73 $rc74 $rc75 $rc76 $rc77 $rc78 $rc79 $rc80 $rc81 $rc82 $rc83 $rc84 $rc85 $rc86 $rc87 $rc88 $rc89 $rc90 $rc91 $rc92 $rc93 $rc94 $rc95 $rc96 $rc97 $rc98 $rc99 $rc100 $rc101 $rc102 $rc103 $rc104 $rc105 $rc106 $rc107 $rc108 $rc109 $rc110 $rc111 $rc112 $rc113 $rc114 $rc115 $rc116 $rc117 $rc118 $rc119 $rc120 $rc121 $rc122 $rc123 $rc124 $rc125 $rc126 $rc127 $rc128 $rc129 $rc130 $rc131 $rc132 $rc133 $rc134 $rc135 $rc136 $rc137 $rc138 $rc139 $rc140 $rc141 $rc142 $rc143 $rc144 $rc145 $rc146 $rc147 $rc148 $rc149 $rc150 $rc151 $rc152 $rc153 $rc154 $rc155 $rc156 $rc157 $rc158 $rc159 $rc160 $rc161 $rc162 $rc163 $rc164 $rc165 $rc166 $rc167 $rc168 $rc169 $rc170 $rc171 $rc172 $rc173 $rc174 $rc175 $rc176 $rc177 $rc178 $rc179 $rc180 $rc181 $rc182 $rc183 $rc184 $rc185 $rc186 $rc187 $rc188 $rc189 $rc190 $rc191 $rc192 $rc193 $rc194 $rc195 $rc196 $rc197 $rc198 $rc199 $rc200 $rc201 $rc202 $rc203 $rc204 $rc205 $rc206 $rc207 $rc208 $rc209 $rc210 $rc211 $rc212 $rc213 $rc214 $rc215 $rc216 $rc217 $rc218 $rc219 $rc220 $rc221 $rc222 $rc223 $rc224 $rc225 $rc226 $rc227 $rc228 $rc229 $rc230 $rc231 $rc232 $rc233 $rc234 $rc235 $rc236 $rc237 $rc238 $rc239 $rc240 $rc241 $rc242 $rc243 $rc244 $rc245 $rc246 $rc247 $rc248 $rc249 $rc250 $rc251 $rc252 $rc253 ]
********** MI Scheduling **********
_Z11testIndCallc:%bb.0 entry
From: $a = LDImm 2
To: JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $a, implicit killed $x, implicit-def $rs1
RegionInstrs: 2
ScheduleDAGMILive::schedule starting
GenericScheduler RegionPolicy: ShouldTrackPressure=1 OnlyTopDown=0 OnlyBottomUp=0
Max Pressure: Ac=1
Xc=1
Yc=1
XY=2
GPR_LSB=3
MOSAsmParamRegClass=3
CV_GPR_LSB=3
CV_GPR_LSB_with_MOSAsmParamRegClass=3
CV_GPR_LSB_with_Pc=3
Imag8=2
GPR_LSB_with_Imag8=3
Anyi1=3
Anyi1_with_Pc=3
Live In: %2
Live Out: RC2LSB RC3LSB %2
Live Thru: Yc=1
XY=1
GPR_LSB=1
MOSAsmParamRegClass=1
CV_GPR_LSB=1
CV_GPR_LSB_with_MOSAsmParamRegClass=1
CV_GPR_LSB_with_Pc=1
GPR_LSB_with_Imag8=1
Anyi1=1
Anyi1_with_Pc=1
LiveReg: %2
UpdateRegP: SU(1) $x = COPY %2:yc
to Xc -1 XY -1 GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Top Pressure:
Yc=1
XY=1
GPR_LSB=1
MOSAsmParamRegClass=1
CV_GPR_LSB=1
CV_GPR_LSB_with_MOSAsmParamRegClass=1
CV_GPR_LSB_with_Pc=1
GPR_LSB_with_Imag8=1
Anyi1=1
Anyi1_with_Pc=1
Bottom Pressure:
Ac=1
Xc=1
Yc=1
XY=2
GPR_LSB=3
MOSAsmParamRegClass=3
CV_GPR_LSB=3
CV_GPR_LSB_with_MOSAsmParamRegClass=3
CV_GPR_LSB_with_Pc=3
Imag8=1
GPR_LSB_with_Imag8=3
Anyi1=3
Anyi1_with_Pc=3
AllocationOrder(Anyi1) = [ $c $alsb $xlsb $ylsb $rc2lsb $rc3lsb $rc4lsb $rc5lsb $rc6lsb $rc7lsb $rc8lsb $rc9lsb $rc10lsb $rc11lsb $rc12lsb $rc13lsb $rc14lsb $rc15lsb $rc16lsb $rc17lsb $rc18lsb $rc19lsb $rc20lsb $rc21lsb $rc22lsb $rc23lsb $rc24lsb $rc25lsb $rc26lsb $rc27lsb $v $rc30lsb $rc31lsb $rc32lsb $rc33lsb $rc34lsb $rc35lsb $rc36lsb $rc37lsb $rc38lsb $rc39lsb $rc40lsb $rc41lsb $rc42lsb $rc43lsb $rc44lsb $rc45lsb $rc46lsb $rc47lsb $rc48lsb $rc49lsb $rc50lsb $rc51lsb $rc52lsb $rc53lsb $rc54lsb $rc55lsb $rc56lsb $rc57lsb $rc58lsb $rc59lsb $rc60lsb $rc61lsb $rc62lsb $rc63lsb $rc64lsb $rc65lsb $rc66lsb $rc67lsb $rc68lsb $rc69lsb $rc70lsb $rc71lsb $rc72lsb $rc73lsb $rc74lsb $rc75lsb $rc76lsb $rc77lsb $rc78lsb $rc79lsb $rc80lsb $rc81lsb $rc82lsb $rc83lsb $rc84lsb $rc85lsb $rc86lsb $rc87lsb $rc88lsb $rc89lsb $rc90lsb $rc91lsb $rc92lsb $rc93lsb $rc94lsb $rc95lsb $rc96lsb $rc97lsb $rc98lsb $rc99lsb $rc100lsb $rc101lsb $rc102lsb $rc103lsb $rc104lsb $rc105lsb $rc106lsb $rc107lsb $rc108lsb $rc109lsb $rc110lsb $rc111lsb $rc112lsb $rc113lsb $rc114lsb $rc115lsb $rc116lsb $rc117lsb $rc118lsb $rc119lsb $rc120lsb $rc121lsb $rc122lsb $rc123lsb $rc124lsb $rc125lsb $rc126lsb $rc127lsb $rc128lsb $rc129lsb $rc130lsb $rc131lsb $rc132lsb $rc133lsb $rc134lsb $rc135lsb $rc136lsb $rc137lsb $rc138lsb $rc139lsb $rc140lsb $rc141lsb $rc142lsb $rc143lsb $rc144lsb $rc145lsb $rc146lsb $rc147lsb $rc148lsb $rc149lsb $rc150lsb $rc151lsb $rc152lsb $rc153lsb $rc154lsb $rc155lsb $rc156lsb $rc157lsb $rc158lsb $rc159lsb $rc160lsb $rc161lsb $rc162lsb $rc163lsb $rc164lsb $rc165lsb $rc166lsb $rc167lsb $rc168lsb $rc169lsb $rc170lsb $rc171lsb $rc172lsb $rc173lsb $rc174lsb $rc175lsb $rc176lsb $rc177lsb $rc178lsb $rc179lsb $rc180lsb $rc181lsb $rc182lsb $rc183lsb $rc184lsb $rc185lsb $rc186lsb $rc187lsb $rc188lsb $rc189lsb $rc190lsb $rc191lsb $rc192lsb $rc193lsb $rc194lsb $rc195lsb $rc196lsb $rc197lsb $rc198lsb $rc199lsb $rc200lsb $rc201lsb $rc202lsb $rc203lsb $rc204lsb $rc205lsb $rc206lsb $rc207lsb $rc208lsb $rc209lsb $rc210lsb $rc211lsb $rc212lsb $rc213lsb $rc214lsb $rc215lsb $rc216lsb $rc217lsb $rc218lsb $rc219lsb $rc220lsb $rc221lsb $rc222lsb $rc223lsb $rc224lsb $rc225lsb $rc226lsb $rc227lsb $rc228lsb $rc229lsb $rc230lsb $rc231lsb $rc232lsb $rc233lsb $rc234lsb $rc235lsb $rc236lsb $rc237lsb $rc238lsb $rc239lsb $rc240lsb $rc241lsb $rc242lsb $rc243lsb $rc244lsb $rc245lsb $rc246lsb $rc247lsb $rc248lsb $rc249lsb $rc250lsb $rc251lsb $rc252lsb $rc253lsb ]
AllocationOrder(Cc) = [ $c ] (sub-class)
AllocationOrder(Vc) = [ $v ] (sub-class)
AllocationOrder(Ac) = [ $a ] (sub-class)
AllocationOrder(Xc) = [ $x ] (sub-class)
AllocationOrder(Yc) = [ $y ] (sub-class)
AllocationOrder(XY) = [ $x $y ] (sub-class)
AllocationOrder(GPR_LSB) = [ $alsb $xlsb $ylsb ] (sub-class)
AllocationOrder(Pc) = [ $p ]
AllocationOrder(GPR_LSB) = [ $alsb $xlsb $ylsb ] (sub-class)
AllocationOrder(CV_GPR_LSB) = [ $c $v $alsb $xlsb $ylsb ] (sub-class)
AllocationOrder(CV_GPR_LSB) = [ $c $v $alsb $xlsb $ylsb ] (sub-class)
AllocationOrder(CV_GPR_LSB) = [ $c $v $alsb $xlsb $ylsb ] (sub-class)
AllocationOrder(AImag8) = [ $a $rc2 $rc3 $rc4 $rc5 $rc6 $rc7 $rc8 $rc9 $rc10 $rc11 $rc12 $rc13 $rc14 $rc15 $rc16 $rc17 $rc18 $rc19 $rc20 $rc21 $rc22 $rc23 $rc24 $rc25 $rc26 $rc27 $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 $rc63 $rc64 $rc65 $rc66 $rc67 $rc68 $rc69 $rc70 $rc71 $rc72 $rc73 $rc74 $rc75 $rc76 $rc77 $rc78 $rc79 $rc80 $rc81 $rc82 $rc83 $rc84 $rc85 $rc86 $rc87 $rc88 $rc89 $rc90 $rc91 $rc92 $rc93 $rc94 $rc95 $rc96 $rc97 $rc98 $rc99 $rc100 $rc101 $rc102 $rc103 $rc104 $rc105 $rc106 $rc107 $rc108 $rc109 $rc110 $rc111 $rc112 $rc113 $rc114 $rc115 $rc116 $rc117 $rc118 $rc119 $rc120 $rc121 $rc122 $rc123 $rc124 $rc125 $rc126 $rc127 $rc128 $rc129 $rc130 $rc131 $rc132 $rc133 $rc134 $rc135 $rc136 $rc137 $rc138 $rc139 $rc140 $rc141 $rc142 $rc143 $rc144 $rc145 $rc146 $rc147 $rc148 $rc149 $rc150 $rc151 $rc152 $rc153 $rc154 $rc155 $rc156 $rc157 $rc158 $rc159 $rc160 $rc161 $rc162 $rc163 $rc164 $rc165 $rc166 $rc167 $rc168 $rc169 $rc170 $rc171 $rc172 $rc173 $rc174 $rc175 $rc176 $rc177 $rc178 $rc179 $rc180 $rc181 $rc182 $rc183 $rc184 $rc185 $rc186 $rc187 $rc188 $rc189 $rc190 $rc191 $rc192 $rc193 $rc194 $rc195 $rc196 $rc197 $rc198 $rc199 $rc200 $rc201 $rc202 $rc203 $rc204 $rc205 $rc206 $rc207 $rc208 $rc209 $rc210 $rc211 $rc212 $rc213 $rc214 $rc215 $rc216 $rc217 $rc218 $rc219 $rc220 $rc221 $rc222 $rc223 $rc224 $rc225 $rc226 $rc227 $rc228 $rc229 $rc230 $rc231 $rc232 $rc233 $rc234 $rc235 $rc236 $rc237 $rc238 $rc239 $rc240 $rc241 $rc242 $rc243 $rc244 $rc245 $rc246 $rc247 $rc248 $rc249 $rc250 $rc251 $rc252 $rc253 ] (sub-class)
AllocationOrder(Anyi8) = [ $a $x $y $rc2 $rc3 $rc4 $rc5 $rc6 $rc7 $rc8 $rc9 $rc10 $rc11 $rc12 $rc13 $rc14 $rc15 $rc16 $rc17 $rc18 $rc19 $rc20 $rc21 $rc22 $rc23 $rc24 $rc25 $rc26 $rc27 $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 $rc63 $rc64 $rc65 $rc66 $rc67 $rc68 $rc69 $rc70 $rc71 $rc72 $rc73 $rc74 $rc75 $rc76 $rc77 $rc78 $rc79 $rc80 $rc81 $rc82 $rc83 $rc84 $rc85 $rc86 $rc87 $rc88 $rc89 $rc90 $rc91 $rc92 $rc93 $rc94 $rc95 $rc96 $rc97 $rc98 $rc99 $rc100 $rc101 $rc102 $rc103 $rc104 $rc105 $rc106 $rc107 $rc108 $rc109 $rc110 $rc111 $rc112 $rc113 $rc114 $rc115 $rc116 $rc117 $rc118 $rc119 $rc120 $rc121 $rc122 $rc123 $rc124 $rc125 $rc126 $rc127 $rc128 $rc129 $rc130 $rc131 $rc132 $rc133 $rc134 $rc135 $rc136 $rc137 $rc138 $rc139 $rc140 $rc141 $rc142 $rc143 $rc144 $rc145 $rc146 $rc147 $rc148 $rc149 $rc150 $rc151 $rc152 $rc153 $rc154 $rc155 $rc156 $rc157 $rc158 $rc159 $rc160 $rc161 $rc162 $rc163 $rc164 $rc165 $rc166 $rc167 $rc168 $rc169 $rc170 $rc171 $rc172 $rc173 $rc174 $rc175 $rc176 $rc177 $rc178 $rc179 $rc180 $rc181 $rc182 $rc183 $rc184 $rc185 $rc186 $rc187 $rc188 $rc189 $rc190 $rc191 $rc192 $rc193 $rc194 $rc195 $rc196 $rc197 $rc198 $rc199 $rc200 $rc201 $rc202 $rc203 $rc204 $rc205 $rc206 $rc207 $rc208 $rc209 $rc210 $rc211 $rc212 $rc213 $rc214 $rc215 $rc216 $rc217 $rc218 $rc219 $rc220 $rc221 $rc222 $rc223 $rc224 $rc225 $rc226 $rc227 $rc228 $rc229 $rc230 $rc231 $rc232 $rc233 $rc234 $rc235 $rc236 $rc237 $rc238 $rc239 $rc240 $rc241 $rc242 $rc243 $rc244 $rc245 $rc246 $rc247 $rc248 $rc249 $rc250 $rc251 $rc252 $rc253 ]
AllocationOrder(Anyi1) = [ $c $alsb $xlsb $ylsb $rc2lsb $rc3lsb $rc4lsb $rc5lsb $rc6lsb $rc7lsb $rc8lsb $rc9lsb $rc10lsb $rc11lsb $rc12lsb $rc13lsb $rc14lsb $rc15lsb $rc16lsb $rc17lsb $rc18lsb $rc19lsb $rc20lsb $rc21lsb $rc22lsb $rc23lsb $rc24lsb $rc25lsb $rc26lsb $rc27lsb $v $rc30lsb $rc31lsb $rc32lsb $rc33lsb $rc34lsb $rc35lsb $rc36lsb $rc37lsb $rc38lsb $rc39lsb $rc40lsb $rc41lsb $rc42lsb $rc43lsb $rc44lsb $rc45lsb $rc46lsb $rc47lsb $rc48lsb $rc49lsb $rc50lsb $rc51lsb $rc52lsb $rc53lsb $rc54lsb $rc55lsb $rc56lsb $rc57lsb $rc58lsb $rc59lsb $rc60lsb $rc61lsb $rc62lsb $rc63lsb $rc64lsb $rc65lsb $rc66lsb $rc67lsb $rc68lsb $rc69lsb $rc70lsb $rc71lsb $rc72lsb $rc73lsb $rc74lsb $rc75lsb $rc76lsb $rc77lsb $rc78lsb $rc79lsb $rc80lsb $rc81lsb $rc82lsb $rc83lsb $rc84lsb $rc85lsb $rc86lsb $rc87lsb $rc88lsb $rc89lsb $rc90lsb $rc91lsb $rc92lsb $rc93lsb $rc94lsb $rc95lsb $rc96lsb $rc97lsb $rc98lsb $rc99lsb $rc100lsb $rc101lsb $rc102lsb $rc103lsb $rc104lsb $rc105lsb $rc106lsb $rc107lsb $rc108lsb $rc109lsb $rc110lsb $rc111lsb $rc112lsb $rc113lsb $rc114lsb $rc115lsb $rc116lsb $rc117lsb $rc118lsb $rc119lsb $rc120lsb $rc121lsb $rc122lsb $rc123lsb $rc124lsb $rc125lsb $rc126lsb $rc127lsb $rc128lsb $rc129lsb $rc130lsb $rc131lsb $rc132lsb $rc133lsb $rc134lsb $rc135lsb $rc136lsb $rc137lsb $rc138lsb $rc139lsb $rc140lsb $rc141lsb $rc142lsb $rc143lsb $rc144lsb $rc145lsb $rc146lsb $rc147lsb $rc148lsb $rc149lsb $rc150lsb $rc151lsb $rc152lsb $rc153lsb $rc154lsb $rc155lsb $rc156lsb $rc157lsb $rc158lsb $rc159lsb $rc160lsb $rc161lsb $rc162lsb $rc163lsb $rc164lsb $rc165lsb $rc166lsb $rc167lsb $rc168lsb $rc169lsb $rc170lsb $rc171lsb $rc172lsb $rc173lsb $rc174lsb $rc175lsb $rc176lsb $rc177lsb $rc178lsb $rc179lsb $rc180lsb $rc181lsb $rc182lsb $rc183lsb $rc184lsb $rc185lsb $rc186lsb $rc187lsb $rc188lsb $rc189lsb $rc190lsb $rc191lsb $rc192lsb $rc193lsb $rc194lsb $rc195lsb $rc196lsb $rc197lsb $rc198lsb $rc199lsb $rc200lsb $rc201lsb $rc202lsb $rc203lsb $rc204lsb $rc205lsb $rc206lsb $rc207lsb $rc208lsb $rc209lsb $rc210lsb $rc211lsb $rc212lsb $rc213lsb $rc214lsb $rc215lsb $rc216lsb $rc217lsb $rc218lsb $rc219lsb $rc220lsb $rc221lsb $rc222lsb $rc223lsb $rc224lsb $rc225lsb $rc226lsb $rc227lsb $rc228lsb $rc229lsb $rc230lsb $rc231lsb $rc232lsb $rc233lsb $rc234lsb $rc235lsb $rc236lsb $rc237lsb $rc238lsb $rc239lsb $rc240lsb $rc241lsb $rc242lsb $rc243lsb $rc244lsb $rc245lsb $rc246lsb $rc247lsb $rc248lsb $rc249lsb $rc250lsb $rc251lsb $rc252lsb $rc253lsb ]
AllocationOrder(Anyi1) = [ $c $alsb $xlsb $ylsb $rc2lsb $rc3lsb $rc4lsb $rc5lsb $rc6lsb $rc7lsb $rc8lsb $rc9lsb $rc10lsb $rc11lsb $rc12lsb $rc13lsb $rc14lsb $rc15lsb $rc16lsb $rc17lsb $rc18lsb $rc19lsb $rc20lsb $rc21lsb $rc22lsb $rc23lsb $rc24lsb $rc25lsb $rc26lsb $rc27lsb $v $rc30lsb $rc31lsb $rc32lsb $rc33lsb $rc34lsb $rc35lsb $rc36lsb $rc37lsb $rc38lsb $rc39lsb $rc40lsb $rc41lsb $rc42lsb $rc43lsb $rc44lsb $rc45lsb $rc46lsb $rc47lsb $rc48lsb $rc49lsb $rc50lsb $rc51lsb $rc52lsb $rc53lsb $rc54lsb $rc55lsb $rc56lsb $rc57lsb $rc58lsb $rc59lsb $rc60lsb $rc61lsb $rc62lsb $rc63lsb $rc64lsb $rc65lsb $rc66lsb $rc67lsb $rc68lsb $rc69lsb $rc70lsb $rc71lsb $rc72lsb $rc73lsb $rc74lsb $rc75lsb $rc76lsb $rc77lsb $rc78lsb $rc79lsb $rc80lsb $rc81lsb $rc82lsb $rc83lsb $rc84lsb $rc85lsb $rc86lsb $rc87lsb $rc88lsb $rc89lsb $rc90lsb $rc91lsb $rc92lsb $rc93lsb $rc94lsb $rc95lsb $rc96lsb $rc97lsb $rc98lsb $rc99lsb $rc100lsb $rc101lsb $rc102lsb $rc103lsb $rc104lsb $rc105lsb $rc106lsb $rc107lsb $rc108lsb $rc109lsb $rc110lsb $rc111lsb $rc112lsb $rc113lsb $rc114lsb $rc115lsb $rc116lsb $rc117lsb $rc118lsb $rc119lsb $rc120lsb $rc121lsb $rc122lsb $rc123lsb $rc124lsb $rc125lsb $rc126lsb $rc127lsb $rc128lsb $rc129lsb $rc130lsb $rc131lsb $rc132lsb $rc133lsb $rc134lsb $rc135lsb $rc136lsb $rc137lsb $rc138lsb $rc139lsb $rc140lsb $rc141lsb $rc142lsb $rc143lsb $rc144lsb $rc145lsb $rc146lsb $rc147lsb $rc148lsb $rc149lsb $rc150lsb $rc151lsb $rc152lsb $rc153lsb $rc154lsb $rc155lsb $rc156lsb $rc157lsb $rc158lsb $rc159lsb $rc160lsb $rc161lsb $rc162lsb $rc163lsb $rc164lsb $rc165lsb $rc166lsb $rc167lsb $rc168lsb $rc169lsb $rc170lsb $rc171lsb $rc172lsb $rc173lsb $rc174lsb $rc175lsb $rc176lsb $rc177lsb $rc178lsb $rc179lsb $rc180lsb $rc181lsb $rc182lsb $rc183lsb $rc184lsb $rc185lsb $rc186lsb $rc187lsb $rc188lsb $rc189lsb $rc190lsb $rc191lsb $rc192lsb $rc193lsb $rc194lsb $rc195lsb $rc196lsb $rc197lsb $rc198lsb $rc199lsb $rc200lsb $rc201lsb $rc202lsb $rc203lsb $rc204lsb $rc205lsb $rc206lsb $rc207lsb $rc208lsb $rc209lsb $rc210lsb $rc211lsb $rc212lsb $rc213lsb $rc214lsb $rc215lsb $rc216lsb $rc217lsb $rc218lsb $rc219lsb $rc220lsb $rc221lsb $rc222lsb $rc223lsb $rc224lsb $rc225lsb $rc226lsb $rc227lsb $rc228lsb $rc229lsb $rc230lsb $rc231lsb $rc232lsb $rc233lsb $rc234lsb $rc235lsb $rc236lsb $rc237lsb $rc238lsb $rc239lsb $rc240lsb $rc241lsb $rc242lsb $rc243lsb $rc244lsb $rc245lsb $rc246lsb $rc247lsb $rc248lsb $rc249lsb $rc250lsb $rc251lsb $rc252lsb $rc253lsb ]
Excess PSets:
Disabled scoreboard hazard recognizer
Disabled scoreboard hazard recognizer
SU(0): $a = LDImm 2
# preds left : 0
# succs left : 1
# rdefs left : 0
Latency : 1
Depth : 0
Height : 1
Successors:
ExitSU: Ord Latency=1 Artificial
Pressure Diff : Ac -1 GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 Imag8 -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
SU(1): $x = COPY %2:yc
# preds left : 0
# succs left : 1
# rdefs left : 0
Latency : 0
Depth : 0
Height : 0
Successors:
ExitSU: Ord Latency=0 Artificial
Pressure Diff : Xc -1 XY -1 GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
ExitSU: JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $a, implicit killed $x, implicit-def $rs1
# preds left : 2
# succs left : 0
# rdefs left : 0
Latency : 0
Depth : 1
Height : 0
Predecessors:
SU(1): Ord Latency=0 Artificial
SU(0): Ord Latency=1 Artificial
Critical Path(GS-RR ): 1
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 1 0
Queue TopQ.P:
Queue TopQ.A: 0 1
Picking from Bot:
Cand SU(1) ORDER
Cand SU(0) PHYS-REG
Picking from Top:
Cand SU(0) ORDER
Cand SU(1) PHYS-REG
Pick Bot PHYS-REG
Scheduling SU(0) $a = LDImm 2
handleMove 96B -> 120B: $a = LDImm 2
ALSB: [0B,16r:0)[96r,128r:1) 0@0B-phi 1@96r
--> [0B,16r:0)[120r,128r:1) 0@0B-phi 1@120r
Bottom Pressure:
Xc=1
Yc=1
XY=2
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
GPR_LSB_with_Imag8=2
Anyi1=2
Anyi1_with_Pc=2
GPR_LSB: 3 <= 3(+ 1 livethru)
MOSAsmParamRegClass: 3 <= 4(+ 1 livethru)
CV_GPR_LSB: 3 <= 5(+ 1 livethru)
Ready @1c
*** Stall until: 1
BotQ.A BotLatency SU(0) 1c
Cycle: 1 BotQ.A
*** Max MOps 1 at cycle 1
Cycle: 2 BotQ.A
BotQ.A @2c
Retired: 1
Executed: 2c
Critical: 1c, 1 MOps
ExpectedLatency: 1c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 1
Pick Bot ONLY1
Scheduling SU(1) $x = COPY %2:yc
Bottom Pressure:
Yc=1
XY=1
GPR_LSB=1
MOSAsmParamRegClass=1
CV_GPR_LSB=1
CV_GPR_LSB_with_MOSAsmParamRegClass=1
CV_GPR_LSB_with_Pc=1
GPR_LSB_with_Imag8=1
Anyi1=1
Anyi1_with_Pc=1
XY: 2 <= 2(+ 1 livethru)
GPR_LSB: 3 <= 3(+ 1 livethru)
MOSAsmParamRegClass: 3 <= 4(+ 1 livethru)
CV_GPR_LSB: 3 <= 5(+ 1 livethru)
Ready @2c
BotQ.A @2c
Retired: 1
Executed: 2c
Critical: 1c, 1 MOps
ExpectedLatency: 1c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
*** Final schedule for %bb.0 ***
SU(1): $x = COPY %2:yc
SU(0): $a = LDImm 2
********** MI Scheduling **********
_Z11testIndCallc:%bb.0 entry
From: %1:gpr = COPY $a
To: ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
RegionInstrs: 2
ScheduleDAGMILive::schedule starting
GenericScheduler RegionPolicy: ShouldTrackPressure=1 OnlyTopDown=0 OnlyBottomUp=0
Max Pressure: Ac=1
Yc=1
XY=1
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
Imag8=1
GPR_LSB_with_Imag8=2
Anyi1=2
Anyi1_with_Pc=2
Live In: ALSB
Live Out: %2 %1
Live Thru:
LiveReg: %2
LiveReg: %1
Top Pressure:
Ac=1
GPR_LSB=1
MOSAsmParamRegClass=1
CV_GPR_LSB=1
CV_GPR_LSB_with_MOSAsmParamRegClass=1
CV_GPR_LSB_with_Pc=1
Imag8=1
GPR_LSB_with_Imag8=1
Anyi1=1
Anyi1_with_Pc=1
Bottom Pressure:
Yc=1
XY=1
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
GPR_LSB_with_Imag8=2
Anyi1=2
Anyi1_with_Pc=2
Excess PSets:
SU(0): %1:gpr = COPY $a
# preds left : 0
# succs left : 0
# rdefs left : 0
Latency : 0
Depth : 0
Height : 0
Pressure Diff : Ac 1 Imag8 1
Single Issue : false;
SU(1): %2:yc = LDImm 0
# preds left : 0
# succs left : 0
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Pressure Diff : Yc -1 XY -1 GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
ExitSU: ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
# preds left : 0
# succs left : 0
# rdefs left : 0
Latency : 0
Depth : 0
Height : 0
Critical Path(GS-RR ): 0
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 1 0
Queue TopQ.P:
Queue TopQ.A: 0 1
Picking from Bot:
Cand SU(1) ORDER
Picking from Top:
Cand SU(0) ORDER
Cand SU(0) PHYS-REG
Pick Top PHYS-REG
Scheduling SU(0) %1:gpr = COPY $a
Top Pressure:
GPR_LSB=1
MOSAsmParamRegClass=1
CV_GPR_LSB=1
CV_GPR_LSB_with_MOSAsmParamRegClass=1
CV_GPR_LSB_with_Pc=1
GPR_LSB_with_Imag8=1
Anyi1=1
Anyi1_with_Pc=1
Ready @0c
TopQ.A @0c
Retired: 0
Executed: 0c
Critical: 0c, 0 MOps
ExpectedLatency: 0c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 1
Pick Bot ONLY1
Scheduling SU(1) %2:yc = LDImm 0
Bottom Pressure:
GPR_LSB=1
MOSAsmParamRegClass=1
CV_GPR_LSB=1
CV_GPR_LSB_with_MOSAsmParamRegClass=1
CV_GPR_LSB_with_Pc=1
GPR_LSB_with_Imag8=1
Anyi1=1
Anyi1_with_Pc=1
XY: 1 <= 2(+ 0 livethru)
GPR_LSB: 2 <= 3(+ 0 livethru)
MOSAsmParamRegClass: 2 <= 4(+ 0 livethru)
Ready @0c
*** Max MOps 1 at cycle 0
Cycle: 1 BotQ.A
BotQ.A @1c
Retired: 1
Executed: 1c
Critical: 1c, 1 MOps
ExpectedLatency: 0c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
*** Final schedule for %bb.0 ***
SU(0): %1:gpr = COPY $a
SU(1): %2:yc = LDImm 0
********** MI Scheduling **********
_Z11testIndCallc:%bb.1
From: %101:ac = LDImm target-flags(lo) @_ZTV4SubB + 4
To: JMP %bb.3
RegionInstrs: 2
ScheduleDAGMILive::schedule starting
GenericScheduler RegionPolicy: ShouldTrackPressure=1 OnlyTopDown=0 OnlyBottomUp=0
Max Pressure: Ac=2
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
Imag8=2
GPR_LSB_with_Imag8=2
Anyi1=2
Anyi1_with_Pc=2
Live In:
Live Out: %102 %101
Live Thru:
LiveReg: %102
LiveReg: %101
Top Pressure:
Bottom Pressure:
Ac=2
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
Imag8=2
GPR_LSB_with_Imag8=2
Anyi1=2
Anyi1_with_Pc=2
Ac Limit 1 Actual 2
Excess PSets: Ac
SU(0): %101:ac = LDImm target-flags(lo) @_ZTV4SubB + 4
# preds left : 0
# succs left : 0
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Pressure Diff : Ac -1 GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 Imag8 -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
SU(1): %102:ac = LDImm target-flags(hi) @_ZTV4SubB + 4
# preds left : 0
# succs left : 0
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Pressure Diff : Ac -1 GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 Imag8 -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
ExitSU: JMP %bb.3
# preds left : 0
# succs left : 0
# rdefs left : 0
Latency : 0
Depth : 0
Height : 0
Critical Path(GS-RR ): 0
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 1 0
Queue TopQ.P:
Queue TopQ.A: 0 1
Picking from Bot:
Try SU(1) Ac:-1
Cand SU(1) ORDER
Try SU(0) Ac:-1
Picking from Top:
Cand SU(0) ORDER
Pick Bot REG-EXCESS
Scheduling SU(1) %102:ac = LDImm target-flags(hi) @_ZTV4SubB + 4
Bottom Pressure:
Ac=1
GPR_LSB=1
MOSAsmParamRegClass=1
CV_GPR_LSB=1
CV_GPR_LSB_with_MOSAsmParamRegClass=1
CV_GPR_LSB_with_Pc=1
Imag8=1
GPR_LSB_with_Imag8=1
Anyi1=1
Anyi1_with_Pc=1
GPR_LSB: 2 <= 3(+ 0 livethru)
MOSAsmParamRegClass: 2 <= 4(+ 0 livethru)
Ready @0c
*** Max MOps 1 at cycle 0
Cycle: 1 BotQ.A
BotQ.A @1c
Retired: 1
Executed: 1c
Critical: 1c, 1 MOps
ExpectedLatency: 0c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 0
Pick Bot ONLY1
Scheduling SU(0) %101:ac = LDImm target-flags(lo) @_ZTV4SubB + 4
Bottom Pressure:
GPR_LSB: 2 <= 3(+ 0 livethru)
MOSAsmParamRegClass: 2 <= 4(+ 0 livethru)
Ready @1c
*** Max MOps 1 at cycle 1
Cycle: 2 BotQ.A
BotQ.A @2c
Retired: 2
Executed: 2c
Critical: 2c, 2 MOps
ExpectedLatency: 0c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
*** Final schedule for %bb.1 ***
SU(0): %101:ac = LDImm target-flags(lo) @_ZTV4SubB + 4
SU(1): %102:ac = LDImm target-flags(hi) @_ZTV4SubB + 4
********** MI Scheduling **********
_Z11testIndCallc:%bb.2 select.false
From: %101:ac = LDImm target-flags(lo) @_ZTV4SubA + 4
To: End RegionInstrs: 2
ScheduleDAGMILive::schedule starting
GenericScheduler RegionPolicy: ShouldTrackPressure=1 OnlyTopDown=0 OnlyBottomUp=0
Max Pressure: Ac=2
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
Imag8=2
GPR_LSB_with_Imag8=2
Anyi1=2
Anyi1_with_Pc=2
Live In:
Live Out: %102 %101
Live Thru:
LiveReg: %102
LiveReg: %101
Top Pressure:
Bottom Pressure:
Ac=2
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
Imag8=2
GPR_LSB_with_Imag8=2
Anyi1=2
Anyi1_with_Pc=2
Ac Limit 1 Actual 2
Excess PSets: Ac
SU(0): %101:ac = LDImm target-flags(lo) @_ZTV4SubA + 4
# preds left : 0
# succs left : 0
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Pressure Diff : Ac -1 GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 Imag8 -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
SU(1): %102:ac = LDImm target-flags(hi) @_ZTV4SubA + 4
# preds left : 0
# succs left : 0
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Pressure Diff : Ac -1 GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 Imag8 -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
Critical Path(GS-RR ): 0
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 1 0
Queue TopQ.P:
Queue TopQ.A: 0 1
Picking from Bot:
Try SU(1) Ac:-1
Cand SU(1) ORDER
Try SU(0) Ac:-1
Picking from Top:
Cand SU(0) ORDER
Pick Bot REG-EXCESS
Scheduling SU(1) %102:ac = LDImm target-flags(hi) @_ZTV4SubA + 4
Bottom Pressure:
Ac=1
GPR_LSB=1
MOSAsmParamRegClass=1
CV_GPR_LSB=1
CV_GPR_LSB_with_MOSAsmParamRegClass=1
CV_GPR_LSB_with_Pc=1
Imag8=1
GPR_LSB_with_Imag8=1
Anyi1=1
Anyi1_with_Pc=1
GPR_LSB: 2 <= 3(+ 0 livethru)
MOSAsmParamRegClass: 2 <= 4(+ 0 livethru)
Ready @0c
*** Max MOps 1 at cycle 0
Cycle: 1 BotQ.A
BotQ.A @1c
Retired: 1
Executed: 1c
Critical: 1c, 1 MOps
ExpectedLatency: 0c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 0
Pick Bot ONLY1
Scheduling SU(0) %101:ac = LDImm target-flags(lo) @_ZTV4SubA + 4
Bottom Pressure:
GPR_LSB: 2 <= 3(+ 0 livethru)
MOSAsmParamRegClass: 2 <= 4(+ 0 livethru)
Ready @1c
*** Max MOps 1 at cycle 1
Cycle: 2 BotQ.A
BotQ.A @2c
Retired: 2
Executed: 2c
Critical: 2c, 2 MOps
ExpectedLatency: 0c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
*** Final schedule for %bb.2 ***
SU(0): %101:ac = LDImm target-flags(lo) @_ZTV4SubA + 4
SU(1): %102:ac = LDImm target-flags(hi) @_ZTV4SubA + 4
********** MI Scheduling **********
_Z11testIndCallc:%bb.3 select.end
From: STYIndir %101:ac, %4:imag16, %2:yc :: (store 1 into %ir.0, !tbaa !2)
To: dead %92:cc = CMPImmTerm %1:gpr, 0, implicit-def dead $nz, implicit-def $z
RegionInstrs: 3
ScheduleDAGMILive::schedule starting
GenericScheduler RegionPolicy: ShouldTrackPressure=1 OnlyTopDown=0 OnlyBottomUp=0
Max Pressure: Cc=1
Ac=2
Yc=1
XY=1
GPR_LSB=4
Pc=1
MOSAsmParamRegClass=4
CV_GPR_LSB=4
CV_GPR_LSB_with_MOSAsmParamRegClass=4
CV_GPR_LSB_with_Pc=4
Imag8=4
GPR_LSB_with_Imag8=6
Anyi1=6
Anyi1_with_Pc=6
Live In: %1 %102 %4 %101 %2
Live Out: %4 %53
Live Thru: Imag8=2
GPR_LSB_with_Imag8=2
Anyi1=2
Anyi1_with_Pc=2
LiveReg: %4
UpdateRegP: SU(0) STYIndir %101:ac, %4:imag16, %2:yc :: (store 1 into %ir.0, !tbaa !2)
to Ac 1 Yc 1 XY 1 GPR_LSB 2 MOSAsmParamRegClass 2 CV_GPR_LSB 2 CV_GPR_LSB_with_MOSAsmParamRegClass 2 CV_GPR_LSB_with_Pc 2 Imag8 1 GPR_LSB_with_Imag8 2 Anyi1 2 Anyi1_with_Pc 2
UpdateRegP: SU(2) STYIndir %102:ac, %4:imag16, %53:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
to Ac 1 Yc 1 XY 1 GPR_LSB 2 MOSAsmParamRegClass 2 CV_GPR_LSB 2 CV_GPR_LSB_with_MOSAsmParamRegClass 2 CV_GPR_LSB_with_Pc 2 Imag8 1 GPR_LSB_with_Imag8 2 Anyi1 2 Anyi1_with_Pc 2
LiveReg: %53
UpdateRegP: SU(2) STYIndir %102:ac, %4:imag16, %53:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
to Ac 1 GPR_LSB 1 MOSAsmParamRegClass 1 CV_GPR_LSB 1 CV_GPR_LSB_with_MOSAsmParamRegClass 1 CV_GPR_LSB_with_Pc 1 Imag8 1 GPR_LSB_with_Imag8 1 Anyi1 1 Anyi1_with_Pc 1
LiveReg: %1
Top Pressure:
Ac=2
Yc=1
XY=1
GPR_LSB=4
MOSAsmParamRegClass=4
CV_GPR_LSB=4
CV_GPR_LSB_with_MOSAsmParamRegClass=4
CV_GPR_LSB_with_Pc=4
Imag8=4
GPR_LSB_with_Imag8=6
Anyi1=6
Anyi1_with_Pc=6
Bottom Pressure:
Yc=1
XY=1
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
Imag8=2
GPR_LSB_with_Imag8=4
Anyi1=4
Anyi1_with_Pc=4
Ac Limit 1 Actual 2
GPR_LSB Limit 3 Actual 4
Excess PSets: Ac GPR_LSB
SU(0): STYIndir %101:ac, %4:imag16, %2:yc :: (store 1 into %ir.0, !tbaa !2)
# preds left : 0
# succs left : 0
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Pressure Diff : Ac 1 Yc 1 XY 1 GPR_LSB 2 MOSAsmParamRegClass 2 CV_GPR_LSB 2 CV_GPR_LSB_with_MOSAsmParamRegClass 2 CV_GPR_LSB_with_Pc 2 Imag8 1 GPR_LSB_with_Imag8 2 Anyi1 2 Anyi1_with_Pc 2
Single Issue : false;
SU(1): %53:yc = LDImm 1
# preds left : 0
# succs left : 1
# rdefs left : 0
Latency : 1
Depth : 0
Height : 1
Successors:
SU(2): Data Latency=1 Reg=%53
Pressure Diff : Yc -1 XY -1 GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
SU(2): STYIndir %102:ac, %4:imag16, %53:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
# preds left : 1
# succs left : 0
# rdefs left : 0
Latency : 1
Depth : 1
Height : 0
Predecessors:
SU(1): Data Latency=1 Reg=%53
Pressure Diff : Ac 1 GPR_LSB 1 MOSAsmParamRegClass 1 CV_GPR_LSB 1 CV_GPR_LSB_with_MOSAsmParamRegClass 1 CV_GPR_LSB_with_Pc 1 Imag8 1 GPR_LSB_with_Imag8 1 Anyi1 1 Anyi1_with_Pc 1
Single Issue : false;
ExitSU: dead %92:cc = CMPImmTerm %1:gpr, 0, implicit-def dead $nz, implicit-def $z
# preds left : 0
# succs left : 0
# rdefs left : 0
Latency : 0
Depth : 0
Height : 0
Critical Path(GS-RR ): 1
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 2 0
Queue TopQ.P:
Queue TopQ.A: 0 1
Picking from Bot:
Cand SU(2) ORDER
Try SU(0) Yc:1
Picking from Top:
Try SU(0) Ac:-1
Cand SU(0) ORDER
Try SU(1) Yc:1
Cand SU(0) REG-EXCESS Ac:-1
Pick Top REG-EXCESS
Scheduling SU(0) STYIndir %101:ac, %4:imag16, %2:yc :: (store 1 into %ir.0, !tbaa !2)
Top Pressure:
Ac=1
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
Imag8=3
GPR_LSB_with_Imag8=4
Anyi1=4
Anyi1_with_Pc=4
XY: 1 <= 2(+ 0 livethru)
GPR_LSB: 4 > 3(+ 0 livethru)
MOSAsmParamRegClass: 4 <= 4(+ 0 livethru)
CV_GPR_LSB: 4 <= 5(+ 0 livethru)
CV_GPR_LSB_with_MOSAsmParamRegClass: 4 <= 6(+ 0 livethru)
Ready @0c
*** Max MOps 1 at cycle 0
Cycle: 1 TopQ.A
TopQ.A @1c
Retired: 1
Executed: 1c
Critical: 1c, 1 MOps
ExpectedLatency: 0c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 2
Pick Bot ONLY1
Scheduling SU(2) STYIndir %102:ac, %4:imag16, %53:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
Bottom Pressure:
Ac=1
Yc=1
XY=1
GPR_LSB=3
MOSAsmParamRegClass=3
CV_GPR_LSB=3
CV_GPR_LSB_with_MOSAsmParamRegClass=3
CV_GPR_LSB_with_Pc=3
Imag8=3
GPR_LSB_with_Imag8=5
Anyi1=5
Anyi1_with_Pc=5
GPR_LSB: 3 <= 3(+ 0 livethru)
MOSAsmParamRegClass: 3 <= 4(+ 0 livethru)
CV_GPR_LSB: 3 <= 5(+ 0 livethru)
LiveReg: %102
UpdateRegP: SU(2) STYIndir %102:ac, %4:imag16, %53:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
to
Ready @0c
BotQ.A TopLatency SU(2) 1c
*** Max MOps 1 at cycle 0
Cycle: 1 BotQ.A
BotQ.A @1c
Retired: 1
Executed: 1c
Critical: 1c, 1 MOps
ExpectedLatency: 0c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 1
Pick Bot ONLY1
Scheduling SU(1) %53:yc = LDImm 1
Bottom Pressure:
Ac=1
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
Imag8=3
GPR_LSB_with_Imag8=4
Anyi1=4
Anyi1_with_Pc=4
XY: 1 <= 2(+ 0 livethru)
GPR_LSB: 3 <= 3(+ 0 livethru)
MOSAsmParamRegClass: 3 <= 4(+ 0 livethru)
CV_GPR_LSB: 3 <= 5(+ 0 livethru)
Ready @1c
BotQ.A BotLatency SU(1) 1c
*** Max MOps 1 at cycle 1
Cycle: 2 BotQ.A
BotQ.A @2c
Retired: 2
Executed: 2c
Critical: 2c, 2 MOps
ExpectedLatency: 1c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
*** Final schedule for %bb.3 ***
SU(0): STYIndir %101:ac, %4:imag16, %2:yc :: (store 1 into %ir.0, !tbaa !2)
SU(1): %53:yc = LDImm 1
SU(2): STYIndir %102:ac, %4:imag16, %53:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
********** MI Scheduling **********
_Z11testIndCallc:%bb.4
From: %103:gpr = LDImm target-flags(lo) @_ZN4SubB2fnEv
To: JMP %bb.6
RegionInstrs: 2
ScheduleDAGMILive::schedule starting
GenericScheduler RegionPolicy: ShouldTrackPressure=1 OnlyTopDown=0 OnlyBottomUp=0
Max Pressure: GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
GPR_LSB_with_Imag8=2
Anyi1=2
Anyi1_with_Pc=2
Live In:
Live Out: %104 %103
Live Thru:
LiveReg: %104
LiveReg: %103
Top Pressure:
Bottom Pressure:
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
GPR_LSB_with_Imag8=2
Anyi1=2
Anyi1_with_Pc=2
Excess PSets:
SU(0): %103:gpr = LDImm target-flags(lo) @_ZN4SubB2fnEv
# preds left : 0
# succs left : 0
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Pressure Diff : GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
SU(1): %104:gpr = LDImm target-flags(hi) @_ZN4SubB2fnEv
# preds left : 0
# succs left : 0
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Pressure Diff : GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
ExitSU: JMP %bb.6
# preds left : 0
# succs left : 0
# rdefs left : 0
Latency : 0
Depth : 0
Height : 0
Critical Path(GS-RR ): 0
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 1 0
Queue TopQ.P:
Queue TopQ.A: 0 1
Picking from Bot:
Cand SU(1) ORDER
Picking from Top:
Cand SU(0) ORDER
Pick Bot ORDER
Scheduling SU(1) %104:gpr = LDImm target-flags(hi) @_ZN4SubB2fnEv
Bottom Pressure:
GPR_LSB=1
MOSAsmParamRegClass=1
CV_GPR_LSB=1
CV_GPR_LSB_with_MOSAsmParamRegClass=1
CV_GPR_LSB_with_Pc=1
GPR_LSB_with_Imag8=1
Anyi1=1
Anyi1_with_Pc=1
GPR_LSB: 2 <= 3(+ 0 livethru)
MOSAsmParamRegClass: 2 <= 4(+ 0 livethru)
Ready @0c
*** Max MOps 1 at cycle 0
Cycle: 1 BotQ.A
BotQ.A @1c
Retired: 1
Executed: 1c
Critical: 1c, 1 MOps
ExpectedLatency: 0c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 0
Pick Bot ONLY1
Scheduling SU(0) %103:gpr = LDImm target-flags(lo) @_ZN4SubB2fnEv
Bottom Pressure:
GPR_LSB: 2 <= 3(+ 0 livethru)
MOSAsmParamRegClass: 2 <= 4(+ 0 livethru)
Ready @1c
*** Max MOps 1 at cycle 1
Cycle: 2 BotQ.A
BotQ.A @2c
Retired: 2
Executed: 2c
Critical: 2c, 2 MOps
ExpectedLatency: 0c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
*** Final schedule for %bb.4 ***
SU(0): %103:gpr = LDImm target-flags(lo) @_ZN4SubB2fnEv
SU(1): %104:gpr = LDImm target-flags(hi) @_ZN4SubB2fnEv
********** MI Scheduling **********
_Z11testIndCallc:%bb.5 select.false9
From: %103:gpr = LDImm target-flags(lo) @_ZN4SubA2fnEv
To: End RegionInstrs: 2
ScheduleDAGMILive::schedule starting
GenericScheduler RegionPolicy: ShouldTrackPressure=1 OnlyTopDown=0 OnlyBottomUp=0
Max Pressure: GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
GPR_LSB_with_Imag8=2
Anyi1=2
Anyi1_with_Pc=2
Live In:
Live Out: %104 %103
Live Thru:
LiveReg: %104
LiveReg: %103
Top Pressure:
Bottom Pressure:
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
GPR_LSB_with_Imag8=2
Anyi1=2
Anyi1_with_Pc=2
Excess PSets:
SU(0): %103:gpr = LDImm target-flags(lo) @_ZN4SubA2fnEv
# preds left : 0
# succs left : 0
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Pressure Diff : GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
SU(1): %104:gpr = LDImm target-flags(hi) @_ZN4SubA2fnEv
# preds left : 0
# succs left : 0
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Pressure Diff : GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
Critical Path(GS-RR ): 0
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 1 0
Queue TopQ.P:
Queue TopQ.A: 0 1
Picking from Bot:
Cand SU(1) ORDER
Picking from Top:
Cand SU(0) ORDER
Pick Bot ORDER
Scheduling SU(1) %104:gpr = LDImm target-flags(hi) @_ZN4SubA2fnEv
Bottom Pressure:
GPR_LSB=1
MOSAsmParamRegClass=1
CV_GPR_LSB=1
CV_GPR_LSB_with_MOSAsmParamRegClass=1
CV_GPR_LSB_with_Pc=1
GPR_LSB_with_Imag8=1
Anyi1=1
Anyi1_with_Pc=1
GPR_LSB: 2 <= 3(+ 0 livethru)
MOSAsmParamRegClass: 2 <= 4(+ 0 livethru)
Ready @0c
*** Max MOps 1 at cycle 0
Cycle: 1 BotQ.A
BotQ.A @1c
Retired: 1
Executed: 1c
Critical: 1c, 1 MOps
ExpectedLatency: 0c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 0
Pick Bot ONLY1
Scheduling SU(0) %103:gpr = LDImm target-flags(lo) @_ZN4SubA2fnEv
Bottom Pressure:
GPR_LSB: 2 <= 3(+ 0 livethru)
MOSAsmParamRegClass: 2 <= 4(+ 0 livethru)
Ready @1c
*** Max MOps 1 at cycle 1
Cycle: 2 BotQ.A
BotQ.A @2c
Retired: 2
Executed: 2c
Critical: 2c, 2 MOps
ExpectedLatency: 0c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
*** Final schedule for %bb.5 ***
SU(0): %103:gpr = LDImm target-flags(lo) @_ZN4SubA2fnEv
SU(1): %104:gpr = LDImm target-flags(hi) @_ZN4SubA2fnEv
********** MI Scheduling **********
_Z11testIndCallc:%bb.6 select.end8
From: %89:yc = LDImm 0
To: ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
RegionInstrs: 16
ScheduleDAGMILive::schedule starting
GenericScheduler RegionPolicy: ShouldTrackPressure=1 OnlyTopDown=0 OnlyBottomUp=0
Max Pressure: Cc=1
Vc=1
Ac=2
Yc=2
XY=2
GPR_LSB=4
Pc=2
MOSAsmParamRegClass=4
CV_GPR_LSB=6
CV_GPR_LSB_with_MOSAsmParamRegClass=6
CV_GPR_LSB_with_Pc=6
Imag8=7
GPR_LSB_with_Imag8=9
Anyi1=10
Anyi1_with_Pc=10
Live In: %53 %4
Live Out: RC16LSB RC17LSB %4
Live Thru: Imag8=2
GPR_LSB_with_Imag8=2
Anyi1=2
Anyi1_with_Pc=2
LiveReg: %4
UpdateRegP: SU(1) %82:ac = LDYIndir %4:imag16, %89:yc :: (load 1 from %ir.3, !tbaa !2)
to Ac -1 Yc 1 XY 1 Imag8 -1
UpdateRegP: SU(2) %85:ac = LDYIndir %4:imag16, %53:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
to Ac -1 Yc 1 XY 1 Imag8 -1
Top Pressure:
Yc=1
XY=1
GPR_LSB=1
MOSAsmParamRegClass=1
CV_GPR_LSB=1
CV_GPR_LSB_with_MOSAsmParamRegClass=1
CV_GPR_LSB_with_Pc=1
Imag8=2
GPR_LSB_with_Imag8=3
Anyi1=3
Anyi1_with_Pc=3
Bottom Pressure:
Imag8=4
GPR_LSB_with_Imag8=4
Anyi1=4
Anyi1_with_Pc=4
Ac Limit 1 Actual 2
Yc Limit 1 Actual 2
GPR_LSB Limit 3 Actual 4
CV_GPR_LSB Limit 5 Actual 6
Excess PSets: Ac Yc GPR_LSB CV_GPR_LSB
SU(0): %89:yc = LDImm 0
# preds left : 0
# succs left : 1
# rdefs left : 0
Latency : 1
Depth : 0
Height : 11
Successors:
SU(1): Data Latency=1 Reg=%89
Pressure Diff : Yc -1 XY -1 GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
SU(1): %82:ac = LDYIndir %4:imag16, %89:yc :: (load 1 from %ir.3, !tbaa !2)
# preds left : 1
# succs left : 3
# rdefs left : 0
Latency : 4
Depth : 1
Height : 10
Predecessors:
SU(0): Data Latency=1 Reg=%89
Successors:
SU(7): Data Latency=4 Reg=%82
SU(3): Data Latency=4 Reg=%82
SU(7): Out Latency=1
Pressure Diff : Ac -1 Yc 1 XY 1 Imag8 -1
Single Issue : false;
SU(2): %85:ac = LDYIndir %4:imag16, %53:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
# preds left : 0
# succs left : 3
# rdefs left : 0
Latency : 4
Depth : 0
Height : 9
Successors:
SU(8): Data Latency=4 Reg=%85
SU(4): Data Latency=4 Reg=%85
SU(8): Out Latency=1
Pressure Diff : Ac -1 Yc 1 XY 1 Imag8 -1
Single Issue : false;
SU(3): undef %34.sublo:imag16 = COPY %82:ac
# preds left : 1
# succs left : 2
# rdefs left : 0
Latency : 0
Depth : 5
Height : 6
Predecessors:
SU(1): Data Latency=4 Reg=%82
Successors:
SU(4): Out Latency=1
SU(7): Anti Latency=0
Pressure Diff : Ac 1 GPR_LSB 1 MOSAsmParamRegClass 1 CV_GPR_LSB 1 CV_GPR_LSB_with_MOSAsmParamRegClass 1 CV_GPR_LSB_with_Pc 1 Imag8 -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
SU(4): %34.subhi:imag16 = COPY %85:ac
# preds left : 2
# succs left : 2
# rdefs left : 0
Latency : 0
Depth : 6
Height : 5
Predecessors:
SU(3): Out Latency=1
SU(2): Data Latency=4 Reg=%85
Successors:
SU(11): Data Latency=0 Reg=%34
SU(8): Anti Latency=0
Pressure Diff : Ac 1 GPR_LSB 1 MOSAsmParamRegClass 1 CV_GPR_LSB 1 CV_GPR_LSB_with_MOSAsmParamRegClass 1 CV_GPR_LSB_with_Pc 1 Imag8 1 GPR_LSB_with_Imag8 1 Anyi1 1 Anyi1_with_Pc 1
Single Issue : false;
SU(5): %33:yc = LDImm 2
# preds left : 0
# succs left : 1
# rdefs left : 0
Latency : 1
Depth : 0
Height : 6
Successors:
SU(11): Data Latency=1 Reg=%33
Pressure Diff : Yc -1 XY -1 GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
SU(6): %86:cc = LDImm1 0
# preds left : 0
# succs left : 2
# rdefs left : 0
Latency : 1
Depth : 0
Height : 7
Successors:
SU(7): Data Latency=1 Reg=%86
SU(7): Out Latency=1
Pressure Diff : Cc -1 Pc -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
SU(7): %82:ac, %86:cc, dead %88:vc = ADCImm %82:ac(tied-def 0), 2, %86:cc(tied-def 1)
# preds left : 5
# succs left : 3
# rdefs left : 0
Latency : 1
Depth : 5
Height : 6
Predecessors:
SU(1): Data Latency=4 Reg=%82
SU(6): Out Latency=1
SU(3): Anti Latency=0
SU(6): Data Latency=1 Reg=%86
SU(1): Out Latency=1
Successors:
SU(9): Data Latency=1 Reg=%82
SU(8): Data Latency=1 Reg=%86
SU(8): Out Latency=1
Pressure Diff :
Single Issue : false;
SU(8): %85:ac, dead %86:cc, dead %87:vc = ADCImm %85:ac(tied-def 0), 0, %86:cc(tied-def 1)
# preds left : 5
# succs left : 1
# rdefs left : 0
Latency : 1
Depth : 6
Height : 5
Predecessors:
SU(7): Data Latency=1 Reg=%86
SU(7): Out Latency=1
SU(4): Anti Latency=0
SU(2): Data Latency=4 Reg=%85
SU(2): Out Latency=1
Successors:
SU(10): Data Latency=1 Reg=%85
Pressure Diff : Cc 1 Pc 1 CV_GPR_LSB 1 CV_GPR_LSB_with_MOSAsmParamRegClass 1 CV_GPR_LSB_with_Pc 1 Anyi1 1 Anyi1_with_Pc 1
Single Issue : false;
SU(9): undef %14.sublo:imag16 = COPY %82:ac
# preds left : 1
# succs left : 1
# rdefs left : 0
Latency : 0
Depth : 6
Height : 5
Predecessors:
SU(7): Data Latency=1 Reg=%82
Successors:
SU(10): Out Latency=1
Pressure Diff : Ac 1 GPR_LSB 1 MOSAsmParamRegClass 1 CV_GPR_LSB 1 CV_GPR_LSB_with_MOSAsmParamRegClass 1 CV_GPR_LSB_with_Pc 1 Imag8 -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
SU(10): %14.subhi:imag16 = COPY %85:ac
# preds left : 2
# succs left : 1
# rdefs left : 0
Latency : 0
Depth : 7
Height : 4
Predecessors:
SU(9): Out Latency=1
SU(8): Data Latency=1 Reg=%85
Successors:
SU(12): Data Latency=0 Reg=%14
Pressure Diff : Ac 1 GPR_LSB 1 MOSAsmParamRegClass 1 CV_GPR_LSB 1 CV_GPR_LSB_with_MOSAsmParamRegClass 1 CV_GPR_LSB_with_Pc 1 Imag8 1 GPR_LSB_with_Imag8 1 Anyi1 1 Anyi1_with_Pc 1
Single Issue : false;
SU(11): %28:ac = LDYIndir %34:imag16, %33:yc :: (load 1 from %ir.vfn3)
# preds left : 2
# succs left : 1
# rdefs left : 0
Latency : 4
Depth : 6
Height : 5
Predecessors:
SU(4): Data Latency=0 Reg=%34
SU(5): Data Latency=1 Reg=%33
Successors:
SU(13): Data Latency=4 Reg=%28
Pressure Diff : Ac -1 Yc 1 XY 1 Imag8 1 GPR_LSB_with_Imag8 2 Anyi1 2 Anyi1_with_Pc 2
Single Issue : false;
SU(12): %31:ac = LDYIndir %14:imag16, %53:yc :: (load 1 from %ir.vfn3 + 1)
# preds left : 1
# succs left : 1
# rdefs left : 0
Latency : 4
Depth : 7
Height : 4
Predecessors:
SU(10): Data Latency=0 Reg=%14
Successors:
SU(14): Data Latency=4 Reg=%31
Pressure Diff : Ac -1 Yc 1 XY 1 Imag8 1 GPR_LSB_with_Imag8 2 Anyi1 2 Anyi1_with_Pc 2
Single Issue : false;
SU(13): undef %27.sublo:imag16 = COPY %28:ac
# preds left : 1
# succs left : 1
# rdefs left : 0
Latency : 0
Depth : 10
Height : 1
Predecessors:
SU(11): Data Latency=4 Reg=%28
Successors:
SU(14): Out Latency=1
Pressure Diff : Ac 1 GPR_LSB 1 MOSAsmParamRegClass 1 CV_GPR_LSB 1 CV_GPR_LSB_with_MOSAsmParamRegClass 1 CV_GPR_LSB_with_Pc 1 Imag8 -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
SU(14): %27.subhi:imag16 = COPY %31:ac
# preds left : 2
# succs left : 1
# rdefs left : 0
Latency : 0
Depth : 11
Height : 0
Predecessors:
SU(13): Out Latency=1
SU(12): Data Latency=4 Reg=%31
Successors:
SU(15): Data Latency=0 Reg=%27
Pressure Diff : Ac 1 GPR_LSB 1 MOSAsmParamRegClass 1 CV_GPR_LSB 1 CV_GPR_LSB_with_MOSAsmParamRegClass 1 CV_GPR_LSB_with_Pc 1 Imag8 1 GPR_LSB_with_Imag8 1 Anyi1 1 Anyi1_with_Pc 1
Single Issue : false;
SU(15): $rs8 = COPY %27:imag16
# preds left : 1
# succs left : 0
# rdefs left : 0
Latency : 0
Depth : 11
Height : 0
Predecessors:
SU(14): Data Latency=0 Reg=%27
Pressure Diff :
Single Issue : false;
ExitSU: ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
# preds left : 0
# succs left : 0
# rdefs left : 0
Latency : 0
Depth : 0
Height : 0
Critical Path(GS-RR ): 11
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 15
Pick Bot ONLY1
Scheduling SU(15) $rs8 = COPY %27:imag16
Bottom Pressure:
Imag8=4
GPR_LSB_with_Imag8=4
Anyi1=4
Anyi1_with_Pc=4
LiveReg: %27
UpdateRegP: SU(15) $rs8 = COPY %27:imag16
to Imag8 -2 GPR_LSB_with_Imag8 -2 Anyi1 -2 Anyi1_with_Pc -2
Ready @0c
BotQ.A TopLatency SU(15) 11c
BotQ.A @0c
Retired: 0
Executed: 0c
Critical: 0c, 0 MOps
ExpectedLatency: 0c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 14
Pick Bot ONLY1
Scheduling SU(14) %27.subhi:imag16 = COPY %31:ac
Bottom Pressure:
Ac=1
GPR_LSB=1
MOSAsmParamRegClass=1
CV_GPR_LSB=1
CV_GPR_LSB_with_MOSAsmParamRegClass=1
CV_GPR_LSB_with_Pc=1
Imag8=5
GPR_LSB_with_Imag8=5
Anyi1=5
Anyi1_with_Pc=5
GPR_LSB: 1 <= 3(+ 0 livethru)
LiveReg: %27
UpdateRegP: SU(14) %27.subhi:imag16 = COPY %31:ac
to Ac 1 GPR_LSB 1 MOSAsmParamRegClass 1 CV_GPR_LSB 1 CV_GPR_LSB_with_MOSAsmParamRegClass 1 CV_GPR_LSB_with_Pc 1 Imag8 -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
LiveReg: %31
UpdateRegP: SU(14) %27.subhi:imag16 = COPY %31:ac
to Imag8 -2 GPR_LSB_with_Imag8 -2 Anyi1 -2 Anyi1_with_Pc -2
Ready @0c
BotQ.A @0c
Retired: 0
Executed: 0c
Critical: 0c, 0 MOps
ExpectedLatency: 0c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 13 12
Queue TopQ.P:
Queue TopQ.A: 0 2 5 6
Picking from Bot:
Try SU(13) Ac:1
Cand SU(13) ORDER
Cand SU(12) REG-EXCESS
Picking from Top:
Try SU(0) Yc:1
Cand SU(0) ORDER
Cand SU(2) REG-EXCESS
Try SU(5) Yc:1
Cand SU(6) REG-CRIT CV_GPR_LSB:1
Pick Bot REG-EXCESS
Scheduling SU(12) %31:ac = LDYIndir %14:imag16, %53:yc :: (load 1 from %ir.vfn3 + 1)
handleMove 1248B -> 1272B: %31:ac = LDYIndir %14:imag16, %53:yc :: (load 1 from %ir.vfn3 + 1)
%31: [1248r,1280r:0) 0@1248r
--> [1272r,1280r:0) 0@1272r
%14 L0000000000000002: [1200r,1248r:0) 0@1200r
--> [1200r,1272r:0) 0@1200r
%14 L0000000000000020: [1216r,1248r:0) 0@1216r
--> [1216r,1272r:0) 0@1216r
%14: [1200r,1216r:0)[1216r,1248r:1) 0@1200r 1@1216r
--> [1200r,1216r:0)[1216r,1272r:1) 0@1200r 1@1216r
%53: [528r,1248r:0) 0@528r
--> [528r,1272r:0) 0@528r
Bottom Pressure:
Yc=1
XY=1
GPR_LSB=1
MOSAsmParamRegClass=1
CV_GPR_LSB=1
CV_GPR_LSB_with_MOSAsmParamRegClass=1
CV_GPR_LSB_with_Pc=1
Imag8=6
GPR_LSB_with_Imag8=7
Anyi1=7
Anyi1_with_Pc=7
XY: 1 <= 2(+ 0 livethru)
LiveReg: %14
UpdateRegP: SU(12) %31:ac = LDYIndir %14:imag16, %53:yc :: (load 1 from %ir.vfn3 + 1)
to Ac -1 Yc 1 XY 1 Imag8 -1
LiveReg: %53
UpdateRegP: SU(2) %85:ac = LDYIndir %4:imag16, %53:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
to Ac -1 GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 Imag8 -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
UpdateRegP: SU(12) %31:ac = LDYIndir %14:imag16, %53:yc :: (load 1 from %ir.vfn3 + 1)
to Ac -1 GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 Imag8 -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Ready @4c
*** Stall until: 4
BotQ.A BotLatency SU(12) 4c
Cycle: 4 BotQ.A
*** Max MOps 1 at cycle 4
Cycle: 5 BotQ.A
BotQ.A @5c
Retired: 1
Executed: 5c
Critical: 1c, 1 MOps
ExpectedLatency: 4c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 13 10
Queue TopQ.P:
Queue TopQ.A: 0 2 5 6
BotQ.A RemLatency SU(13) 10c
BotQ.A RemainingLatency 10 + 5c > CritPath 11
Picking from Bot:
Cand SU(13) ORDER
Picking from Top:
Cand SU(6) NOCAND
Pick Bot ORDER
Scheduling SU(13) undef %27.sublo:imag16 = COPY %28:ac
Bottom Pressure:
Ac=1
Yc=1
XY=1
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
Imag8=5
GPR_LSB_with_Imag8=6
Anyi1=6
Anyi1_with_Pc=6
GPR_LSB: 2 <= 3(+ 0 livethru)
MOSAsmParamRegClass: 2 <= 4(+ 0 livethru)
LiveReg: %28
UpdateRegP: SU(13) undef %27.sublo:imag16 = COPY %28:ac
to Imag8 -2 GPR_LSB_with_Imag8 -2 Anyi1 -2 Anyi1_with_Pc -2
Ready @5c
BotQ.A TopLatency SU(13) 10c
BotQ.A @5c
Retired: 1
Executed: 5c
Critical: 1c, 1 MOps
ExpectedLatency: 4c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 10 11
Queue TopQ.P:
Queue TopQ.A: 0 2 5 6
BotQ.A RemLatency SU(10) 7c
BotQ.A RemainingLatency 10 + 5c > CritPath 11
Picking from Bot:
Try SU(10) Ac:1
Cand SU(10) ORDER
Try SU(11) Yc:1
Cand SU(11) REG-EXCESS Yc:1
Picking from Top:
Cand SU(6) NOCAND
Pick Bot REG-EXCESS
Scheduling SU(11) %28:ac = LDYIndir %34:imag16, %33:yc :: (load 1 from %ir.vfn3)
Bottom Pressure:
Yc=2
XY=2
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
Imag8=6
GPR_LSB_with_Imag8=8
Anyi1=8
Anyi1_with_Pc=8
XY: 2 <= 2(+ 0 livethru)
LiveReg: %34
UpdateRegP: SU(11) %28:ac = LDYIndir %34:imag16, %33:yc :: (load 1 from %ir.vfn3)
to Ac -1 Yc 1 XY 1 Imag8 -1
LiveReg: %33
UpdateRegP: SU(11) %28:ac = LDYIndir %34:imag16, %33:yc :: (load 1 from %ir.vfn3)
to Ac -1 GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 Imag8 -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Ready @9c
*** Stall until: 9
BotQ.A BotLatency SU(11) 5c
Cycle: 9 BotQ.A
*** Max MOps 1 at cycle 9
Cycle: 10 BotQ.A
BotQ.A @10c
Retired: 2
Executed: 10c
Critical: 2c, 2 MOps
ExpectedLatency: 5c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 10 5
Queue TopQ.P:
Queue TopQ.A: 0 2 5 6
BotQ.A RemLatency SU(10) 7c
BotQ.A RemainingLatency 7 + 10c > CritPath 11
Picking from Bot:
Cand SU(10) ORDER
Try SU(5) Yc:-1
Cand SU(5) REG-EXCESS Yc:-1
Picking from Top:
Cand SU(6) NOCAND
Pick Bot REG-EXCESS
Scheduling SU(5) %33:yc = LDImm 2
handleMove 1072B -> 1224B: %33:yc = LDImm 2
%33: [1072r,1232r:0) 0@1072r
--> [1224r,1232r:0) 0@1224r
Bottom Pressure:
Yc=1
XY=1
GPR_LSB=1
MOSAsmParamRegClass=1
CV_GPR_LSB=1
CV_GPR_LSB_with_MOSAsmParamRegClass=1
CV_GPR_LSB_with_Pc=1
Imag8=6
GPR_LSB_with_Imag8=7
Anyi1=7
Anyi1_with_Pc=7
XY: 2 <= 2(+ 0 livethru)
GPR_LSB: 2 <= 3(+ 0 livethru)
MOSAsmParamRegClass: 2 <= 4(+ 0 livethru)
Ready @10c
BotQ.A BotLatency SU(5) 6c
*** Max MOps 1 at cycle 10
Cycle: 11 BotQ.A
BotQ.A @11c
Retired: 3
Executed: 11c
Critical: 3c, 3 MOps
ExpectedLatency: 6c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 10
Pick Bot ONLY1
Scheduling SU(10) %14.subhi:imag16 = COPY %85:ac
Bottom Pressure:
Ac=1
Yc=1
XY=1
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
Imag8=7
GPR_LSB_with_Imag8=8
Anyi1=8
Anyi1_with_Pc=8
GPR_LSB: 2 <= 3(+ 0 livethru)
MOSAsmParamRegClass: 2 <= 4(+ 0 livethru)
LiveReg: %14
UpdateRegP: SU(10) %14.subhi:imag16 = COPY %85:ac
to Ac 1 GPR_LSB 1 MOSAsmParamRegClass 1 CV_GPR_LSB 1 CV_GPR_LSB_with_MOSAsmParamRegClass 1 CV_GPR_LSB_with_Pc 1 Imag8 -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
LiveReg: %85
UpdateRegP: SU(10) %14.subhi:imag16 = COPY %85:ac
to Imag8 -2 GPR_LSB_with_Imag8 -2 Anyi1 -2 Anyi1_with_Pc -2
Ready @11c
BotQ.A TopLatency SU(10) 7c
BotQ.A @11c
Retired: 3
Executed: 11c
Critical: 3c, 3 MOps
ExpectedLatency: 6c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 9 8
Queue TopQ.P:
Queue TopQ.A: 0 2 6
BotQ.A RemLatency SU(9) 6c
BotQ.A RemainingLatency 7 + 11c > CritPath 11
Picking from Bot:
Try SU(9) Ac:1
Cand SU(9) ORDER
Cand SU(8) REG-EXCESS
Picking from Top:
Cand SU(6) NOCAND
Pick Bot REG-EXCESS
Scheduling SU(8) %85:ac, dead %86:cc, dead %87:vc = ADCImm %85:ac(tied-def 0), 0, %86:cc(tied-def 1)
handleMove 1184B -> 1208B: %85:ac, dead %86:cc, dead %87:vc = ADCImm %85:ac(tied-def 0), 0, %86:cc(tied-def 1)
%85: [1024r,1184r:0)[1184r,1216r:1) 0@1024r 1@1184r
--> [1024r,1208r:0)[1208r,1216r:1) 0@1024r 1@1208r
%86: [1088r,1136r:2)[1136r,1184r:0)[1184r,1184d:1) 0@1136r 1@1184r 2@1088r
--> [1088r,1136r:2)[1136r,1208r:0)[1208r,1208d:1) 0@1136r 1@1208r 2@1088r
%87: [1184r,1184d:0) 0@1184r
--> [1208r,1208d:0) 0@1208r
Bottom Pressure:
Cc=1
Ac=1
Yc=1
XY=1
GPR_LSB=2
Pc=1
MOSAsmParamRegClass=2
CV_GPR_LSB=3
CV_GPR_LSB_with_MOSAsmParamRegClass=3
CV_GPR_LSB_with_Pc=3
Imag8=7
GPR_LSB_with_Imag8=8
Anyi1=9
Anyi1_with_Pc=9
Pc: 2 <= 4(+ 0 livethru)
CV_GPR_LSB: 4 <= 5(+ 0 livethru)
CV_GPR_LSB_with_MOSAsmParamRegClass: 4 <= 6(+ 0 livethru)
LiveReg: %85
UpdateRegP: SU(4) %34.subhi:imag16 = COPY %85:ac
to
UpdateRegP: SU(8) %85:ac, dead %86:cc, dead %87:vc = ADCImm %85:ac(tied-def 0), 0, %86:cc(tied-def 1)
to Cc 1 Ac -1 GPR_LSB -1 Pc 1 MOSAsmParamRegClass -1 Imag8 -1 GPR_LSB_with_Imag8 -1
LiveReg: %86
UpdateRegP: SU(8) %85:ac, dead %86:cc, dead %87:vc = ADCImm %85:ac(tied-def 0), 0, %86:cc(tied-def 1)
to Ac -1 GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 Imag8 -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Ready @12c
*** Stall until: 12
Cycle: 12 BotQ.A
*** Max MOps 1 at cycle 12
Cycle: 13 BotQ.A
BotQ.A @13c
Retired: 4
Executed: 13c
Critical: 4c, 4 MOps
ExpectedLatency: 6c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 9 4
Queue TopQ.P:
Queue TopQ.A: 0 2 6
BotQ.A RemainingLatency 0 + 13c > CritPath 11
Picking from Bot:
Try SU(9) Ac:1
Cand SU(9) ORDER
Cand SU(4) REG-EXCESS
Picking from Top:
Cand SU(6) NOCAND
Pick Bot REG-EXCESS
Scheduling SU(4) %34.subhi:imag16 = COPY %85:ac
handleMove 1056B -> 1204B: %34.subhi:imag16 = COPY %85:ac
%34 L0000000000000020: [1056r,1232r:0) 0@1056r
--> [1204r,1232r:0) 0@1204r
%34: [1040r,1056r:0)[1056r,1232r:1) 0@1040r 1@1056r
--> [1040r,1204r:0)[1204r,1232r:1) 0@1040r 1@1204r
%85: [1024r,1208r:0)[1208r,1216r:1) 0@1024r 1@1208r
--> [1024r,1208r:0)[1208r,1216r:1) 0@1024r 1@1208r
Bottom Pressure:
Cc=1
Ac=1
Yc=1
XY=1
GPR_LSB=2
Pc=1
MOSAsmParamRegClass=2
CV_GPR_LSB=3
CV_GPR_LSB_with_MOSAsmParamRegClass=3
CV_GPR_LSB_with_Pc=3
Imag8=7
GPR_LSB_with_Imag8=8
Anyi1=9
Anyi1_with_Pc=9
LiveReg: %34
UpdateRegP: SU(4) %34.subhi:imag16 = COPY %85:ac
to Imag8 -2 GPR_LSB_with_Imag8 -2 Anyi1 -2 Anyi1_with_Pc -2
Ready @13c
BotQ.A TopLatency SU(4) 6c
BotQ.A @13c
Retired: 4
Executed: 13c
Critical: 4c, 4 MOps
ExpectedLatency: 6c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 9 2
Queue TopQ.P:
Queue TopQ.A: 0 2 6
BotQ.A RemainingLatency 0 + 13c > CritPath 11
Picking from Bot:
Try SU(9) Ac:1
Cand SU(9) ORDER
Cand SU(2) REG-EXCESS
Picking from Top:
Cand SU(6) NOCAND
Pick Bot REG-EXCESS
Scheduling SU(2) %85:ac = LDYIndir %4:imag16, %53:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
*** Renumbered SlotIndexes 1200-1256 ***
handleMove 1024B -> 1208B: %85:ac = LDYIndir %4:imag16, %53:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
%85: [1024r,1224r:0)[1224r,1232r:1) 0@1024r 1@1224r
--> [1208r,1224r:0)[1224r,1232r:1) 0@1208r 1@1224r
%4: [144r,1328r:0) 0@144r
--> [144r,1328r:0) 0@144r
%53: [528r,1272r:0) 0@528r
--> [528r,1272r:0) 0@528r
Bottom Pressure:
Cc=1
Yc=1
XY=1
GPR_LSB=1
Pc=1
MOSAsmParamRegClass=1
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
Imag8=6
GPR_LSB_with_Imag8=7
Anyi1=8
Anyi1_with_Pc=8
GPR_LSB: 2 <= 3(+ 0 livethru)
MOSAsmParamRegClass: 2 <= 4(+ 0 livethru)
CV_GPR_LSB: 4 <= 5(+ 0 livethru)
CV_GPR_LSB_with_MOSAsmParamRegClass: 4 <= 6(+ 0 livethru)
Ready @17c
*** Stall until: 17
BotQ.A BotLatency SU(2) 9c
Cycle: 17 BotQ.A
*** Max MOps 1 at cycle 17
Cycle: 18 BotQ.A
BotQ.A @18c
Retired: 5
Executed: 18c
Critical: 5c, 5 MOps
ExpectedLatency: 9c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 9
Pick Bot ONLY1
Scheduling SU(9) undef %14.sublo:imag16 = COPY %82:ac
Bottom Pressure:
Cc=1
Ac=1
Yc=1
XY=1
GPR_LSB=2
Pc=1
MOSAsmParamRegClass=2
CV_GPR_LSB=3
CV_GPR_LSB_with_MOSAsmParamRegClass=3
CV_GPR_LSB_with_Pc=3
Imag8=5
GPR_LSB_with_Imag8=6
Anyi1=7
Anyi1_with_Pc=7
GPR_LSB: 2 <= 3(+ 0 livethru)
MOSAsmParamRegClass: 2 <= 4(+ 0 livethru)
CV_GPR_LSB: 4 <= 5(+ 0 livethru)
CV_GPR_LSB_with_MOSAsmParamRegClass: 4 <= 6(+ 0 livethru)
LiveReg: %82
UpdateRegP: SU(9) undef %14.sublo:imag16 = COPY %82:ac
to Imag8 -2 GPR_LSB_with_Imag8 -2 Anyi1 -2 Anyi1_with_Pc -2
Ready @18c
BotQ.A TopLatency SU(9) 6c
BotQ.A @18c
Retired: 5
Executed: 18c
Critical: 5c, 5 MOps
ExpectedLatency: 9c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 7
Pick Bot ONLY1
Scheduling SU(7) %82:ac, %86:cc, dead %88:vc = ADCImm %82:ac(tied-def 0), 2, %86:cc(tied-def 1)
Bottom Pressure:
Cc=1
Ac=1
Yc=1
XY=1
GPR_LSB=2
Pc=1
MOSAsmParamRegClass=2
CV_GPR_LSB=3
CV_GPR_LSB_with_MOSAsmParamRegClass=3
CV_GPR_LSB_with_Pc=3
Imag8=5
GPR_LSB_with_Imag8=6
Anyi1=7
Anyi1_with_Pc=7
LiveReg: %82
UpdateRegP: SU(3) undef %34.sublo:imag16 = COPY %82:ac
to Imag8 -2 GPR_LSB_with_Imag8 -2 Anyi1 -2 Anyi1_with_Pc -2
UpdateRegP: SU(7) %82:ac, %86:cc, dead %88:vc = ADCImm %82:ac(tied-def 0), 2, %86:cc(tied-def 1)
to Ac -1 GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 Imag8 -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
LiveReg: %86
UpdateRegP: SU(7) %82:ac, %86:cc, dead %88:vc = ADCImm %82:ac(tied-def 0), 2, %86:cc(tied-def 1)
to Cc -1 Ac -1 GPR_LSB -1 Pc -1 MOSAsmParamRegClass -1 CV_GPR_LSB -2 CV_GPR_LSB_with_MOSAsmParamRegClass -2 CV_GPR_LSB_with_Pc -2 Imag8 -1 GPR_LSB_with_Imag8 -1 Anyi1 -2 Anyi1_with_Pc -2
Ready @19c
*** Stall until: 19
Cycle: 19 BotQ.A
*** Max MOps 1 at cycle 19
Cycle: 20 BotQ.A
BotQ.A @20c
Retired: 6
Executed: 20c
Critical: 6c, 6 MOps
ExpectedLatency: 9c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 3 6
Queue TopQ.P:
Queue TopQ.A: 0 6
BotQ.A RemainingLatency 0 + 20c > CritPath 11
Picking from Bot:
Cand SU(3) ORDER
Cand SU(6) ORDER
Picking from Top:
Cand SU(6) NOCAND
Pick Bot ORDER
Scheduling SU(6) %86:cc = LDImm1 0
Bottom Pressure:
Ac=1
Yc=1
XY=1
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
Imag8=5
GPR_LSB_with_Imag8=6
Anyi1=6
Anyi1_with_Pc=6
Pc: 2 <= 4(+ 0 livethru)
CV_GPR_LSB: 4 <= 5(+ 0 livethru)
CV_GPR_LSB_with_MOSAsmParamRegClass: 4 <= 6(+ 0 livethru)
Ready @20c
*** Max MOps 1 at cycle 20
Cycle: 21 BotQ.A
BotQ.A @21c
Retired: 7
Executed: 21c
Critical: 7c, 7 MOps
ExpectedLatency: 9c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 3
Pick Bot ONLY1
Scheduling SU(3) undef %34.sublo:imag16 = COPY %82:ac
Bottom Pressure:
Ac=1
Yc=1
XY=1
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
Imag8=3
GPR_LSB_with_Imag8=4
Anyi1=4
Anyi1_with_Pc=4
Ready @21c
BotQ.A TopLatency SU(3) 5c
BotQ.A @21c
Retired: 7
Executed: 21c
Critical: 7c, 7 MOps
ExpectedLatency: 9c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 1
Pick Bot ONLY1
Scheduling SU(1) %82:ac = LDYIndir %4:imag16, %89:yc :: (load 1 from %ir.3, !tbaa !2)
Bottom Pressure:
Yc=2
XY=2
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
Imag8=2
GPR_LSB_with_Imag8=4
Anyi1=4
Anyi1_with_Pc=4
XY: 2 <= 2(+ 0 livethru)
LiveReg: %89
UpdateRegP: SU(1) %82:ac = LDYIndir %4:imag16, %89:yc :: (load 1 from %ir.3, !tbaa !2)
to Ac -1 GPR_LSB -1 MOSAsmParamRegClass -1 CV_GPR_LSB -1 CV_GPR_LSB_with_MOSAsmParamRegClass -1 CV_GPR_LSB_with_Pc -1 Imag8 -1 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Ready @25c
*** Stall until: 25
BotQ.A BotLatency SU(1) 10c
Cycle: 25 BotQ.A
*** Max MOps 1 at cycle 25
Cycle: 26 BotQ.A
BotQ.A @26c
Retired: 8
Executed: 26c
Critical: 8c, 8 MOps
ExpectedLatency: 10c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 0
Pick Bot ONLY1
Scheduling SU(0) %89:yc = LDImm 0
Bottom Pressure:
Yc=1
XY=1
GPR_LSB=1
MOSAsmParamRegClass=1
CV_GPR_LSB=1
CV_GPR_LSB_with_MOSAsmParamRegClass=1
CV_GPR_LSB_with_Pc=1
Imag8=2
GPR_LSB_with_Imag8=3
Anyi1=3
Anyi1_with_Pc=3
XY: 2 <= 2(+ 0 livethru)
GPR_LSB: 2 <= 3(+ 0 livethru)
MOSAsmParamRegClass: 2 <= 4(+ 0 livethru)
CV_GPR_LSB: 4 <= 5(+ 0 livethru)
CV_GPR_LSB_with_MOSAsmParamRegClass: 4 <= 6(+ 0 livethru)
Ready @26c
BotQ.A BotLatency SU(0) 11c
*** Max MOps 1 at cycle 26
Cycle: 27 BotQ.A
BotQ.A @27c
Retired: 9
Executed: 27c
Critical: 9c, 9 MOps
ExpectedLatency: 11c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
*** Final schedule for %bb.6 ***
SU(0): %89:yc = LDImm 0
SU(1): %82:ac = LDYIndir %4:imag16, %89:yc :: (load 1 from %ir.3, !tbaa !2)
SU(3): undef %34.sublo:imag16 = COPY %82:ac
SU(6): %86:cc = LDImm1 0
SU(7): %82:ac, %86:cc, dead %88:vc = ADCImm %82:ac(tied-def 0), 2, %86:cc(tied-def 1)
SU(9): undef %14.sublo:imag16 = COPY %82:ac
SU(2): %85:ac = LDYIndir %4:imag16, %53:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
SU(4): %34.subhi:imag16 = COPY %85:ac
SU(8): %85:ac, dead %86:cc, dead %87:vc = ADCImm %85:ac(tied-def 0), 0, %86:cc(tied-def 1)
SU(10): %14.subhi:imag16 = COPY %85:ac
SU(5): %33:yc = LDImm 2
SU(11): %28:ac = LDYIndir %34:imag16, %33:yc :: (load 1 from %ir.vfn3)
SU(13): undef %27.sublo:imag16 = COPY %28:ac
SU(12): %31:ac = LDYIndir %14:imag16, %53:yc :: (load 1 from %ir.vfn3 + 1)
SU(14): %27.subhi:imag16 = COPY %31:ac
SU(15): $rs8 = COPY %27:imag16
********** MI Scheduling **********
_Z11testIndCallc:%bb.6 select.end8
From: undef %41.sublo:imag16 = COPY %103:gpr
To: ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
RegionInstrs: 3
ScheduleDAGMILive::schedule starting
GenericScheduler RegionPolicy: ShouldTrackPressure=1 OnlyTopDown=0 OnlyBottomUp=0
Max Pressure: GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
Imag8=2
GPR_LSB_with_Imag8=3
Anyi1=3
Anyi1_with_Pc=3
Live In: %104 %103
Live Out: RC16LSB RC17LSB
Live Thru:
Top Pressure:
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
GPR_LSB_with_Imag8=2
Anyi1=2
Anyi1_with_Pc=2
Bottom Pressure:
Imag8=2
GPR_LSB_with_Imag8=2
Anyi1=2
Anyi1_with_Pc=2
Excess PSets:
SU(0): undef %41.sublo:imag16 = COPY %103:gpr
# preds left : 0
# succs left : 1
# rdefs left : 0
Latency : 0
Depth : 0
Height : 1
Successors:
SU(1): Out Latency=1
Pressure Diff : GPR_LSB 1 MOSAsmParamRegClass 1 CV_GPR_LSB 1 CV_GPR_LSB_with_MOSAsmParamRegClass 1 CV_GPR_LSB_with_Pc 1 Imag8 -2 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
Single Issue : false;
SU(1): %41.subhi:imag16 = COPY %104:gpr
# preds left : 1
# succs left : 1
# rdefs left : 0
Latency : 0
Depth : 1
Height : 0
Predecessors:
SU(0): Out Latency=1
Successors:
SU(2): Data Latency=0 Reg=%41
Pressure Diff : GPR_LSB 1 MOSAsmParamRegClass 1 CV_GPR_LSB 1 CV_GPR_LSB_with_MOSAsmParamRegClass 1 CV_GPR_LSB_with_Pc 1 GPR_LSB_with_Imag8 1 Anyi1 1 Anyi1_with_Pc 1
Single Issue : false;
SU(2): $rs8 = COPY %41:imag16
# preds left : 1
# succs left : 0
# rdefs left : 0
Latency : 0
Depth : 1
Height : 0
Predecessors:
SU(1): Data Latency=0 Reg=%41
Pressure Diff :
Single Issue : false;
ExitSU: ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
# preds left : 0
# succs left : 0
# rdefs left : 0
Latency : 0
Depth : 0
Height : 0
Critical Path(GS-RR ): 1
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 2
Pick Bot ONLY1
Scheduling SU(2) $rs8 = COPY %41:imag16
Bottom Pressure:
Imag8=2
GPR_LSB_with_Imag8=2
Anyi1=2
Anyi1_with_Pc=2
LiveReg: %41
UpdateRegP: SU(2) $rs8 = COPY %41:imag16
to Imag8 -2 GPR_LSB_with_Imag8 -2 Anyi1 -2 Anyi1_with_Pc -2
Ready @0c
BotQ.A TopLatency SU(2) 1c
BotQ.A @0c
Retired: 0
Executed: 0c
Critical: 0c, 0 MOps
ExpectedLatency: 0c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 1
Pick Bot ONLY1
Scheduling SU(1) %41.subhi:imag16 = COPY %104:gpr
Bottom Pressure:
GPR_LSB=1
MOSAsmParamRegClass=1
CV_GPR_LSB=1
CV_GPR_LSB_with_MOSAsmParamRegClass=1
CV_GPR_LSB_with_Pc=1
Imag8=2
GPR_LSB_with_Imag8=3
Anyi1=3
Anyi1_with_Pc=3
GPR_LSB: 1 <= 3(+ 0 livethru)
LiveReg: %41
UpdateRegP: SU(1) %41.subhi:imag16 = COPY %104:gpr
to GPR_LSB 1 MOSAsmParamRegClass 1 CV_GPR_LSB 1 CV_GPR_LSB_with_MOSAsmParamRegClass 1 CV_GPR_LSB_with_Pc 1 Imag8 -2 GPR_LSB_with_Imag8 -1 Anyi1 -1 Anyi1_with_Pc -1
LiveReg: %104
UpdateRegP: SU(1) %41.subhi:imag16 = COPY %104:gpr
to Imag8 -2 GPR_LSB_with_Imag8 -2 Anyi1 -2 Anyi1_with_Pc -2
Ready @0c
BotQ.A @0c
Retired: 0
Executed: 0c
Critical: 0c, 0 MOps
ExpectedLatency: 0c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P:
Queue BotQ.A: 0
Pick Bot ONLY1
Scheduling SU(0) undef %41.sublo:imag16 = COPY %103:gpr
Bottom Pressure:
GPR_LSB=2
MOSAsmParamRegClass=2
CV_GPR_LSB=2
CV_GPR_LSB_with_MOSAsmParamRegClass=2
CV_GPR_LSB_with_Pc=2
GPR_LSB_with_Imag8=2
Anyi1=2
Anyi1_with_Pc=2
GPR_LSB: 2 <= 3(+ 0 livethru)
MOSAsmParamRegClass: 2 <= 4(+ 0 livethru)
LiveReg: %103
UpdateRegP: SU(0) undef %41.sublo:imag16 = COPY %103:gpr
to Imag8 -2 GPR_LSB_with_Imag8 -2 Anyi1 -2 Anyi1_with_Pc -2
Ready @1c
*** Stall until: 1
BotQ.A BotLatency SU(0) 1c
Cycle: 1 BotQ.A
BotQ.A @1c
Retired: 0
Executed: 1c
Critical: 0c, 0 MOps
ExpectedLatency: 1c
- Latency limited.
** ScheduleDAGMILive::schedule picking next node
*** Final schedule for %bb.6 ***
SU(0): undef %41.sublo:imag16 = COPY %103:gpr
SU(1): %41.subhi:imag16 = COPY %104:gpr
SU(2): $rs8 = COPY %41:imag16
********** INTERVALS **********
ALSB [0B,16r:0)[120r,128r:1) 0@0B-phi 1@120r
%1 [16r,560r:0) 0@16r weight:0.000000e+00
%2 [48r,512r:0) 0@48r weight:0.000000e+00
%4 [144r,1328r:0) 0@144r weight:0.000000e+00
%14 [1200r,1232r:0)[1232r,1272r:1) 0@1200r 1@1232r L0000000000000002 [1200r,1272r:0) 0@1200r L0000000000000020 [1232r,1272r:0) 0@1232r weight:0.000000e+00
%27 [1264r,1280r:0)[1280r,1296r:1) 0@1264r 1@1280r L0000000000000002 [1264r,1296r:0) 0@1264r L0000000000000020 [1280r,1296r:0) 0@1280r weight:0.000000e+00
%28 [1248r,1264r:0) 0@1248r weight:0.000000e+00
%31 [1272r,1280r:0) 0@1272r weight:0.000000e+00
%33 [1240r,1248r:0) 0@1240r weight:0.000000e+00
%34 [1040r,1216r:0)[1216r,1248r:1) 0@1040r 1@1216r L0000000000000002 [1040r,1248r:0) 0@1040r L0000000000000020 [1216r,1248r:0) 0@1216r weight:0.000000e+00
%41 [880r,896r:0)[896r,912r:1) 0@880r 1@896r L0000000000000002 [880r,912r:0) 0@880r L0000000000000020 [896r,912r:0) 0@896r weight:0.000000e+00
%53 [528r,1272r:0) 0@528r weight:0.000000e+00
%82 [1008r,1136r:0)[1136r,1200r:1) 0@1008r 1@1136r weight:0.000000e+00
%85 [1208r,1224r:0)[1224r,1232r:1) 0@1208r 1@1224r weight:0.000000e+00
%86 [1088r,1136r:2)[1136r,1224r:0)[1224r,1224d:1) 0@1136r 1@1224r 2@1088r weight:0.000000e+00
%87 [1224r,1224d:0) 0@1224r weight:0.000000e+00
%88 [1136r,1136d:0) 0@1136r weight:0.000000e+00
%89 [992r,1008r:0) 0@992r weight:0.000000e+00
%92 [560r,560d:0) 0@560r weight:0.000000e+00
%98 [176r,176d:0) 0@176r weight:0.000000e+00
%101 [224r,336B:0)[352r,448B:1)[448B,512r:2) 0@224r 1@352r 2@448B-phi weight:0.000000e+00
%102 [240r,336B:0)[368r,448B:1)[448B,544r:2) 0@240r 1@368r 2@448B-phi weight:0.000000e+00
%103 [608r,720B:0)[736r,832B:1)[832B,880r:2) 0@608r 1@736r 2@832B-phi weight:0.000000e+00
%104 [624r,720B:0)[752r,832B:1)[832B,896r:2) 0@624r 1@752r 2@832B-phi weight:0.000000e+00
RegMasks: 128r 960r 1344r
********** MACHINEINSTRS **********
# Machine code for function _Z11testIndCallc: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
successors: %bb.1(0x30000000), %bb.2(0x50000000); %bb.1(37.50%), %bb.2(62.50%)
liveins: $a
16B %1:gpr = COPY $a
48B %2:yc = LDImm 0
64B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
112B $x = COPY %2:yc
120B $a = LDImm 2
128B JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $a, implicit killed $x, implicit-def $rs1
144B %4:imag16 = COPY killed $rs1
160B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
176B dead %98:cc = CMPImmTerm %1:gpr, 0, implicit-def dead $nz, implicit-def $z
192B BR %bb.2, killed $z, 0
208B bb.1:
; predecessors: %bb.0
successors: %bb.3(0x80000000); %bb.3(100.00%)
224B %101:ac = LDImm target-flags(lo) @_ZTV4SubB + 4
240B %102:ac = LDImm target-flags(hi) @_ZTV4SubB + 4
320B JMP %bb.3
336B bb.2.select.false:
; predecessors: %bb.0
successors: %bb.3(0x80000000); %bb.3(100.00%)
352B %101:ac = LDImm target-flags(lo) @_ZTV4SubA + 4
368B %102:ac = LDImm target-flags(hi) @_ZTV4SubA + 4
448B bb.3.select.end:
; predecessors: %bb.2, %bb.1
successors: %bb.4(0x30000000), %bb.5(0x50000000); %bb.4(37.50%), %bb.5(62.50%)
512B STYIndir %101:ac, %4:imag16, %2:yc :: (store 1 into %ir.0, !tbaa !2)
528B %53:yc = LDImm 1
544B STYIndir %102:ac, %4:imag16, %53:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
560B dead %92:cc = CMPImmTerm %1:gpr, 0, implicit-def dead $nz, implicit-def $z
576B BR %bb.5, killed $z, 0
592B bb.4:
; predecessors: %bb.3
successors: %bb.6(0x80000000); %bb.6(100.00%)
608B %103:gpr = LDImm target-flags(lo) @_ZN4SubB2fnEv
624B %104:gpr = LDImm target-flags(hi) @_ZN4SubB2fnEv
704B JMP %bb.6
720B bb.5.select.false9:
; predecessors: %bb.3
successors: %bb.6(0x80000000); %bb.6(100.00%)
736B %103:gpr = LDImm target-flags(lo) @_ZN4SubA2fnEv
752B %104:gpr = LDImm target-flags(hi) @_ZN4SubA2fnEv
832B bb.6.select.end8:
; predecessors: %bb.5, %bb.4
880B undef %41.sublo:imag16 = COPY %103:gpr
896B %41.subhi:imag16 = COPY %104:gpr
912B $rs8 = COPY %41:imag16
928B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
944B $rs1 = COPY %4:imag16
960B JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit killed $rs8, implicit killed $rs1
976B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
992B %89:yc = LDImm 0
1008B %82:ac = LDYIndir %4:imag16, %89:yc :: (load 1 from %ir.3, !tbaa !2)
1040B undef %34.sublo:imag16 = COPY %82:ac
1088B %86:cc = LDImm1 0
1136B %82:ac, %86:cc, dead %88:vc = ADCImm %82:ac(tied-def 0), 2, %86:cc(tied-def 1)
1200B undef %14.sublo:imag16 = COPY %82:ac
1208B %85:ac = LDYIndir %4:imag16, %53:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
1216B %34.subhi:imag16 = COPY %85:ac
1224B %85:ac, dead %86:cc, dead %87:vc = ADCImm %85:ac(tied-def 0), 0, %86:cc(tied-def 1)
1232B %14.subhi:imag16 = COPY %85:ac
1240B %33:yc = LDImm 2
1248B %28:ac = LDYIndir %34:imag16, %33:yc :: (load 1 from %ir.vfn3)
1264B undef %27.sublo:imag16 = COPY %28:ac
1272B %31:ac = LDYIndir %14:imag16, %53:yc :: (load 1 from %ir.vfn3 + 1)
1280B %27.subhi:imag16 = COPY %31:ac
1296B $rs8 = COPY %27:imag16
1312B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
1328B $rs1 = COPY %4:imag16
1344B JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit killed $rs8, implicit killed $rs1
1360B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
1376B RTS
# End machine code for function _Z11testIndCallc.
block-frequency: _Z11testIndCallc
=================================
reverse-post-order-traversal
- 0: BB0[entry]
- 1: BB2[select.false]
- 2: BB1
- 3: BB3[select.end]
- 4: BB5[select.false9]
- 5: BB4
- 6: BB6[select.end8]
loop-detection
compute-mass-in-function
- node: BB0[entry]
=> [ local ] weight = 805306368, succ = BB1
=> [ local ] weight = 1342177280, succ = BB2[select.false]
=> mass: ffffffffffffffff
=> assign 9fffffffffffffff (6000000000000000) to BB2[select.false]
=> assign 6000000000000000 (0000000000000000) to BB1
- node: BB2[select.false]
=> [ local ] weight = 2147483648, succ = BB3[select.end]
=> mass: 9fffffffffffffff
=> assign 9fffffffffffffff (0000000000000000) to BB3[select.end]
- node: BB1
=> [ local ] weight = 2147483648, succ = BB3[select.end]
=> mass: 6000000000000000
=> assign 6000000000000000 (0000000000000000) to BB3[select.end]
- node: BB3[select.end]
=> [ local ] weight = 805306368, succ = BB4
=> [ local ] weight = 1342177280, succ = BB5[select.false9]
=> mass: ffffffffffffffff
=> assign 9fffffffffffffff (6000000000000000) to BB5[select.false9]
=> assign 6000000000000000 (0000000000000000) to BB4
- node: BB5[select.false9]
=> [ local ] weight = 2147483648, succ = BB6[select.end8]
=> mass: 9fffffffffffffff
=> assign 9fffffffffffffff (0000000000000000) to BB6[select.end8]
- node: BB4
=> [ local ] weight = 2147483648, succ = BB6[select.end8]
=> mass: 6000000000000000
=> assign 6000000000000000 (0000000000000000) to BB6[select.end8]
- node: BB6[select.end8]
=> mass: ffffffffffffffff
float-to-int: min = 0.375, max = 1.0, factor = 21.33333333
- BB0[entry]: float = 1.0, scaled = 21.33333333, int = 21
- BB2[select.false]: float = 0.625, scaled = 13.33333333, int = 13
- BB1: float = 0.375, scaled = 8.0, int = 8
- BB3[select.end]: float = 1.0, scaled = 21.33333333, int = 21
- BB5[select.false9]: float = 0.625, scaled = 13.33333333, int = 13
- BB4: float = 0.375, scaled = 8.0, int = 8
- BB6[select.end8]: float = 1.0, scaled = 21.33333333, int = 21
block-frequency-info: _Z11testIndCallc
- BB0[entry]: float = 1.0, int = 21
- BB1: float = 0.375, int = 8
- BB2[select.false]: float = 0.625, int = 13
- BB3[select.end]: float = 1.0, int = 21
- BB4: float = 0.375, int = 8
- BB5[select.false9]: float = 0.625, int = 13
- BB6[select.end8]: float = 1.0, int = 21
********** GREEDY REGISTER ALLOCATION **********
********** Function: _Z11testIndCallc
********** Compute Spill Weights **********
********** Function: _Z11testIndCallc
********** INTERVALS **********
ALSB [0B,16r:0)[120r,128r:1) 0@0B-phi 1@120r
%1 [16r,560r:0) 0@16r weight:3.209746e-03
%2 [48r,512r:0) 0@48r weight:1.736111e-03
%4 [144r,1328r:0) 0@144r weight:4.463383e-03
%14 [1200r,1232r:0)[1232r,1272r:1) 0@1200r 1@1232r L0000000000000002 [1200r,1272r:0) 0@1200r L0000000000000020 [1232r,1272r:0) 0@1232r weight:8.474576e-03
%27 [1264r,1280r:0)[1280r,1296r:1) 0@1264r 1@1280r L0000000000000002 [1264r,1296r:0) 0@1264r L0000000000000020 [1280r,1296r:0) 0@1280r weight:9.351851e-03
%28 [1248r,1264r:0) 0@1248r weight:INF
%31 [1272r,1280r:0) 0@1272r weight:INF
%33 [1240r,1248r:0) 0@1240r weight:INF
%34 [1040r,1216r:0)[1216r,1248r:1) 0@1040r 1@1216r L0000000000000002 [1040r,1248r:0) 0@1040r L0000000000000020 [1216r,1248r:0) 0@1216r weight:6.578947e-03
%41 [880r,896r:0)[896r,912r:1) 0@880r 1@896r L0000000000000002 [880r,912r:0) 0@880r L0000000000000020 [896r,912r:0) 0@896r weight:INF
%53 [528r,1272r:0) 0@528r weight:1.748252e-03
%82 [1008r,1136r:0)[1136r,1200r:1) 0@1008r 1@1136r weight:8.445946e-03
%85 [1208r,1224r:0)[1224r,1232r:1) 0@1208r 1@1224r weight:1.179245e-02
%86 [1088r,1136r:2)[1136r,1224r:0)[1224r,1224d:1) 0@1136r 1@1224r 2@1088r weight:9.310987e-03
%87 [1224r,1224d:0) 0@1224r weight:INF
%88 [1136r,1136d:0) 0@1136r weight:INF
%89 [992r,1008r:0) 0@992r weight:INF
%92 [560r,560d:0) 0@560r weight:INF
%98 [176r,176d:0) 0@176r weight:INF
%101 [224r,336B:0)[352r,448B:1)[448B,512r:2) 0@224r 1@352r 2@448B-phi weight:2.985075e-03
%102 [240r,336B:0)[368r,448B:1)[448B,544r:2) 0@240r 1@368r 2@448B-phi weight:2.985075e-03
%103 [608r,720B:0)[736r,832B:1)[832B,880r:2) 0@608r 1@736r 2@832B-phi weight:3.058104e-03
%104 [624r,720B:0)[752r,832B:1)[832B,896r:2) 0@624r 1@752r 2@832B-phi weight:3.134796e-03
RegMasks: 128r 960r 1344r
********** MACHINEINSTRS **********
# Machine code for function _Z11testIndCallc: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
successors: %bb.1(0x30000000), %bb.2(0x50000000); %bb.1(37.50%), %bb.2(62.50%)
liveins: $a
16B %1:gpr = COPY $a
48B %2:yc = LDImm 0
64B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
112B $x = COPY %2:yc
120B $a = LDImm 2
128B JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $a, implicit killed $x, implicit-def $rs1
144B %4:imag16 = COPY killed $rs1
160B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
176B dead %98:cc = CMPImmTerm %1:gpr, 0, implicit-def dead $nz, implicit-def $z
192B BR %bb.2, killed $z, 0
208B bb.1:
; predecessors: %bb.0
successors: %bb.3(0x80000000); %bb.3(100.00%)
224B %101:ac = LDImm target-flags(lo) @_ZTV4SubB + 4
240B %102:ac = LDImm target-flags(hi) @_ZTV4SubB + 4
320B JMP %bb.3
336B bb.2.select.false:
; predecessors: %bb.0
successors: %bb.3(0x80000000); %bb.3(100.00%)
352B %101:ac = LDImm target-flags(lo) @_ZTV4SubA + 4
368B %102:ac = LDImm target-flags(hi) @_ZTV4SubA + 4
448B bb.3.select.end:
; predecessors: %bb.2, %bb.1
successors: %bb.4(0x30000000), %bb.5(0x50000000); %bb.4(37.50%), %bb.5(62.50%)
512B STYIndir %101:ac, %4:imag16, %2:yc :: (store 1 into %ir.0, !tbaa !2)
528B %53:yc = LDImm 1
544B STYIndir %102:ac, %4:imag16, %53:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
560B dead %92:cc = CMPImmTerm %1:gpr, 0, implicit-def dead $nz, implicit-def $z
576B BR %bb.5, killed $z, 0
592B bb.4:
; predecessors: %bb.3
successors: %bb.6(0x80000000); %bb.6(100.00%)
608B %103:gpr = LDImm target-flags(lo) @_ZN4SubB2fnEv
624B %104:gpr = LDImm target-flags(hi) @_ZN4SubB2fnEv
704B JMP %bb.6
720B bb.5.select.false9:
; predecessors: %bb.3
successors: %bb.6(0x80000000); %bb.6(100.00%)
736B %103:gpr = LDImm target-flags(lo) @_ZN4SubA2fnEv
752B %104:gpr = LDImm target-flags(hi) @_ZN4SubA2fnEv
832B bb.6.select.end8:
; predecessors: %bb.5, %bb.4
880B undef %41.sublo:imag16 = COPY %103:gpr
896B %41.subhi:imag16 = COPY %104:gpr
912B $rs8 = COPY %41:imag16
928B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
944B $rs1 = COPY %4:imag16
960B JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit killed $rs8, implicit killed $rs1
976B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
992B %89:yc = LDImm 0
1008B %82:ac = LDYIndir %4:imag16, %89:yc :: (load 1 from %ir.3, !tbaa !2)
1040B undef %34.sublo:imag16 = COPY %82:ac
1088B %86:cc = LDImm1 0
1136B %82:ac, %86:cc, dead %88:vc = ADCImm %82:ac(tied-def 0), 2, %86:cc(tied-def 1)
1200B undef %14.sublo:imag16 = COPY %82:ac
1208B %85:ac = LDYIndir %4:imag16, %53:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
1216B %34.subhi:imag16 = COPY %85:ac
1224B %85:ac, dead %86:cc, dead %87:vc = ADCImm %85:ac(tied-def 0), 0, %86:cc(tied-def 1)
1232B %14.subhi:imag16 = COPY %85:ac
1240B %33:yc = LDImm 2
1248B %28:ac = LDYIndir %34:imag16, %33:yc :: (load 1 from %ir.vfn3)
1264B undef %27.sublo:imag16 = COPY %28:ac
1272B %31:ac = LDYIndir %14:imag16, %53:yc :: (load 1 from %ir.vfn3 + 1)
1280B %27.subhi:imag16 = COPY %31:ac
1296B $rs8 = COPY %27:imag16
1312B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
1328B $rs1 = COPY %4:imag16
1344B JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit killed $rs8, implicit killed $rs1
1360B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
1376B RTS
# End machine code for function _Z11testIndCallc.
selectOrSplit Imag16:%4 [144r,1328r:0) 0@144r weight:4.463383e-03 w=4.463383e-03
AllocationOrder(Imag16) = [ $rs1 $rs2 $rs3 $rs4 $rs5 $rs6 $rs7 $rs8 $rs9 $rs10 $rs11 $rs12 $rs13 $rs15 $rs16 $rs17 $rs18 $rs19 $rs20 $rs21 $rs22 $rs23 $rs24 $rs25 $rs26 $rs27 $rs28 $rs29 $rs30 $rs31 $rs32 $rs33 $rs34 $rs35 $rs36 $rs37 $rs38 $rs39 $rs40 $rs41 $rs42 $rs43 $rs44 $rs45 $rs46 $rs47 $rs48 $rs49 $rs50 $rs51 $rs52 $rs53 $rs54 $rs55 $rs56 $rs57 $rs58 $rs59 $rs60 $rs61 $rs62 $rs63 $rs64 $rs65 $rs66 $rs67 $rs68 $rs69 $rs70 $rs71 $rs72 $rs73 $rs74 $rs75 $rs76 $rs77 $rs78 $rs79 $rs80 $rs81 $rs82 $rs83 $rs84 $rs85 $rs86 $rs87 $rs88 $rs89 $rs90 $rs91 $rs92 $rs93 $rs94 $rs95 $rs96 $rs97 $rs98 $rs99 $rs100 $rs101 $rs102 $rs103 $rs104 $rs105 $rs106 $rs107 $rs108 $rs109 $rs110 $rs111 $rs112 $rs113 $rs114 $rs115 $rs116 $rs117 $rs118 $rs119 $rs120 $rs121 $rs122 $rs123 $rs124 $rs125 $rs126 ]
hints: $rs1
missed hint $rs1
assigning %4 to $rs15: RC30LSB [144r,1328r:0) 0@144r RC31LSB [144r,1328r:0) 0@144r
selectOrSplit GPR:%1 [16r,560r:0) 0@16r weight:3.209746e-03 w=3.209746e-03
AllocationOrder(Anyi8) = [ $a $x $y $rc2 $rc3 $rc4 $rc5 $rc6 $rc7 $rc8 $rc9 $rc10 $rc11 $rc12 $rc13 $rc14 $rc15 $rc16 $rc17 $rc18 $rc19 $rc20 $rc21 $rc22 $rc23 $rc24 $rc25 $rc26 $rc27 $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 $rc63 $rc64 $rc65 $rc66 $rc67 $rc68 $rc69 $rc70 $rc71 $rc72 $rc73 $rc74 $rc75 $rc76 $rc77 $rc78 $rc79 $rc80 $rc81 $rc82 $rc83 $rc84 $rc85 $rc86 $rc87 $rc88 $rc89 $rc90 $rc91 $rc92 $rc93 $rc94 $rc95 $rc96 $rc97 $rc98 $rc99 $rc100 $rc101 $rc102 $rc103 $rc104 $rc105 $rc106 $rc107 $rc108 $rc109 $rc110 $rc111 $rc112 $rc113 $rc114 $rc115 $rc116 $rc117 $rc118 $rc119 $rc120 $rc121 $rc122 $rc123 $rc124 $rc125 $rc126 $rc127 $rc128 $rc129 $rc130 $rc131 $rc132 $rc133 $rc134 $rc135 $rc136 $rc137 $rc138 $rc139 $rc140 $rc141 $rc142 $rc143 $rc144 $rc145 $rc146 $rc147 $rc148 $rc149 $rc150 $rc151 $rc152 $rc153 $rc154 $rc155 $rc156 $rc157 $rc158 $rc159 $rc160 $rc161 $rc162 $rc163 $rc164 $rc165 $rc166 $rc167 $rc168 $rc169 $rc170 $rc171 $rc172 $rc173 $rc174 $rc175 $rc176 $rc177 $rc178 $rc179 $rc180 $rc181 $rc182 $rc183 $rc184 $rc185 $rc186 $rc187 $rc188 $rc189 $rc190 $rc191 $rc192 $rc193 $rc194 $rc195 $rc196 $rc197 $rc198 $rc199 $rc200 $rc201 $rc202 $rc203 $rc204 $rc205 $rc206 $rc207 $rc208 $rc209 $rc210 $rc211 $rc212 $rc213 $rc214 $rc215 $rc216 $rc217 $rc218 $rc219 $rc220 $rc221 $rc222 $rc223 $rc224 $rc225 $rc226 $rc227 $rc228 $rc229 $rc230 $rc231 $rc232 $rc233 $rc234 $rc235 $rc236 $rc237 $rc238 $rc239 $rc240 $rc241 $rc242 $rc243 $rc244 $rc245 $rc246 $rc247 $rc248 $rc249 $rc250 $rc251 $rc252 $rc253 ]
AllocationOrder(GPR) = [ $a $x $y ] (sub-class)
hints: $a
RS_Assign Cascade 0
wait for second round
queuing new interval: %1 [16r,560r:0) 0@16r weight:3.209746e-03
selectOrSplit Imag16:%41 [880r,896r:0)[896r,912r:1) 0@880r 1@896r L0000000000000002 [880r,912r:0) 0@880r L0000000000000020 [896r,912r:0) 0@896r weight:INF w=INF
hints: $rs8
assigning %41 to $rs8: RC16LSB [880r,912r:0) 0@880r RC17LSB [896r,912r:0) 0@896r
selectOrSplit Imag16:%27 [1264r,1280r:0)[1280r,1296r:1) 0@1264r 1@1280r L0000000000000002 [1264r,1296r:0) 0@1264r L0000000000000020 [1280r,1296r:0) 0@1280r weight:9.351851e-03 w=9.351851e-03
hints: $rs8
assigning %27 to $rs8: RC16LSB [1264r,1296r:0) 0@1264r RC17LSB [1280r,1296r:0) 0@1280r
selectOrSplit Yc:%53 [528r,1272r:0) 0@528r weight:1.748252e-03 w=1.748252e-03
AllocationOrder(Yc) = [ $y ] (sub-class)
RS_Assign Cascade 0
wait for second round
queuing new interval: %53 [528r,1272r:0) 0@528r weight:1.748252e-03
selectOrSplit Yc:%2 [48r,512r:0) 0@48r weight:1.736111e-03 w=1.736111e-03
RS_Assign Cascade 0
wait for second round
queuing new interval: %2 [48r,512r:0) 0@48r weight:1.736111e-03
selectOrSplit Ac:%101 [224r,336B:0)[352r,448B:1)[448B,512r:2) 0@224r 1@352r 2@448B-phi weight:2.985075e-03 w=2.985075e-03
AllocationOrder(Ac) = [ $a ] (sub-class)
assigning %101 to $a: ALSB [224r,336B:0)[352r,448B:1)[448B,512r:2) 0@224r 1@352r 2@448B-phi
selectOrSplit Ac:%102 [240r,336B:0)[368r,448B:1)[448B,544r:2) 0@240r 1@368r 2@448B-phi weight:2.985075e-03 w=2.985075e-03
RS_Assign Cascade 0
wait for second round
queuing new interval: %102 [240r,336B:0)[368r,448B:1)[448B,544r:2) 0@240r 1@368r 2@448B-phi weight:2.985075e-03
selectOrSplit GPR:%103 [608r,720B:0)[736r,832B:1)[832B,880r:2) 0@608r 1@736r 2@832B-phi weight:3.058104e-03 w=3.058104e-03
assigning %103 to $a: ALSB [608r,720B:0)[736r,832B:1)[832B,880r:2) 0@608r 1@736r 2@832B-phi
selectOrSplit GPR:%104 [624r,720B:0)[752r,832B:1)[832B,896r:2) 0@624r 1@752r 2@832B-phi weight:3.134796e-03 w=3.134796e-03
assigning %104 to $x: XLSB [624r,720B:0)[752r,832B:1)[832B,896r:2) 0@624r 1@752r 2@832B-phi
selectOrSplit Ac:%82 [1008r,1136r:0)[1136r,1200r:1) 0@1008r 1@1136r weight:8.445946e-03 w=8.445946e-03
assigning %82 to $a: ALSB [1008r,1136r:0)[1136r,1200r:1) 0@1008r 1@1136r
selectOrSplit Cc:%86 [1088r,1136r:2)[1136r,1224r:0)[1224r,1224d:1) 0@1136r 1@1224r 2@1088r weight:9.310987e-03 w=9.310987e-03
AllocationOrder(Anyi1) = [ $c $alsb $xlsb $ylsb $rc2lsb $rc3lsb $rc4lsb $rc5lsb $rc6lsb $rc7lsb $rc8lsb $rc9lsb $rc10lsb $rc11lsb $rc12lsb $rc13lsb $rc14lsb $rc15lsb $rc16lsb $rc17lsb $rc18lsb $rc19lsb $rc20lsb $rc21lsb $rc22lsb $rc23lsb $rc24lsb $rc25lsb $rc26lsb $rc27lsb $v $rc30lsb $rc31lsb $rc32lsb $rc33lsb $rc34lsb $rc35lsb $rc36lsb $rc37lsb $rc38lsb $rc39lsb $rc40lsb $rc41lsb $rc42lsb $rc43lsb $rc44lsb $rc45lsb $rc46lsb $rc47lsb $rc48lsb $rc49lsb $rc50lsb $rc51lsb $rc52lsb $rc53lsb $rc54lsb $rc55lsb $rc56lsb $rc57lsb $rc58lsb $rc59lsb $rc60lsb $rc61lsb $rc62lsb $rc63lsb $rc64lsb $rc65lsb $rc66lsb $rc67lsb $rc68lsb $rc69lsb $rc70lsb $rc71lsb $rc72lsb $rc73lsb $rc74lsb $rc75lsb $rc76lsb $rc77lsb $rc78lsb $rc79lsb $rc80lsb $rc81lsb $rc82lsb $rc83lsb $rc84lsb $rc85lsb $rc86lsb $rc87lsb $rc88lsb $rc89lsb $rc90lsb $rc91lsb $rc92lsb $rc93lsb $rc94lsb $rc95lsb $rc96lsb $rc97lsb $rc98lsb $rc99lsb $rc100lsb $rc101lsb $rc102lsb $rc103lsb $rc104lsb $rc105lsb $rc106lsb $rc107lsb $rc108lsb $rc109lsb $rc110lsb $rc111lsb $rc112lsb $rc113lsb $rc114lsb $rc115lsb $rc116lsb $rc117lsb $rc118lsb $rc119lsb $rc120lsb $rc121lsb $rc122lsb $rc123lsb $rc124lsb $rc125lsb $rc126lsb $rc127lsb $rc128lsb $rc129lsb $rc130lsb $rc131lsb $rc132lsb $rc133lsb $rc134lsb $rc135lsb $rc136lsb $rc137lsb $rc138lsb $rc139lsb $rc140lsb $rc141lsb $rc142lsb $rc143lsb $rc144lsb $rc145lsb $rc146lsb $rc147lsb $rc148lsb $rc149lsb $rc150lsb $rc151lsb $rc152lsb $rc153lsb $rc154lsb $rc155lsb $rc156lsb $rc157lsb $rc158lsb $rc159lsb $rc160lsb $rc161lsb $rc162lsb $rc163lsb $rc164lsb $rc165lsb $rc166lsb $rc167lsb $rc168lsb $rc169lsb $rc170lsb $rc171lsb $rc172lsb $rc173lsb $rc174lsb $rc175lsb $rc176lsb $rc177lsb $rc178lsb $rc179lsb $rc180lsb $rc181lsb $rc182lsb $rc183lsb $rc184lsb $rc185lsb $rc186lsb $rc187lsb $rc188lsb $rc189lsb $rc190lsb $rc191lsb $rc192lsb $rc193lsb $rc194lsb $rc195lsb $rc196lsb $rc197lsb $rc198lsb $rc199lsb $rc200lsb $rc201lsb $rc202lsb $rc203lsb $rc204lsb $rc205lsb $rc206lsb $rc207lsb $rc208lsb $rc209lsb $rc210lsb $rc211lsb $rc212lsb $rc213lsb $rc214lsb $rc215lsb $rc216lsb $rc217lsb $rc218lsb $rc219lsb $rc220lsb $rc221lsb $rc222lsb $rc223lsb $rc224lsb $rc225lsb $rc226lsb $rc227lsb $rc228lsb $rc229lsb $rc230lsb $rc231lsb $rc232lsb $rc233lsb $rc234lsb $rc235lsb $rc236lsb $rc237lsb $rc238lsb $rc239lsb $rc240lsb $rc241lsb $rc242lsb $rc243lsb $rc244lsb $rc245lsb $rc246lsb $rc247lsb $rc248lsb $rc249lsb $rc250lsb $rc251lsb $rc252lsb $rc253lsb ]
AllocationOrder(Cc) = [ $c ] (sub-class)
assigning %86 to $c: C [1088r,1136r:2)[1136r,1224r:0)[1224r,1224d:1) 0@1136r 1@1224r 2@1088r
selectOrSplit Cc:%98 [176r,176d:0) 0@176r weight:INF w=INF
assigning %98 to $c: C [176r,176d:0) 0@176r
selectOrSplit Cc:%92 [560r,560d:0) 0@560r weight:INF w=INF
assigning %92 to $c: C [560r,560d:0) 0@560r
selectOrSplit Yc:%89 [992r,1008r:0) 0@992r weight:INF w=INF
assigning %89 to $y: YLSB [992r,1008r:0) 0@992r
selectOrSplit Imag16:%34 [1040r,1216r:0)[1216r,1248r:1) 0@1040r 1@1216r L0000000000000002 [1040r,1248r:0) 0@1040r L0000000000000020 [1216r,1248r:0) 0@1216r weight:6.578947e-03 w=6.578947e-03
assigning %34 to $rs1: RC2LSB [1040r,1248r:0) 0@1040r RC3LSB [1216r,1248r:0) 0@1216r
selectOrSplit Vc:%88 [1136r,1136d:0) 0@1136r weight:INF w=INF
AllocationOrder(Vc) = [ $v ] (sub-class)
assigning %88 to $v: V [1136r,1136d:0) 0@1136r
selectOrSplit Imag16:%14 [1200r,1232r:0)[1232r,1272r:1) 0@1200r 1@1232r L0000000000000002 [1200r,1272r:0) 0@1200r L0000000000000020 [1232r,1272r:0) 0@1232r weight:8.474576e-03 w=8.474576e-03
assigning %14 to $rs2: RC4LSB [1200r,1272r:0) 0@1200r RC5LSB [1232r,1272r:0) 0@1232r
selectOrSplit Ac:%85 [1208r,1224r:0)[1224r,1232r:1) 0@1208r 1@1224r weight:1.179245e-02 w=1.179245e-02
assigning %85 to $a: ALSB [1208r,1224r:0)[1224r,1232r:1) 0@1208r 1@1224r
selectOrSplit Vc:%87 [1224r,1224d:0) 0@1224r weight:INF w=INF
assigning %87 to $v: V [1224r,1224d:0) 0@1224r
selectOrSplit Yc:%33 [1240r,1248r:0) 0@1240r weight:INF w=INF
assigning %33 to $y: YLSB [1240r,1248r:0) 0@1240r
selectOrSplit Ac:%28 [1248r,1264r:0) 0@1248r weight:INF w=INF
assigning %28 to $a: ALSB [1248r,1264r:0) 0@1248r
selectOrSplit Ac:%31 [1272r,1280r:0) 0@1272r weight:INF w=INF
assigning %31 to $a: ALSB [1272r,1280r:0) 0@1272r
selectOrSplit Yc:%53 [528r,1272r:0) 0@528r weight:1.748252e-03 w=1.748252e-03
RS_Split Cascade 0
Analyze counted 4 instrs in 2 blocks, through 2 blocks.
Compact region bundles, v=2, none.
Cost of isolating all blocks = 2.0
$y static = 1.0, v=2, total = 2.0 with bundles EB#3.
enterIntvBefore 528r: not live
leaveIntvAfter 544r: valno 0
useIntv [528B;544r): [528B;544r):1
enterIntvBefore 1208r: valno 0
leaveIntvAfter 1272r: not live
useIntv [1204r;1280B): [528B;544r):1 [1204r;1280B):2
Removing 0 back-copies.
blit [528r,1272r:0): [528r;544r)=1(%106)(recalc) [544r;1204r)=0(%105)(recalc) [1204r;1272r)=2(%107)(recalc)
rewr %bb.3 528r:1 %106:yc = LDImm 1
rewr %bb.3 544B:1 STYIndir %102:ac, %4:imag16, %106:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
rewr %bb.6 1272B:2 %31:ac = LDYIndir %14:imag16, %107:yc :: (load 1 from %ir.vfn3 + 1)
rewr %bb.6 1208B:2 %85:ac = LDYIndir %4:imag16, %107:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
All defs dead: dead %105:yc = LDImm 1
Deleting dead def 536r dead %105:yc = LDImm 1
Inflated %105 to Anyi8
not queueing unused %105 EMPTY weight:INF
queuing new interval: %106 [528r,544r:0) 0@528r weight:INF
queuing new interval: %107 [1204r,1272r:0) 0@1204r weight:3.205128e-03
selectOrSplit Yc:%107 [1204r,1272r:0) 0@1204r weight:3.205128e-03 w=3.205128e-03
RS_Assign Cascade 0
wait for second round
queuing new interval: %107 [1204r,1272r:0) 0@1204r weight:3.205128e-03
selectOrSplit Yc:%106 [528r,544r:0) 0@528r weight:INF w=INF
assigning %106 to $y: YLSB [528r,544r:0) 0@528r
selectOrSplit GPR:%1 [16r,560r:0) 0@16r weight:3.209746e-03 w=3.209746e-03
hints: $a
RS_Split Cascade 0
Analyze counted 3 instrs in 2 blocks, through 2 blocks.
Compact region bundles, v=2, none.
Cost of isolating all blocks = 2.0
$a static = 2.0 worse than no bundles
$x static = 1.0, v=2, total = 1.0 with bundles EB#1 EB#2.
$y static = 2.0 worse than $x
Best split candidate of vreg %1 may not cause bad eviction chain
Split for $x in 2 bundles, intv 1.
splitAroundRegion with 2 globals.
%bb.0 [0B;208B), uses 16r-176r, reg-out 1, enter after 128d, defined in block, interference overlaps uses.
selectIntv 1 -> 1
enterIntvAfter 128d: valno 0
useIntv [136r;208B): [136r;208B):1
enterIntvBefore 16r: not live
useIntv [16B;136r): [16B;136r):2 [136r;208B):1
%bb.3 [448B;592B), uses 560r-560r, reg-in 1, leave before invalid, killed in block before interference.
selectIntv 2 -> 1
useIntv [448B;560r): [16B;136r):2 [136r;208B):1 [448B;560r):1
%bb.1 [208B;336B) intf invalid-invalid, live-through 1 -> 1, straight through.
selectIntv 1 -> 1
useIntv [208B;336B): [16B;136r):2 [136r;336B):1 [448B;560r):1
%bb.2 [336B;448B) intf invalid-invalid, live-through 1 -> 1, straight through.
selectIntv 1 -> 1
useIntv [336B;448B): [16B;136r):2 [136r;560r):1
Removing 0 back-copies.
blit [16r,560r:0): [16r;136r)=2(%110):0 [136r;560r)=1(%109):0
rewr %bb.0 16r:2 %110:gpr = COPY $a
rewr %bb.0 176B:1 dead %98:cc = CMPImmTerm %109:gpr, 0, implicit-def dead $nz, implicit-def $z
rewr %bb.3 560B:1 dead %92:cc = CMPImmTerm %109:gpr, 0, implicit-def dead $nz, implicit-def $z
rewr %bb.0 136B:2 %109:gpr = COPY %110:gpr
Inflated %108 to Anyi8
Inflated %110 to Anyi8
Main interval covers the same 4 blocks as original.
not queueing unused %108 EMPTY weight:INF
queuing new interval: %109 [136r,560r:0) 0@136r weight:3.677184e-03
queuing new interval: %110 [16r,136r:0) 0@16r weight:3.884615e-03
selectOrSplit Anyi8:%110 [16r,136r:0) 0@16r weight:3.884615e-03 w=3.884615e-03
hints: $a
missed hint $a
assigning %110 to $rc30: RC30LSB [16r,136r:0) 0@16r
selectOrSplit GPR:%109 [136r,560r:0) 0@136r weight:3.677184e-03 w=3.677184e-03
assigning %109 to $x: XLSB [136r,560r:0) 0@136r
selectOrSplit Yc:%2 [48r,512r:0) 0@48r weight:1.736111e-03 w=1.736111e-03
RS_Split Cascade 0
Analyze counted 3 instrs in 2 blocks, through 2 blocks.
Compact region bundles, v=2, none.
Cost of isolating all blocks = 2.0
$y static = 1.0, v=2 no bundles.
enterIntvBefore 48r: not live
leaveIntvAfter 112r: valno 0
useIntv [48B;112r): [48B;112r):1
enterIntvBefore 512r: valno 0
leaveIntvAfter 512r: not live
useIntv [504r;528B): [48B;112r):1 [504r;528B):2
Removing 0 back-copies.
blit [48r,512r:0): [48r;112r)=1(%112)(recalc) [112r;504r)=0(%111)(recalc) [504r;512r)=2(%113)(recalc)
rewr %bb.0 48r:1 %112:yc = LDImm 0
rewr %bb.0 112B:1 $x = COPY %112:yc
rewr %bb.3 512B:2 STYIndir %101:ac, %4:imag16, %113:yc :: (store 1 into %ir.0, !tbaa !2)
All defs dead: dead %111:yc = LDImm 0
Deleting dead def 72r dead %111:yc = LDImm 0
Inflated %111 to Anyi8
Inflated %112 to GPR
not queueing unused %111 EMPTY weight:INF
queuing new interval: %112 [48r,112r:0) 0@48r weight:2.176724e-03
queuing new interval: %113 [504r,512r:0) 0@504r weight:INF
selectOrSplit GPR:%112 [48r,112r:0) 0@48r weight:2.176724e-03 w=2.176724e-03
hints: $x
assigning %112 to $x: XLSB [48r,112r:0) 0@48r
selectOrSplit Yc:%113 [504r,512r:0) 0@504r weight:INF w=INF
assigning %113 to $y: YLSB [504r,512r:0) 0@504r
selectOrSplit Ac:%102 [240r,336B:0)[368r,448B:1)[448B,544r:2) 0@240r 1@368r 2@448B-phi weight:2.985075e-03 w=2.985075e-03
RS_Split Cascade 0
Analyze counted 3 instrs in 3 blocks, through 0 blocks.
Cost of isolating all blocks = 2.0
$a no positive bundles
enterIntvBefore 240r: not live
leaveIntvAfter 240r: valno 0
useIntv [240B;248r): [240B;248r):1
enterIntvBefore 368r: not live
leaveIntvAfter 368r: valno 1
useIntv [368B;376r): [240B;248r):1 [368B;376r):2
enterIntvBefore 544r: valno 2
leaveIntvAfter 544r: not live
useIntv [540r;560B): [240B;248r):1 [368B;376r):2 [540r;560B):3
Direct complement def at 448B
Removing 0 back-copies.
blit [240r,336B:0): [240r;248r)=1(%115)(recalc) [248r;336B)=0(%114)(recalc)
blit [368r,448B:1): [368r;376r)=2(%116)(recalc) [376r;448B)=0(%114)(recalc)
blit [448B,544r:2): [448B;540r)=0(%114):2 [540r;544r)=3(%117):0
rewr %bb.2 368r:2 %116:ac = LDImm target-flags(hi) @_ZTV4SubA + 4
rewr %bb.1 240r:1 %115:ac = LDImm target-flags(hi) @_ZTV4SubB + 4
rewr %bb.3 544B:3 STYIndir %117:ac, %4:imag16, %106:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
rewr %bb.3 540B:0 %117:ac = COPY %114:ac
All defs dead: dead %115:ac = LDImm target-flags(hi) @_ZTV4SubB + 4
All defs dead: dead %116:ac = LDImm target-flags(hi) @_ZTV4SubA + 4
Deleting dead def 368r dead %116:ac = LDImm target-flags(hi) @_ZTV4SubA + 4
Deleting dead def 240r dead %115:ac = LDImm target-flags(hi) @_ZTV4SubB + 4
Inflated %114 to GPR
Inflated %115 to Anyi8
Inflated %116 to Anyi8
queuing new interval: %114 [248r,336B:0)[376r,448B:1)[448B,540r:2) 0@248r 1@376r 2@448B-phi weight:3.107692e-03
not queueing unused %115 EMPTY weight:INF
not queueing unused %116 EMPTY weight:INF
queuing new interval: %117 [540r,544r:0) 0@540r weight:INF
selectOrSplit GPR:%114 [248r,336B:0)[376r,448B:1)[448B,540r:2) 0@248r 1@376r 2@448B-phi weight:3.107692e-03 w=3.107692e-03
RS_Spill Cascade 0
should evict: %101 [224r,336B:0)[352r,448B:1)[448B,512r:2) 0@224r 1@352r 2@448B-phi weight:2.985075e-03 w= 2.985075e-03
evicting $a interference: Cascade 1
unassigning %101 from $a: ALSB
assigning %114 to $a: ALSB [248r,336B:0)[376r,448B:1)[448B,540r:2) 0@248r 1@376r 2@448B-phi
queuing new interval: %101 [224r,336B:0)[352r,448B:1)[448B,512r:2) 0@224r 1@352r 2@448B-phi weight:2.985075e-03
selectOrSplit Ac:%101 [224r,336B:0)[352r,448B:1)[448B,512r:2) 0@224r 1@352r 2@448B-phi weight:2.985075e-03 w=2.985075e-03
RS_Assign Cascade 1
wait for second round
queuing new interval: %101 [224r,336B:0)[352r,448B:1)[448B,512r:2) 0@224r 1@352r 2@448B-phi weight:2.985075e-03
selectOrSplit Ac:%117 [540r,544r:0) 0@540r weight:INF w=INF
hints: $a
assigning %117 to $a: ALSB [540r,544r:0) 0@540r
selectOrSplit Ac:%101 [224r,336B:0)[352r,448B:1)[448B,512r:2) 0@224r 1@352r 2@448B-phi weight:2.985075e-03 w=2.985075e-03
RS_Split Cascade 1
Analyze counted 3 instrs in 3 blocks, through 0 blocks.
Cost of isolating all blocks = 2.0
$a no positive bundles
enterIntvBefore 224r: not live
leaveIntvAfter 224r: valno 0
useIntv [224B;232r): [224B;232r):1
enterIntvBefore 352r: not live
leaveIntvAfter 352r: valno 1
useIntv [352B;360r): [224B;232r):1 [352B;360r):2
enterIntvBefore 512r: valno 2
leaveIntvAfter 512r: not live
useIntv [508r;528B): [224B;232r):1 [352B;360r):2 [508r;528B):3
Direct complement def at 448B
Removing 0 back-copies.
blit [224r,336B:0): [224r;232r)=1(%121)(recalc) [232r;336B)=0(%120)(recalc)
blit [352r,448B:1): [352r;360r)=2(%122)(recalc) [360r;448B)=0(%120)(recalc)
blit [448B,512r:2): [448B;508r)=0(%120):2 [508r;512r)=3(%123):0
rewr %bb.2 352r:2 %122:ac = LDImm target-flags(lo) @_ZTV4SubA + 4
rewr %bb.1 224r:1 %121:ac = LDImm target-flags(lo) @_ZTV4SubB + 4
rewr %bb.3 512B:3 STYIndir %123:ac, %4:imag16, %113:yc :: (store 1 into %ir.0, !tbaa !2)
rewr %bb.3 508B:0 %123:ac = COPY %120:ac
All defs dead: dead %121:ac = LDImm target-flags(lo) @_ZTV4SubB + 4
All defs dead: dead %122:ac = LDImm target-flags(lo) @_ZTV4SubA + 4
Deleting dead def 352r dead %122:ac = LDImm target-flags(lo) @_ZTV4SubA + 4
Deleting dead def 224r dead %121:ac = LDImm target-flags(lo) @_ZTV4SubB + 4
Inflated %120 to GPR
Inflated %121 to Anyi8
Inflated %122 to Anyi8
queuing new interval: %120 [232r,336B:0)[360r,448B:1)[448B,508r:2) 0@232r 1@360r 2@448B-phi weight:3.107692e-03
not queueing unused %121 EMPTY weight:INF
not queueing unused %122 EMPTY weight:INF
queuing new interval: %123 [508r,512r:0) 0@508r weight:INF
selectOrSplit GPR:%120 [232r,336B:0)[360r,448B:1)[448B,508r:2) 0@232r 1@360r 2@448B-phi weight:3.107692e-03 w=3.107692e-03
RS_Spill Cascade 0
Inline spilling GPR:%120 [232r,336B:0)[360r,448B:1)[448B,508r:2) 0@232r 1@360r 2@448B-phi weight:3.107692e-03
From original %101
also spill snippet %123 [508r,512r:0) 0@508r weight:INF
cannot remat for 512e STYIndir %123:ac, %4:imag16, %113:yc :: (store 1 into %ir.0, !tbaa !2)
Merged spilled regs: SS#0 [232r,336B:0)[360r,512r:0) 0@x weight:0.000000e+00
spillAroundUses %120
rewrite: 360r %126:gpr = LDImm target-flags(lo) @_ZTV4SubA + 4
Inserted stack slot load/store:
early-clobber %127:imag16, early-clobber %128:yc = STStk killed %126:gpr, %stack.0, 0 :: (store 1 into %stack.0)
spill: 364r dead early-clobber %127:imag16, dead early-clobber %128:yc = STStk killed %126:gpr, %stack.0, 0 :: (store 1 into %stack.0)
rewrite: 232r %129:gpr = LDImm target-flags(lo) @_ZTV4SubB + 4
Inserted stack slot load/store:
early-clobber %130:imag16, early-clobber %131:yc = STStk killed %129:gpr, %stack.0, 0 :: (store 1 into %stack.0)
spill: 236r dead early-clobber %130:imag16, dead early-clobber %131:yc = STStk killed %129:gpr, %stack.0, 0 :: (store 1 into %stack.0)
spillAroundUses %123
Inserted stack slot load/store:
%132:ac, early-clobber %133:imag16, early-clobber %134:yc = LDStk %stack.0, 0 :: (load 1 from %stack.0)
*** Renumbered SlotIndexes 508-524 ***
reload: 516r %132:ac, early-clobber %133:imag16, early-clobber %134:yc = LDStk %stack.0, 0 :: (load 1 from %stack.0)
rewrite: 524r STYIndir killed %132:ac, %4:imag16, %113:yc :: (store 1 into %ir.0, !tbaa !2)
queuing new interval: %126 [360r,364r:0) 0@360r weight:INF
queuing new interval: %127 [364e,364d:0) 0@364e weight:INF
queuing new interval: %128 [364e,364d:0) 0@364e weight:INF
queuing new interval: %129 [232r,236r:0) 0@232r weight:INF
queuing new interval: %130 [236e,236d:0) 0@236e weight:INF
queuing new interval: %131 [236e,236d:0) 0@236e weight:INF
queuing new interval: %132 [516r,524r:0) 0@516r weight:INF
queuing new interval: %133 [516e,516d:0) 0@516e weight:INF
queuing new interval: %134 [516e,516d:0) 0@516e weight:INF
selectOrSplit Ac:%132 [516r,524r:0) 0@516r weight:INF w=INF
RS_Done Cascade 0
evicting $a interference: Cascade 2
unassigning %114 from $a: ALSB
assigning %132 to $a: ALSB [516r,524r:0) 0@516r
queuing new interval: %114 [248r,336B:0)[376r,448B:1)[448B,540r:2) 0@248r 1@376r 2@448B-phi weight:3.107692e-03
selectOrSplit GPR:%114 [248r,336B:0)[376r,448B:1)[448B,540r:2) 0@248r 1@376r 2@448B-phi weight:3.107692e-03 w=3.107692e-03
hints: $a
RS_Spill Cascade 2
Inline spilling GPR:%114 [248r,336B:0)[376r,448B:1)[448B,540r:2) 0@248r 1@376r 2@448B-phi weight:3.107692e-03
From original %102
also spill snippet %117 [540r,544r:0) 0@540r weight:INF
cannot remat for 544e STYIndir %117:ac, %4:imag16, %106:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
Merged spilled regs: SS#1 [248r,336B:0)[376r,544r:0) 0@x weight:0.000000e+00
spillAroundUses %114
rewrite: 376r %135:gpr = LDImm target-flags(hi) @_ZTV4SubA + 4
Inserted stack slot load/store:
early-clobber %136:imag16, early-clobber %137:yc = STStk killed %135:gpr, %stack.1, 0 :: (store 1 into %stack.1)
spill: 380r dead early-clobber %136:imag16, dead early-clobber %137:yc = STStk killed %135:gpr, %stack.1, 0 :: (store 1 into %stack.1)
rewrite: 248r %138:gpr = LDImm target-flags(hi) @_ZTV4SubB + 4
Inserted stack slot load/store:
early-clobber %139:imag16, early-clobber %140:yc = STStk killed %138:gpr, %stack.1, 0 :: (store 1 into %stack.1)
spill: 252r dead early-clobber %139:imag16, dead early-clobber %140:yc = STStk killed %138:gpr, %stack.1, 0 :: (store 1 into %stack.1)
spillAroundUses %117
Inserted stack slot load/store:
%141:ac, early-clobber %142:imag16, early-clobber %143:yc = LDStk %stack.1, 0 :: (load 1 from %stack.1)
*** Renumbered SlotIndexes 540-556 ***
reload: 548r %141:ac, early-clobber %142:imag16, early-clobber %143:yc = LDStk %stack.1, 0 :: (load 1 from %stack.1)
rewrite: 556r STYIndir killed %141:ac, %4:imag16, %106:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
unassigning %117 from $a: ALSB
queuing new interval: %135 [376r,380r:0) 0@376r weight:INF
queuing new interval: %136 [380e,380d:0) 0@380e weight:INF
queuing new interval: %137 [380e,380d:0) 0@380e weight:INF
queuing new interval: %138 [248r,252r:0) 0@248r weight:INF
queuing new interval: %139 [252e,252d:0) 0@252e weight:INF
queuing new interval: %140 [252e,252d:0) 0@252e weight:INF
queuing new interval: %141 [548r,556r:0) 0@548r weight:INF
queuing new interval: %142 [548e,548d:0) 0@548e weight:INF
queuing new interval: %143 [548e,548d:0) 0@548e weight:INF
selectOrSplit Ac:%141 [548r,556r:0) 0@548r weight:INF w=INF
assigning %141 to $a: ALSB [548r,556r:0) 0@548r
selectOrSplit GPR:%126 [360r,364r:0) 0@360r weight:INF w=INF
assigning %126 to $a: ALSB [360r,364r:0) 0@360r
selectOrSplit GPR:%129 [232r,236r:0) 0@232r weight:INF w=INF
assigning %129 to $a: ALSB [232r,236r:0) 0@232r
selectOrSplit GPR:%135 [376r,380r:0) 0@376r weight:INF w=INF
assigning %135 to $a: ALSB [376r,380r:0) 0@376r
selectOrSplit GPR:%138 [248r,252r:0) 0@248r weight:INF w=INF
assigning %138 to $a: ALSB [248r,252r:0) 0@248r
selectOrSplit Imag16:%127 [364e,364d:0) 0@364e weight:INF w=INF
assigning %127 to $rs1: RC2LSB [364e,364d:0) 0@364e RC3LSB [364e,364d:0) 0@364e
selectOrSplit Yc:%128 [364e,364d:0) 0@364e weight:INF w=INF
assigning %128 to $y: YLSB [364e,364d:0) 0@364e
selectOrSplit Imag16:%130 [236e,236d:0) 0@236e weight:INF w=INF
assigning %130 to $rs1: RC2LSB [236e,236d:0) 0@236e RC3LSB [236e,236d:0) 0@236e
selectOrSplit Yc:%131 [236e,236d:0) 0@236e weight:INF w=INF
assigning %131 to $y: YLSB [236e,236d:0) 0@236e
selectOrSplit Imag16:%133 [516e,516d:0) 0@516e weight:INF w=INF
assigning %133 to $rs1: RC2LSB [516e,516d:0) 0@516e RC3LSB [516e,516d:0) 0@516e
selectOrSplit Yc:%134 [516e,516d:0) 0@516e weight:INF w=INF
RS_Done Cascade 0
Try last chance recoloring for %134 [516e,516d:0) 0@516e weight:INF
Try to assign: %134 [516e,516d:0) 0@516e weight:INF to $y
unassigning %113 from $y: YLSB
assigning %134 to $y: YLSB [516e,516d:0) 0@516e
Try to recolor: %113 [504r,524r:0) 0@504r weight:INF
RS_Assign Cascade 0
wait for second round
Fail to assign: %134 [516e,516d:0) 0@516e weight:INF to $y
unassigning %134 from $y: YLSB
assigning %113 to $y: YLSB [504r,524r:0) 0@504r
error: ran out of registers during register allocation
selectOrSplit Imag16:%136 [380e,380d:0) 0@380e weight:INF w=INF
assigning %136 to $rs1: RC2LSB [380e,380d:0) 0@380e RC3LSB [380e,380d:0) 0@380e
selectOrSplit Yc:%137 [380e,380d:0) 0@380e weight:INF w=INF
assigning %137 to $y: YLSB [380e,380d:0) 0@380e
selectOrSplit Imag16:%139 [252e,252d:0) 0@252e weight:INF w=INF
assigning %139 to $rs1: RC2LSB [252e,252d:0) 0@252e RC3LSB [252e,252d:0) 0@252e
selectOrSplit Yc:%140 [252e,252d:0) 0@252e weight:INF w=INF
assigning %140 to $y: YLSB [252e,252d:0) 0@252e
selectOrSplit Imag16:%142 [548e,548d:0) 0@548e weight:INF w=INF
assigning %142 to $rs1: RC2LSB [548e,548d:0) 0@548e RC3LSB [548e,548d:0) 0@548e
selectOrSplit Yc:%143 [548e,548d:0) 0@548e weight:INF w=INF
RS_Done Cascade 0
Try last chance recoloring for %143 [548e,548d:0) 0@548e weight:INF
Try to assign: %143 [548e,548d:0) 0@548e weight:INF to $y
unassigning %106 from $y: YLSB
assigning %143 to $y: YLSB [548e,548d:0) 0@548e
Try to recolor: %106 [528r,556r:0) 0@528r weight:INF
RS_Assign Cascade 0
wait for second round
Fail to assign: %143 [548e,548d:0) 0@548e weight:INF to $y
unassigning %143 from $y: YLSB
assigning %106 to $y: YLSB [528r,556r:0) 0@528r
error: ran out of registers during register allocation
Dropping unused %123 EMPTY weight:INF
selectOrSplit Yc:%107 [1204r,1272r:0) 0@1204r weight:3.205128e-03 w=3.205128e-03
RS_Split Cascade 0
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
tryLocalSplit: 1204r 1208r 1272r
$y 1204r-1208r I=0.000000e+00 w=7.142857e-03 (best) extend
$y 1204r-1272r I=INF all
Best local split range: 1204r-1208r, 6.999861e-03, 2 instrs
enterIntvBefore 1204r: not live
leaveIntvAfter 1208r: valno 0
useIntv [1204B;1212r): [1204B;1212r):1
blit [1204r,1272r:0): [1204r;1212r)=1(%145)(recalc) [1212r;1272r)=0(%144)(recalc)
rewr %bb.6 1204r:1 %145:yc = LDImm 1
rewr %bb.6 1272B:0 %31:ac = LDYIndir %14:imag16, %144:yc :: (load 1 from %ir.vfn3 + 1)
rewr %bb.6 1208B:1 %85:ac = LDYIndir %4:imag16, %145:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
Tagging non-progress ranges: %145
queuing new interval: %144 [1212r,1272r:0) 0@1212r weight:2.173913e-03
queuing new interval: %145 [1204r,1208r:0) 0@1204r weight:INF
selectOrSplit Yc:%144 [1212r,1272r:0) 0@1212r weight:2.173913e-03 w=2.173913e-03
RS_Assign Cascade 0
wait for second round
queuing new interval: %144 [1212r,1272r:0) 0@1212r weight:2.173913e-03
selectOrSplit Yc:%145 [1204r,1208r:0) 0@1204r weight:INF w=INF
assigning %145 to $y: YLSB [1204r,1208r:0) 0@1204r
selectOrSplit Yc:%144 [1212r,1272r:0) 0@1212r weight:2.173913e-03 w=2.173913e-03
RS_Split Cascade 0
Analyze counted 2 instrs in 1 blocks, through 0 blocks.
Split around 2 individual instrs.
AllocationOrder(Anyi8) = [ $a $x $y $rc2 $rc3 $rc4 $rc5 $rc6 $rc7 $rc8 $rc9 $rc10 $rc11 $rc12 $rc13 $rc14 $rc15 $rc16 $rc17 $rc18 $rc19 $rc20 $rc21 $rc22 $rc23 $rc24 $rc25 $rc26 $rc27 $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 $rc63 $rc64 $rc65 $rc66 $rc67 $rc68 $rc69 $rc70 $rc71 $rc72 $rc73 $rc74 $rc75 $rc76 $rc77 $rc78 $rc79 $rc80 $rc81 $rc82 $rc83 $rc84 $rc85 $rc86 $rc87 $rc88 $rc89 $rc90 $rc91 $rc92 $rc93 $rc94 $rc95 $rc96 $rc97 $rc98 $rc99 $rc100 $rc101 $rc102 $rc103 $rc104 $rc105 $rc106 $rc107 $rc108 $rc109 $rc110 $rc111 $rc112 $rc113 $rc114 $rc115 $rc116 $rc117 $rc118 $rc119 $rc120 $rc121 $rc122 $rc123 $rc124 $rc125 $rc126 $rc127 $rc128 $rc129 $rc130 $rc131 $rc132 $rc133 $rc134 $rc135 $rc136 $rc137 $rc138 $rc139 $rc140 $rc141 $rc142 $rc143 $rc144 $rc145 $rc146 $rc147 $rc148 $rc149 $rc150 $rc151 $rc152 $rc153 $rc154 $rc155 $rc156 $rc157 $rc158 $rc159 $rc160 $rc161 $rc162 $rc163 $rc164 $rc165 $rc166 $rc167 $rc168 $rc169 $rc170 $rc171 $rc172 $rc173 $rc174 $rc175 $rc176 $rc177 $rc178 $rc179 $rc180 $rc181 $rc182 $rc183 $rc184 $rc185 $rc186 $rc187 $rc188 $rc189 $rc190 $rc191 $rc192 $rc193 $rc194 $rc195 $rc196 $rc197 $rc198 $rc199 $rc200 $rc201 $rc202 $rc203 $rc204 $rc205 $rc206 $rc207 $rc208 $rc209 $rc210 $rc211 $rc212 $rc213 $rc214 $rc215 $rc216 $rc217 $rc218 $rc219 $rc220 $rc221 $rc222 $rc223 $rc224 $rc225 $rc226 $rc227 $rc228 $rc229 $rc230 $rc231 $rc232 $rc233 $rc234 $rc235 $rc236 $rc237 $rc238 $rc239 $rc240 $rc241 $rc242 $rc243 $rc244 $rc245 $rc246 $rc247 $rc248 $rc249 $rc250 $rc251 $rc252 $rc253 ]
AllocationOrder(GPR) = [ $a $x $y ] (sub-class)
enterIntvBefore 1212r: not live
leaveIntvAfter 1212r: valno 0
*** Renumbered SlotIndexes 1212-1292 ***
useIntv [1212B;1220r): [1212B;1220r):1
AllocationOrder(Yc) = [ $y ] (sub-class)
enterIntvBefore 1284r: valno 0
leaveIntvAfter 1284r: not live
useIntv [1280r;1292B): [1212B;1220r):1 [1280r;1292B):2
Removing 0 back-copies.
blit [1212r,1284r:0): [1212r;1220r)=1(%147)(recalc) [1220r;1280r)=0(%146)(recalc) [1280r;1284r)=2(%148)(recalc)
rewr %bb.6 1212r:1 %147:yc = LDImm 1
rewr %bb.6 1284B:2 %31:ac = LDYIndir %14:imag16, %148:yc :: (load 1 from %ir.vfn3 + 1)
All defs dead: dead %146:yc = LDImm 1
All defs dead: dead %147:yc = LDImm 1
Deleting dead def 1212r dead %147:yc = LDImm 1
Deleting dead def 1220r dead %146:yc = LDImm 1
Inflated %146 to Anyi8
Inflated %147 to Anyi8
not queueing unused %146 EMPTY weight:INF
not queueing unused %147 EMPTY weight:INF
queuing new interval: %148 [1280r,1284r:0) 0@1280r weight:INF
selectOrSplit Yc:%148 [1280r,1284r:0) 0@1280r weight:INF w=INF
assigning %148 to $y: YLSB [1280r,1284r:0) 0@1280r
Trying to reconcile hints for: %4($rs15)
%4($rs15) is recolorable.
Trying to reconcile hints for: %110($rc30)
%110($rc30) is recolorable.
********** REWRITE VIRTUAL REGISTERS **********
********** Function: _Z11testIndCallc
********** REGISTER MAP **********
[%4 -> $rs15] Imag16
[%14 -> $rs2] Imag16
[%27 -> $rs8] Imag16
[%28 -> $a] Ac
[%31 -> $a] Ac
[%33 -> $y] Yc
[%34 -> $rs1] Imag16
[%41 -> $rs8] Imag16
[%82 -> $a] Ac
[%85 -> $a] Ac
[%86 -> $c] Cc
[%87 -> $v] Vc
[%88 -> $v] Vc
[%89 -> $y] Yc
[%92 -> $c] Cc
[%98 -> $c] Cc
[%103 -> $a] GPR
[%104 -> $x] GPR
[%106 -> $y] Yc
[%109 -> $x] GPR
[%110 -> $rc30] Anyi8
[%112 -> $x] GPR
[%113 -> $y] Yc
[%126 -> $a] GPR
[%127 -> $rs1] Imag16
[%128 -> $y] Yc
[%129 -> $a] GPR
[%130 -> $rs1] Imag16
[%131 -> $y] Yc
[%132 -> $a] Ac
[%133 -> $rs1] Imag16
[%134 -> $y] Yc
[%135 -> $a] GPR
[%136 -> $rs1] Imag16
[%137 -> $y] Yc
[%138 -> $a] GPR
[%139 -> $rs1] Imag16
[%140 -> $y] Yc
[%141 -> $a] Ac
[%142 -> $rs1] Imag16
[%143 -> $y] Yc
[%145 -> $y] Yc
[%148 -> $y] Yc
[%101 -> fi#0] Ac
[%102 -> fi#1] Ac
[%114 -> fi#1] GPR
[%120 -> fi#0] GPR
0B bb.0.entry:
successors: %bb.1(0x30000000), %bb.2(0x50000000); %bb.1(37.50%), %bb.2(62.50%)
liveins: $a
16B %110:anyi8 = COPY $a
48B %112:gpr = LDImm 0
64B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
112B $x = COPY killed %112:gpr
120B $a = LDImm 2
128B JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $a, implicit $x, implicit-def $rs1
136B %109:gpr = COPY killed %110:anyi8
144B %4:imag16 = COPY $rs1
160B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
176B dead %98:cc = CMPImmTerm %109:gpr, 0, implicit-def dead $nz, implicit-def $z
192B BR %bb.2, killed $z, 0
> renamable $rc30 = COPY $a
> renamable $x = LDImm 0
> ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
> $x = COPY killed renamable $x
Identity copy: $x = COPY killed renamable $x
deleted.
> $a = LDImm 2
> JSR @_Znwt, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $a, implicit $x, implicit-def $rs1
> renamable $x = COPY killed renamable $rc30
> renamable $rs15 = COPY $rs1
> ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
> dead renamable $c = CMPImmTerm renamable $x, 0, implicit-def dead $nz, implicit-def $z
> BR %bb.2, killed $z, 0
208B bb.1:
; predecessors: %bb.0
successors: %bb.3(0x80000000); %bb.3(100.00%)
liveins: $x, $rs15
232B %129:gpr = LDImm target-flags(lo) @_ZTV4SubB + 4
236B dead early-clobber %130:imag16, dead early-clobber %131:yc = STStk killed %129:gpr, %stack.0, 0 :: (store 1 into %stack.0)
248B %138:gpr = LDImm target-flags(hi) @_ZTV4SubB + 4
252B dead early-clobber %139:imag16, dead early-clobber %140:yc = STStk killed %138:gpr, %stack.1, 0 :: (store 1 into %stack.1)
320B JMP %bb.3
> renamable $a = LDImm target-flags(lo) @_ZTV4SubB + 4
> dead early-clobber renamable $rs1, dead early-clobber renamable $y = STStk killed renamable $a, %stack.0, 0 :: (store 1 into %stack.0)
> renamable $a = LDImm target-flags(hi) @_ZTV4SubB + 4
> dead early-clobber renamable $rs1, dead early-clobber renamable $y = STStk killed renamable $a, %stack.1, 0 :: (store 1 into %stack.1)
> JMP %bb.3
336B bb.2.select.false:
; predecessors: %bb.0
successors: %bb.3(0x80000000); %bb.3(100.00%)
liveins: $x, $rs15
360B %126:gpr = LDImm target-flags(lo) @_ZTV4SubA + 4
364B dead early-clobber %127:imag16, dead early-clobber %128:yc = STStk killed %126:gpr, %stack.0, 0 :: (store 1 into %stack.0)
376B %135:gpr = LDImm target-flags(hi) @_ZTV4SubA + 4
380B dead early-clobber %136:imag16, dead early-clobber %137:yc = STStk killed %135:gpr, %stack.1, 0 :: (store 1 into %stack.1)
> renamable $a = LDImm target-flags(lo) @_ZTV4SubA + 4
> dead early-clobber renamable $rs1, dead early-clobber renamable $y = STStk killed renamable $a, %stack.0, 0 :: (store 1 into %stack.0)
> renamable $a = LDImm target-flags(hi) @_ZTV4SubA + 4
> dead early-clobber renamable $rs1, dead early-clobber renamable $y = STStk killed renamable $a, %stack.1, 0 :: (store 1 into %stack.1)
448B bb.3.select.end:
; predecessors: %bb.2, %bb.1
successors: %bb.4(0x30000000), %bb.5(0x50000000); %bb.4(37.50%), %bb.5(62.50%)
liveins: $x, $rs15
504B %113:yc = LDImm 0
516B %132:ac, dead early-clobber %133:imag16, dead early-clobber %134:yc = LDStk %stack.0, 0 :: (load 1 from %stack.0)
524B STYIndir killed %132:ac, %4:imag16, killed %113:yc :: (store 1 into %ir.0, !tbaa !2)
528B %106:yc = LDImm 1
548B %141:ac, dead early-clobber %142:imag16, dead early-clobber %143:yc = LDStk %stack.1, 0 :: (load 1 from %stack.1)
556B STYIndir killed %141:ac, %4:imag16, killed %106:yc :: (store 1 into %ir.0 + 1, !tbaa !2)
560B dead %92:cc = CMPImmTerm killed %109:gpr, 0, implicit-def dead $nz, implicit-def $z
576B BR %bb.5, killed $z, 0
> renamable $y = LDImm 0
> renamable $a, dead early-clobber renamable $rs1, dead early-clobber renamable $y = LDStk %stack.0, 0 :: (load 1 from %stack.0)
> STYIndir killed renamable $a, renamable $rs15, killed renamable $y :: (store 1 into %ir.0, !tbaa !2)
> renamable $y = LDImm 1
> renamable $a, dead early-clobber renamable $rs1, dead early-clobber renamable $y = LDStk %stack.1, 0 :: (load 1 from %stack.1)
> STYIndir killed renamable $a, renamable $rs15, killed renamable $y :: (store 1 into %ir.0 + 1, !tbaa !2)
> dead renamable $c = CMPImmTerm killed renamable $x, 0, implicit-def dead $nz, implicit-def $z
> BR %bb.5, killed $z, 0
592B bb.4:
; predecessors: %bb.3
successors: %bb.6(0x80000000); %bb.6(100.00%)
liveins: $rs15
608B %103:gpr = LDImm target-flags(lo) @_ZN4SubB2fnEv
624B %104:gpr = LDImm target-flags(hi) @_ZN4SubB2fnEv
704B JMP %bb.6
> renamable $a = LDImm target-flags(lo) @_ZN4SubB2fnEv
> renamable $x = LDImm target-flags(hi) @_ZN4SubB2fnEv
> JMP %bb.6
720B bb.5.select.false9:
; predecessors: %bb.3
successors: %bb.6(0x80000000); %bb.6(100.00%)
liveins: $rs15
736B %103:gpr = LDImm target-flags(lo) @_ZN4SubA2fnEv
752B %104:gpr = LDImm target-flags(hi) @_ZN4SubA2fnEv
> renamable $a = LDImm target-flags(lo) @_ZN4SubA2fnEv
> renamable $x = LDImm target-flags(hi) @_ZN4SubA2fnEv
832B bb.6.select.end8:
; predecessors: %bb.5, %bb.4
liveins: $a, $x, $rs15
880B undef %41.sublo:imag16 = COPY killed %103:gpr
896B %41.subhi:imag16 = COPY killed %104:gpr
912B $rs8 = COPY killed %41:imag16
928B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
944B $rs1 = COPY %4:imag16
960B JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
976B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
992B %89:yc = LDImm 0
1008B %82:ac = LDYIndir %4:imag16, killed %89:yc :: (load 1 from %ir.3, !tbaa !2)
1040B undef %34.sublo:imag16 = COPY %82:ac
1088B %86:cc = LDImm1 0
1136B %82:ac, %86:cc, dead %88:vc = ADCImm killed %82:ac(tied-def 0), 2, killed %86:cc(tied-def 1)
1200B undef %14.sublo:imag16 = COPY killed %82:ac
1204B %145:yc = LDImm 1
1208B %85:ac = LDYIndir %4:imag16, killed %145:yc :: (load 1 from %ir.3 + 1, !tbaa !2)
1228B %34.subhi:imag16 = COPY %85:ac
1236B %85:ac, dead %86:cc, dead %87:vc = ADCImm killed %85:ac(tied-def 0), 0, killed %86:cc(tied-def 1)
1244B %14.subhi:imag16 = COPY killed %85:ac
1252B %33:yc = LDImm 2
1260B %28:ac = LDYIndir killed %34:imag16, killed %33:yc :: (load 1 from %ir.vfn3)
1276B undef %27.sublo:imag16 = COPY killed %28:ac
1280B %148:yc = LDImm 1
1284B %31:ac = LDYIndir killed %14:imag16, killed %148:yc :: (load 1 from %ir.vfn3 + 1)
1292B %27.subhi:imag16 = COPY killed %31:ac
1296B $rs8 = COPY killed %27:imag16
1312B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
1328B $rs1 = COPY killed %4:imag16
1344B JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
1360B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
1376B RTS
> renamable $rc16 = COPY killed renamable $a
> renamable $rc17 = COPY killed renamable $x
> $rs8 = COPY killed renamable $rs8
Identity copy: $rs8 = COPY killed renamable $rs8
deleted.
> ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
> $rs1 = COPY renamable $rs15
> JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
> ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
> renamable $y = LDImm 0
> renamable $a = LDYIndir renamable $rs15, killed renamable $y :: (load 1 from %ir.3, !tbaa !2)
> renamable $rc2 = COPY renamable $a
> renamable $c = LDImm1 0
> renamable $a, renamable $c, dead renamable $v = ADCImm killed renamable $a(tied-def 0), 2, killed renamable $c(tied-def 1)
> renamable $rc4 = COPY killed renamable $a
> renamable $y = LDImm 1
> renamable $a = LDYIndir renamable $rs15, killed renamable $y :: (load 1 from %ir.3 + 1, !tbaa !2)
> renamable $rc3 = COPY renamable $a
> renamable $a, dead renamable $c, dead renamable $v = ADCImm killed renamable $a(tied-def 0), 0, killed renamable $c(tied-def 1)
> renamable $rc5 = COPY killed renamable $a
> renamable $y = LDImm 2
> renamable $a = LDYIndir killed renamable $rs1, killed renamable $y :: (load 1 from %ir.vfn3)
> renamable $rc16 = COPY killed renamable $a
> renamable $y = LDImm 1
> renamable $a = LDYIndir killed renamable $rs2, killed renamable $y :: (load 1 from %ir.vfn3 + 1)
> renamable $rc17 = COPY killed renamable $a
> $rs8 = COPY killed renamable $rs8
Identity copy: $rs8 = COPY killed renamable $rs8
deleted.
> ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
> $rs1 = COPY killed renamable $rs15
> JSR &__call_indir, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs8, implicit $rs1
> ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
> RTS
********** Stack Slot Coloring **********
********** Function: _Z11testIndCallc
Spill slot intervals:
SS#0 [232r,336B:0)[360r,524r:0) 0@x weight:2.000000e+00
SS#1 [248r,336B:0)[376r,556r:0) 0@x weight:2.000000e+00
Color spill slot intervals:
Assigning fi#0 to fi#0
Assigning fi#1 to fi#1
Spill slots after coloring:
SS#0 [232r,336B:0)[360r,524r:0) 0@x weight:2.000000e+00
SS#1 [248r,336B:0)[376r,556r:0) 0@x weight:2.000000e+00
MCP: BackwardCopyPropagateBlock entry
MCP: ForwardCopyPropagateBlock entry
MCP: Copy is a deletion candidate: renamable $rc30 = COPY $a
MCP: Copy is used - not dead: renamable $rc30 = COPY $a
MCP: Copy is a deletion candidate: renamable $x = COPY killed renamable $rc30
MCP: Copy is a deletion candidate: renamable $rs15 = COPY $rs1
MCP: Copy is used - not dead: renamable $x = COPY killed renamable $rc30
MCP: BackwardCopyPropagateBlock
MCP: ForwardCopyPropagateBlock
MCP: BackwardCopyPropagateBlock select.false
MCP: ForwardCopyPropagateBlock select.false
MCP: BackwardCopyPropagateBlock select.end
MCP: ForwardCopyPropagateBlock select.end
MCP: BackwardCopyPropagateBlock
MCP: ForwardCopyPropagateBlock
MCP: BackwardCopyPropagateBlock select.false9
MCP: ForwardCopyPropagateBlock select.false9
MCP: BackwardCopyPropagateBlock select.end8
MCP: ForwardCopyPropagateBlock select.end8
MCP: Copy is a deletion candidate: renamable $rc16 = COPY killed renamable $a
MCP: Copy is a deletion candidate: renamable $rc17 = COPY killed renamable $x
MCP: Copy is a deletion candidate: $rs1 = COPY renamable $rs15
MCP: Copy is used - not dead: renamable $rc16 = COPY killed renamable $a
MCP: Copy is used - not dead: renamable $rc17 = COPY killed renamable $x
MCP: Copy is used - not dead: $rs1 = COPY renamable $rs15
MCP: Copy is used - not dead: $rs1 = COPY renamable $rs15
MCP: Copy is a deletion candidate: renamable $rc2 = COPY renamable $a
MCP: Copy is a deletion candidate: renamable $rc4 = COPY killed renamable $a
MCP: Copy is a deletion candidate: renamable $rc3 = COPY renamable $a
MCP: Copy is a deletion candidate: renamable $rc5 = COPY killed renamable $a
MCP: Copy is used - not dead: renamable $rc2 = COPY renamable $a
MCP: Copy is used - not dead: renamable $rc3 = COPY renamable $a
MCP: Copy is a deletion candidate: renamable $rc16 = COPY killed renamable $a
MCP: Copy is used - not dead: renamable $rc4 = COPY killed renamable $a
MCP: Copy is used - not dead: renamable $rc5 = COPY killed renamable $a
MCP: Copy is a deletion candidate: renamable $rc17 = COPY killed renamable $a
MCP: Copy is a deletion candidate: $rs1 = COPY killed renamable $rs15
MCP: Copy is used - not dead: renamable $rc16 = COPY killed renamable $a
MCP: Copy is used - not dead: renamable $rc17 = COPY killed renamable $a
MCP: Copy is used - not dead: $rs1 = COPY killed renamable $rs15
MCP: Copy is used - not dead: $rs1 = COPY killed renamable $rs15
******** Post-regalloc Machine LICM: _Z11testIndCallc ********
block-frequency: _Z11testIndCallc
=================================
reverse-post-order-traversal
- 0: BB0[entry]
- 1: BB2[select.false]
- 2: BB1
- 3: BB3[select.end]
- 4: BB5[select.false9]
- 5: BB4
- 6: BB6[select.end8]
loop-detection
compute-mass-in-function
- node: BB0[entry]
=> [ local ] weight = 805306368, succ = BB1
=> [ local ] weight = 1342177280, succ = BB2[select.false]
=> mass: ffffffffffffffff
=> assign 9fffffffffffffff (6000000000000000) to BB2[select.false]
=> assign 6000000000000000 (0000000000000000) to BB1
- node: BB2[select.false]
=> [ local ] weight = 2147483648, succ = BB3[select.end]
=> mass: 9fffffffffffffff
=> assign 9fffffffffffffff (0000000000000000) to BB3[select.end]
- node: BB1
=> [ local ] weight = 2147483648, succ = BB3[select.end]
=> mass: 6000000000000000
=> assign 6000000000000000 (0000000000000000) to BB3[select.end]
- node: BB3[select.end]
=> [ local ] weight = 805306368, succ = BB4
=> [ local ] weight = 1342177280, succ = BB5[select.false9]
=> mass: ffffffffffffffff
=> assign 9fffffffffffffff (6000000000000000) to BB5[select.false9]
=> assign 6000000000000000 (0000000000000000) to BB4
- node: BB5[select.false9]
=> [ local ] weight = 2147483648, succ = BB6[select.end8]
=> mass: 9fffffffffffffff
=> assign 9fffffffffffffff (0000000000000000) to BB6[select.end8]
- node: BB4
=> [ local ] weight = 2147483648, succ = BB6[select.end8]
=> mass: 6000000000000000
=> assign 6000000000000000 (0000000000000000) to BB6[select.end8]
- node: BB6[select.end8]
=> mass: ffffffffffffffff
float-to-int: min = 0.375, max = 1.0, factor = 21.33333333
- BB0[entry]: float = 1.0, scaled = 21.33333333, int = 21
- BB2[select.false]: float = 0.625, scaled = 13.33333333, int = 13
- BB1: float = 0.375, scaled = 8.0, int = 8
- BB3[select.end]: float = 1.0, scaled = 21.33333333, int = 21
- BB5[select.false9]: float = 0.625, scaled = 13.33333333, int = 13
- BB4: float = 0.375, scaled = 8.0, int = 8
- BB6[select.end8]: float = 1.0, scaled = 21.33333333, int = 21
block-frequency-info: _Z11testIndCallc
- BB0[entry]: float = 1.0, int = 21
- BB1: float = 0.375, int = 8
- BB2[select.false]: float = 0.625, int = 13
- BB3[select.end]: float = 1.0, int = 21
- BB4: float = 0.375, int = 8
- BB5[select.false9]: float = 0.625, int = 13
- BB6[select.end8]: float = 1.0, int = 21
Looking for trivial roots
Found a new trivial root: %bb.6
Last visited node: %bb.5
Looking for non-trivial roots
Total: 7, Num: 8
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.6
3: %bb.4
4: %bb.3
5: %bb.1
6: %bb.0
7: %bb.2
8: %bb.5
Found roots: %bb.6
**** Analysing _Z11testIndCallc
Look into: 0 entry
Use or define CSR(1) or FI(0): renamable $rc30 = COPY $a
No Shrink wrap candidate found
alloc FI(0) at SP[-1]
alloc FI(1) at SP[-2]
Reload before: renamable $rc30 = COPY $a
Scavenged register with spill: $a until undef %5.subcarry:pc = LDCImm 0
Scavenged free register: $a
Scavenged free register: $p
Scavenged free register: $a
Scavenged free register: $a
Scavenged free register: $a
Scavenged free register: $y
Scavenged free register: $y
Scavenged free register: $y
Scavenged free register: $y
Reload before: STYIndir killed renamable $a, renamable $rs15, killed renamable $y :: (store 1 into %ir.0 + 1, !tbaa !2)
Scavenged register with spill: $y until %14:yc = LDImm 0
Reload before: STYIndir killed renamable $a, renamable $rs15, killed renamable $y :: (store 1 into %ir.0, !tbaa !2)
Scavenged register with spill: $y until %13:yc = LDImm 1
Scavenged free register: $a
Scavenged free register: $p
Scavenged free register: $a
Scavenged free register: $a
Scavenged free register: $a
TryTailMergeBlocks: %bb.2, %bb.1
with successor %bb.3
which has fall-through from %bb.2
Looking for common tails of at least 3 instructions
Common tail length of %bb.2 and %bb.1 is 2
Splitting %bb.2, size 2
Using common tail in %bb.7 for %bb.1
TryTailMergeBlocks: %bb.5, %bb.4
with successor %bb.6
which has fall-through from %bb.5
Looking for common tails of at least 3 instructions
Merging into block: bb.3.select.end:
; predecessors: %bb.2, %bb.1
successors: %bb.4(0x80000000); %bb.4(100.00%)
liveins: $x, $rs15, $a
$y = LDImm 0
STYIndir $a, $rs0, killed $y :: (store 1 into %stack.1)
From MBB: bb.4.select.end:
; predecessors: %bb.3
successors: %bb.5(0x30000000), %bb.6(0x50000000); %bb.5(37.50%), %bb.6(62.50%)
liveins: $x, $rs15
renamable $y = LDImm 0
$rc29 = STImag8 $y
$y = LDImm 1
$a = LDYIndir $rs0, killed $y :: (load 1 from %stack.0)
$y = LDImag8 $rc29
STYIndir killed renamable $a, renamable $rs15, killed renamable $y :: (store 1 into %ir.0, !tbaa !2)
renamable $y = LDImm 1
$rc29 = STImag8 $y
$y = LDImm 0
$a = LDYIndir $rs0, killed $y :: (load 1 from %stack.1)
$y = LDImag8 $rc29
STYIndir killed renamable $a, renamable $rs15, killed renamable $y :: (store 1 into %ir.0 + 1, !tbaa !2)
dead renamable $c = CMPImmTerm killed renamable $x, 0, implicit-def dead $nz, implicit-def $z
BR %bb.6, killed $z, 0
Removing MBB: bb.4.select.end:
liveins: $x, $rs15
TryTailMergeBlocks: %bb.2, %bb.1
with successor %bb.3
which has fall-through from %bb.2
Looking for common tails of at least 3 instructions
TryTailMergeBlocks: %bb.6, %bb.5
with successor %bb.7
which has fall-through from %bb.6
Looking for common tails of at least 3 instructions
MCP: BackwardCopyPropagateBlock entry
MCP: ForwardCopyPropagateBlock entry
MCP: Copy is a deletion candidate: $a = COPY $rc0
MCP: Copy is used - not dead: $a = COPY $rc0
MCP: Copy is a deletion candidate: $a = COPY $rc1
MCP: Copy is used - not dead: $a = COPY $rc1
MCP: Copy is a deletion candidate: $rc1 = COPY killed $a
MCP: Copy is a deletion candidate: $rc0 = COPY killed $a
MCP: Copy is a deletion candidate: $a = frame-setup COPY $rc30
MCP: Copy is used - not dead: $a = frame-setup COPY $rc30
MCP: Copy is a deletion candidate: $a = frame-setup COPY $rc31
MCP: Copy is used - not dead: $a = frame-setup COPY $rc31
MCP: Copy is a deletion candidate: renamable $rc30 = COPY $a
MCP: Copy is used - not dead: renamable $rc30 = COPY $a
MCP: Copy is a deletion candidate: renamable $x = COPY killed renamable $rc30
MCP: Copy is a deletion candidate: renamable $rs15 = COPY $rs1
MCP: Copy is used - not dead: renamable $x = COPY killed renamable $rc30
MCP: BackwardCopyPropagateBlock
MCP: ForwardCopyPropagateBlock
MCP: BackwardCopyPropagateBlock select.false
MCP: ForwardCopyPropagateBlock select.false
MCP: BackwardCopyPropagateBlock select.end
MCP: ForwardCopyPropagateBlock select.end
MCP: BackwardCopyPropagateBlock
MCP: ForwardCopyPropagateBlock
MCP: BackwardCopyPropagateBlock select.false9
MCP: ForwardCopyPropagateBlock select.false9
MCP: BackwardCopyPropagateBlock select.end8
MCP: ForwardCopyPropagateBlock select.end8
MCP: Copy is a deletion candidate: renamable $rc16 = COPY killed renamable $a
MCP: Copy is a deletion candidate: renamable $rc17 = COPY killed renamable $x
MCP: Copy is a deletion candidate: $rs1 = COPY renamable $rs15
MCP: Copy is used - not dead: renamable $rc16 = COPY killed renamable $a
MCP: Copy is used - not dead: renamable $rc17 = COPY killed renamable $x
MCP: Copy is used - not dead: $rs1 = COPY renamable $rs15
MCP: Copy is used - not dead: $rs1 = COPY renamable $rs15
MCP: Copy is a deletion candidate: renamable $rc2 = COPY renamable $a
MCP: Copy is a deletion candidate: renamable $rc4 = COPY killed renamable $a
MCP: Copy is a deletion candidate: renamable $rc3 = COPY renamable $a
MCP: Copy is a deletion candidate: renamable $rc5 = COPY killed renamable $a
MCP: Copy is used - not dead: renamable $rc2 = COPY renamable $a
MCP: Copy is used - not dead: renamable $rc3 = COPY renamable $a
MCP: Copy is a deletion candidate: renamable $rc16 = COPY killed renamable $a
MCP: Copy is used - not dead: renamable $rc4 = COPY killed renamable $a
MCP: Copy is used - not dead: renamable $rc5 = COPY killed renamable $a
MCP: Copy is a deletion candidate: renamable $rc17 = COPY killed renamable $a
MCP: Copy is a deletion candidate: $rs1 = COPY killed renamable $rs15
MCP: Copy is used - not dead: renamable $rc16 = COPY killed renamable $a
MCP: Copy is used - not dead: renamable $rc17 = COPY killed renamable $a
MCP: Copy is used - not dead: $rs1 = COPY killed renamable $rs15
MCP: Copy is used - not dead: $rs1 = COPY killed renamable $rs15
MCP: Copy is a deletion candidate: $rc31 = frame-destroy COPY killed $a
MCP: Copy is a deletion candidate: $rc30 = frame-destroy COPY killed $a
MCP: Copy is a deletion candidate: $a = COPY $rc0
MCP: Copy is used - not dead: $a = COPY $rc0
MCP: Copy is a deletion candidate: $rc0 = COPY killed $a
MCP: Copy is a deletion candidate: $a = COPY $rc1
MCP: Copy is used - not dead: $a = COPY $rc1
MCP: Copy is a deletion candidate: $rc1 = COPY killed $a
MCP: Copy is used - not dead: $rc30 = frame-destroy COPY killed $a
MCP: Copy is used - not dead: $rc31 = frame-destroy COPY killed $a
Machine Function
********** EXPANDING POST-RA PSEUDO INSTRS **********
********** Function: _Z11testIndCallc
real copy: $a = COPY $rc0
replaced by: $a = LDImag8 $rc0
real copy: $a = COPY $rc1
replaced by: $a = LDImag8 $rc1
real copy: $rc1 = COPY killed $a
replaced by: $rc1 = STImag8 $a
real copy: $rc0 = COPY killed $a
replaced by: $rc0 = STImag8 $a
real copy: $a = frame-setup COPY $rc30
replaced by: $a = LDImag8 $rc30
real copy: $a = frame-setup COPY $rc31
replaced by: $a = LDImag8 $rc31
real copy: renamable $rc30 = COPY $a
replaced by: $rc30 = STImag8 $a
real copy: renamable $x = COPY killed renamable $rc30
replaced by: $x = LDImag8 $rc30
real copy: renamable $rs15 = COPY $rs1
replaced by: $rc31 = STImag8 %1:gpr
real copy: renamable $rc16 = COPY killed renamable $a
replaced by: $rc16 = STImag8 $a
real copy: renamable $rc17 = COPY killed renamable $x
replaced by: $rc17 = STImag8 $x
real copy: $rs1 = COPY renamable $rs15
replaced by: $rc3 = STImag8 %3:gpr
real copy: renamable $rc2 = COPY renamable $a
replaced by: $rc2 = STImag8 $a
real copy: renamable $rc4 = COPY killed renamable $a
replaced by: $rc4 = STImag8 $a
real copy: renamable $rc3 = COPY renamable $a
replaced by: $rc3 = STImag8 $a
real copy: renamable $rc5 = COPY killed renamable $a
replaced by: $rc5 = STImag8 $a
real copy: renamable $rc16 = COPY killed renamable $a
replaced by: $rc16 = STImag8 $a
real copy: renamable $rc17 = COPY killed renamable $a
replaced by: $rc17 = STImag8 $a
real copy: $rs1 = COPY killed renamable $rs15
replaced by: $rc3 = STImag8 %5:gpr
real copy: $rc31 = frame-destroy COPY killed $a
replaced by: $rc31 = STImag8 $a
real copy: $rc30 = frame-destroy COPY killed $a
replaced by: $rc30 = STImag8 $a
real copy: $a = COPY $rc0
replaced by: $a = LDImag8 $rc0
real copy: $rc0 = COPY killed $a
replaced by: $rc0 = STImag8 $a
real copy: $a = COPY $rc1
replaced by: $a = LDImag8 $rc1
real copy: $rc1 = COPY killed $a
replaced by: $rc1 = STImag8 $a
Scavenged free register: $a
Scavenged free register: $a
Scavenged free register: $a
Scavenged free register: $a
Scavenged free register: $a
Scavenged free register: $a
Machine Function
********** EXPANDING POST-RA PSEUDO INSTRS **********
********** Function: _Z11testIndCallc
[SafeStack] Function: _ZN4SubAD0Ev
[SafeStack] safestack is not requested for this function
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4SubAD0Ev ----
Computing probabilities for entry
Checking DILocation from tail call void @_ZdlPv(i8* nonnull %0) #6 was copied to ADJCALLSTACKDOWN implicit-def $rs0, implicit $rs0
Checking DILocation from tail call void @_ZdlPv(i8* nonnull %0) #6 was copied to COPY
Checking DILocation from tail call void @_ZdlPv(i8* nonnull %0) #6 was copied to JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
Checking DILocation from tail call void @_ZdlPv(i8* nonnull %0) #6 was copied to ADJCALLSTACKUP implicit-def $rs0, implicit $rs0
Checking DILocation from ret void was copied to RTS
Generic MI Combiner for: _ZN4SubAD0Ev
Try combining %0:_(p0) = COPY $rs1
Try combining ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Try combining $rs1 = COPY %0:_(p0)
Try combining JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
Try combining ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Try combining RTS
Legalize Machine IR for: _ZN4SubAD0Ev
=== New Iteration ===
.. No debug info was present
Generic MI Combiner for: _ZN4SubAD0Ev
Try combining %0:_(p0) = COPY $rs1
Try combining ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Try combining $rs1 = COPY %0:_(p0)
Try combining JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
Try combining ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Try combining RTS
Handling G_SELECTs in: _ZN4SubAD0Ev
Iteratively lowering G_SELECTs.
Assign register banks for: _ZN4SubAD0Ev
Assign: %0:_(p0) = COPY $rs1
Evaluating mapping cost for: %0:_(p0) = COPY $rs1
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Assign: $rs1 = COPY %0:any(p0)
Evaluating mapping cost for: $rs1 = COPY %0:any(p0)
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Localize instructions for: _ZN4SubAD0Ev
Selecting function: _ZN4SubAD0Ev
Selecting:
RTS
Into:
RTS
Selecting:
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Into:
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Selecting:
JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
Into:
JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
Selecting:
$rs1 = COPY %0:any(p0)
Into:
$rs1 = COPY %0:any(p0)
Selecting:
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Into:
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Selecting:
%0:any(p0) = COPY $rs1
Into:
%0:imag16(p0) = COPY $rs1
Rules covered by selecting function: _ZN4SubAD0Ev:
# Machine code for function _ZN4SubAD0Ev: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
0B bb.1.entry:
liveins: $rs1
16B %0:imag16 = COPY $rs1
32B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
48B $rs1 = COPY %0:imag16
64B JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
80B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
96B RTS
# End machine code for function _ZN4SubAD0Ev.
********** Stack Coloring **********
********** Function: _ZN4SubAD0Ev
block-frequency: _ZN4SubAD0Ev
=============================
reverse-post-order-traversal
- 0: BB1[entry]
loop-detection
compute-mass-in-function
- node: BB1[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB1[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubAD0Ev
- BB1[entry]: float = 1.0, int = 8
******** Pre-regalloc Machine LICM: _ZN4SubAD0Ev ********
block-frequency: _ZN4SubAD0Ev
=============================
reverse-post-order-traversal
- 0: BB1[entry]
loop-detection
compute-mass-in-function
- node: BB1[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB1[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubAD0Ev
- BB1[entry]: float = 1.0, int = 8
Entering: entry
Exiting: entry
Looking for trivial roots
Found a new trivial root: %bb.1
Last visited node: %bb.1
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.1
Found roots: %bb.1
******** Machine Sinking ********
********** PEEPHOLE OPTIMIZER **********
********** Function: _ZN4SubAD0Ev
Encountered load fold barrier on JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
Defined/Used lanes:
%0 Used: 0000000000000022 Def: 0000000000000022
********** PROCESS IMPLICIT DEFS **********
********** Function: _ZN4SubAD0Ev
********** REWRITING TWO-ADDR INSTRS **********
********** Function: _ZN4SubAD0Ev
# Machine code for function _ZN4SubAD0Ev: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B %0:imag16 = COPY killed $rs1
32B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
48B $rs1 = COPY killed %0:imag16
64B JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit killed $rs1
80B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
96B RTS
# End machine code for function _ZN4SubAD0Ev.
Computing live-in reg-units in ABI blocks.
0B %bb.0 RC2LSB#0 RC3LSB#0
Created 2 new intervals.
********** INTERVALS **********
RC2LSB [0B,16r:0)[48r,64r:1) 0@0B-phi 1@48r
RC3LSB [0B,16r:0)[48r,64r:1) 0@0B-phi 1@48r
%0 [16r,48r:0) 0@16r weight:0.000000e+00
RegMasks: 64r
********** MACHINEINSTRS **********
# Machine code for function _ZN4SubAD0Ev: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B %0:imag16 = COPY $rs1
32B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
48B $rs1 = COPY %0:imag16
64B JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
80B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
96B RTS
# End machine code for function _ZN4SubAD0Ev.
********** SIMPLE REGISTER COALESCING **********
********** Function: _ZN4SubAD0Ev
********** JOINING INTERVALS ***********
entry:
16B %0:imag16 = COPY $rs1
Considering merging %0 with $rs1
Can only merge into reserved registers.
48B $rs1 = COPY %0:imag16
Considering merging %0 with $rs1
Can only merge into reserved registers.
48B $rs1 = COPY %0:imag16
Considering merging %0 with $rs1
Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
RC2LSB [0B,16r:0)[48r,64r:1) 0@0B-phi 1@48r
RC3LSB [0B,16r:0)[48r,64r:1) 0@0B-phi 1@48r
%0 [16r,48r:0) 0@16r weight:0.000000e+00
RegMasks: 64r
********** MACHINEINSTRS **********
# Machine code for function _ZN4SubAD0Ev: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B %0:imag16 = COPY $rs1
32B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
48B $rs1 = COPY %0:imag16
64B JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
80B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
96B RTS
# End machine code for function _ZN4SubAD0Ev.
Renaming independent subregister live ranges in _ZN4SubAD0Ev
Before MISched:
# Machine code for function _ZN4SubAD0Ev: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
bb.0.entry:
liveins: $rs1
%0:imag16 = COPY $rs1
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
$rs1 = COPY %0:imag16
JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
RTS
# End machine code for function _ZN4SubAD0Ev.
********** INTERVALS **********
RC2LSB [0B,16r:0)[48r,64r:1) 0@0B-phi 1@48r
RC3LSB [0B,16r:0)[48r,64r:1) 0@0B-phi 1@48r
%0 [16r,48r:0) 0@16r weight:0.000000e+00
RegMasks: 64r
********** MACHINEINSTRS **********
# Machine code for function _ZN4SubAD0Ev: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B %0:imag16 = COPY $rs1
32B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
48B $rs1 = COPY %0:imag16
64B JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
80B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
96B RTS
# End machine code for function _ZN4SubAD0Ev.
block-frequency: _ZN4SubAD0Ev
=============================
reverse-post-order-traversal
- 0: BB0[entry]
loop-detection
compute-mass-in-function
- node: BB0[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB0[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubAD0Ev
- BB0[entry]: float = 1.0, int = 8
********** GREEDY REGISTER ALLOCATION **********
********** Function: _ZN4SubAD0Ev
********** Compute Spill Weights **********
********** Function: _ZN4SubAD0Ev
********** INTERVALS **********
RC2LSB [0B,16r:0)[48r,64r:1) 0@0B-phi 1@48r
RC3LSB [0B,16r:0)[48r,64r:1) 0@0B-phi 1@48r
%0 [16r,48r:0) 0@16r weight:4.675926e-03
RegMasks: 64r
********** MACHINEINSTRS **********
# Machine code for function _ZN4SubAD0Ev: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B %0:imag16 = COPY $rs1
32B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
48B $rs1 = COPY %0:imag16
64B JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
80B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
96B RTS
# End machine code for function _ZN4SubAD0Ev.
selectOrSplit Imag16:%0 [16r,48r:0) 0@16r weight:4.675926e-03 w=4.675926e-03
hints: $rs1
assigning %0 to $rs1: RC2LSB [16r,48r:0) 0@16r RC3LSB [16r,48r:0) 0@16r
********** REWRITE VIRTUAL REGISTERS **********
********** Function: _ZN4SubAD0Ev
********** REGISTER MAP **********
[%0 -> $rs1] Imag16
0B bb.0.entry:
liveins: $rs1
16B %0:imag16 = COPY $rs1
32B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
48B $rs1 = COPY killed %0:imag16
64B JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
80B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
96B RTS
> renamable $rs1 = COPY $rs1
Identity copy: renamable $rs1 = COPY $rs1
deleted.
> ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
> $rs1 = COPY killed renamable $rs1
Identity copy: $rs1 = COPY killed renamable $rs1
deleted.
> JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
> ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
> RTS
********** Stack Slot Coloring **********
********** Function: _ZN4SubAD0Ev
MCP: BackwardCopyPropagateBlock entry
MCP: ForwardCopyPropagateBlock entry
******** Post-regalloc Machine LICM: _ZN4SubAD0Ev ********
block-frequency: _ZN4SubAD0Ev
=============================
reverse-post-order-traversal
- 0: BB0[entry]
loop-detection
compute-mass-in-function
- node: BB0[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB0[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubAD0Ev
- BB0[entry]: float = 1.0, int = 8
Looking for trivial roots
Found a new trivial root: %bb.0
Last visited node: %bb.0
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.0
Found roots: %bb.0
**** Analysing _ZN4SubAD0Ev
Look into: 0 entry
Frame instruction: ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
No Shrink wrap candidate found
MCP: BackwardCopyPropagateBlock entry
MCP: ForwardCopyPropagateBlock entry
Machine Function
********** EXPANDING POST-RA PSEUDO INSTRS **********
********** Function: _ZN4SubAD0Ev
Machine Function
********** EXPANDING POST-RA PSEUDO INSTRS **********
********** Function: _ZN4SubAD0Ev
[SafeStack] Function: _ZN4SubA2fnEv
[SafeStack] safestack is not requested for this function
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4SubA2fnEv ----
Computing probabilities for entry
Checking DILocation from ret void was copied to RTS
Generic MI Combiner for: _ZN4SubA2fnEv
%0:_(p0) = COPY $rs1
Is dead; erasing.
Erasing: %0:_(p0) = COPY $rs1
Try combining RTS
Legalize Machine IR for: _ZN4SubA2fnEv
=== New Iteration ===
.. No debug info was present
Generic MI Combiner for: _ZN4SubA2fnEv
Try combining RTS
Handling G_SELECTs in: _ZN4SubA2fnEv
Iteratively lowering G_SELECTs.
Assign register banks for: _ZN4SubA2fnEv
Localize instructions for: _ZN4SubA2fnEv
Selecting function: _ZN4SubA2fnEv
Selecting:
RTS
Into:
RTS
Rules covered by selecting function: _ZN4SubA2fnEv:
# Machine code for function _ZN4SubA2fnEv: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
0B bb.1.entry:
liveins: $rs1
16B RTS
# End machine code for function _ZN4SubA2fnEv.
********** Stack Coloring **********
********** Function: _ZN4SubA2fnEv
block-frequency: _ZN4SubA2fnEv
==============================
reverse-post-order-traversal
- 0: BB1[entry]
loop-detection
compute-mass-in-function
- node: BB1[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB1[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubA2fnEv
- BB1[entry]: float = 1.0, int = 8
******** Pre-regalloc Machine LICM: _ZN4SubA2fnEv ********
block-frequency: _ZN4SubA2fnEv
==============================
reverse-post-order-traversal
- 0: BB1[entry]
loop-detection
compute-mass-in-function
- node: BB1[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB1[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubA2fnEv
- BB1[entry]: float = 1.0, int = 8
Entering: entry
Exiting: entry
Looking for trivial roots
Found a new trivial root: %bb.1
Last visited node: %bb.1
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.1
Found roots: %bb.1
******** Machine Sinking ********
********** PEEPHOLE OPTIMIZER **********
********** Function: _ZN4SubA2fnEv
Defined/Used lanes:
%0 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
********** PROCESS IMPLICIT DEFS **********
********** Function: _ZN4SubA2fnEv
********** REWRITING TWO-ADDR INSTRS **********
********** Function: _ZN4SubA2fnEv
# Machine code for function _ZN4SubA2fnEv: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B RTS
# End machine code for function _ZN4SubA2fnEv.
Computing live-in reg-units in ABI blocks.
0B %bb.0 RC2LSB#0 RC3LSB#0
Created 2 new intervals.
********** INTERVALS **********
RC2LSB [0B,0d:0) 0@0B-phi
RC3LSB [0B,0d:0) 0@0B-phi
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function _ZN4SubA2fnEv: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B RTS
# End machine code for function _ZN4SubA2fnEv.
********** SIMPLE REGISTER COALESCING **********
********** Function: _ZN4SubA2fnEv
********** JOINING INTERVALS ***********
entry:
Trying to inflate 0 regs.
********** INTERVALS **********
RC2LSB [0B,0d:0) 0@0B-phi
RC3LSB [0B,0d:0) 0@0B-phi
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function _ZN4SubA2fnEv: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B RTS
# End machine code for function _ZN4SubA2fnEv.
Renaming independent subregister live ranges in _ZN4SubA2fnEv
Before MISched:
# Machine code for function _ZN4SubA2fnEv: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
bb.0.entry:
liveins: $rs1
RTS
# End machine code for function _ZN4SubA2fnEv.
********** INTERVALS **********
RC2LSB [0B,0d:0) 0@0B-phi
RC3LSB [0B,0d:0) 0@0B-phi
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function _ZN4SubA2fnEv: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B RTS
# End machine code for function _ZN4SubA2fnEv.
block-frequency: _ZN4SubA2fnEv
==============================
reverse-post-order-traversal
- 0: BB0[entry]
loop-detection
compute-mass-in-function
- node: BB0[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB0[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubA2fnEv
- BB0[entry]: float = 1.0, int = 8
********** GREEDY REGISTER ALLOCATION **********
********** Function: _ZN4SubA2fnEv
********** Compute Spill Weights **********
********** Function: _ZN4SubA2fnEv
********** INTERVALS **********
RC2LSB [0B,0d:0) 0@0B-phi
RC3LSB [0B,0d:0) 0@0B-phi
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function _ZN4SubA2fnEv: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B RTS
# End machine code for function _ZN4SubA2fnEv.
********** REWRITE VIRTUAL REGISTERS **********
********** Function: _ZN4SubA2fnEv
********** REGISTER MAP **********
0B bb.0.entry:
liveins: $rs1
16B RTS
> RTS
********** Stack Slot Coloring **********
********** Function: _ZN4SubA2fnEv
MCP: BackwardCopyPropagateBlock entry
MCP: ForwardCopyPropagateBlock entry
******** Post-regalloc Machine LICM: _ZN4SubA2fnEv ********
block-frequency: _ZN4SubA2fnEv
==============================
reverse-post-order-traversal
- 0: BB0[entry]
loop-detection
compute-mass-in-function
- node: BB0[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB0[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubA2fnEv
- BB0[entry]: float = 1.0, int = 8
Looking for trivial roots
Found a new trivial root: %bb.0
Last visited node: %bb.0
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.0
Found roots: %bb.0
**** Analysing _ZN4SubA2fnEv
Look into: 0 entry
Nothing to shrink-wrap
MCP: BackwardCopyPropagateBlock entry
MCP: ForwardCopyPropagateBlock entry
Machine Function
********** EXPANDING POST-RA PSEUDO INSTRS **********
********** Function: _ZN4SubA2fnEv
Machine Function
********** EXPANDING POST-RA PSEUDO INSTRS **********
********** Function: _ZN4SubA2fnEv
[SafeStack] Function: _ZN4BaseD2Ev
[SafeStack] safestack is not requested for this function
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4BaseD2Ev ----
Computing probabilities for entry
Checking DILocation from ret void was copied to RTS
Generic MI Combiner for: _ZN4BaseD2Ev
%0:_(p0) = COPY $rs1
Is dead; erasing.
Erasing: %0:_(p0) = COPY $rs1
Try combining RTS
Legalize Machine IR for: _ZN4BaseD2Ev
=== New Iteration ===
.. No debug info was present
Generic MI Combiner for: _ZN4BaseD2Ev
Try combining RTS
Handling G_SELECTs in: _ZN4BaseD2Ev
Iteratively lowering G_SELECTs.
Assign register banks for: _ZN4BaseD2Ev
Localize instructions for: _ZN4BaseD2Ev
Selecting function: _ZN4BaseD2Ev
Selecting:
RTS
Into:
RTS
Rules covered by selecting function: _ZN4BaseD2Ev:
# Machine code for function _ZN4BaseD2Ev: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
0B bb.1.entry:
liveins: $rs1
16B RTS
# End machine code for function _ZN4BaseD2Ev.
********** Stack Coloring **********
********** Function: _ZN4BaseD2Ev
block-frequency: _ZN4BaseD2Ev
=============================
reverse-post-order-traversal
- 0: BB1[entry]
loop-detection
compute-mass-in-function
- node: BB1[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB1[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4BaseD2Ev
- BB1[entry]: float = 1.0, int = 8
******** Pre-regalloc Machine LICM: _ZN4BaseD2Ev ********
block-frequency: _ZN4BaseD2Ev
=============================
reverse-post-order-traversal
- 0: BB1[entry]
loop-detection
compute-mass-in-function
- node: BB1[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB1[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4BaseD2Ev
- BB1[entry]: float = 1.0, int = 8
Entering: entry
Exiting: entry
Looking for trivial roots
Found a new trivial root: %bb.1
Last visited node: %bb.1
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.1
Found roots: %bb.1
******** Machine Sinking ********
********** PEEPHOLE OPTIMIZER **********
********** Function: _ZN4BaseD2Ev
Defined/Used lanes:
%0 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
********** PROCESS IMPLICIT DEFS **********
********** Function: _ZN4BaseD2Ev
********** REWRITING TWO-ADDR INSTRS **********
********** Function: _ZN4BaseD2Ev
# Machine code for function _ZN4BaseD2Ev: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B RTS
# End machine code for function _ZN4BaseD2Ev.
Computing live-in reg-units in ABI blocks.
0B %bb.0 RC2LSB#0 RC3LSB#0
Created 2 new intervals.
********** INTERVALS **********
RC2LSB [0B,0d:0) 0@0B-phi
RC3LSB [0B,0d:0) 0@0B-phi
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function _ZN4BaseD2Ev: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B RTS
# End machine code for function _ZN4BaseD2Ev.
********** SIMPLE REGISTER COALESCING **********
********** Function: _ZN4BaseD2Ev
********** JOINING INTERVALS ***********
entry:
Trying to inflate 0 regs.
********** INTERVALS **********
RC2LSB [0B,0d:0) 0@0B-phi
RC3LSB [0B,0d:0) 0@0B-phi
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function _ZN4BaseD2Ev: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B RTS
# End machine code for function _ZN4BaseD2Ev.
Renaming independent subregister live ranges in _ZN4BaseD2Ev
Before MISched:
# Machine code for function _ZN4BaseD2Ev: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
bb.0.entry:
liveins: $rs1
RTS
# End machine code for function _ZN4BaseD2Ev.
********** INTERVALS **********
RC2LSB [0B,0d:0) 0@0B-phi
RC3LSB [0B,0d:0) 0@0B-phi
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function _ZN4BaseD2Ev: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B RTS
# End machine code for function _ZN4BaseD2Ev.
block-frequency: _ZN4BaseD2Ev
=============================
reverse-post-order-traversal
- 0: BB0[entry]
loop-detection
compute-mass-in-function
- node: BB0[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB0[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4BaseD2Ev
- BB0[entry]: float = 1.0, int = 8
********** GREEDY REGISTER ALLOCATION **********
********** Function: _ZN4BaseD2Ev
********** Compute Spill Weights **********
********** Function: _ZN4BaseD2Ev
********** INTERVALS **********
RC2LSB [0B,0d:0) 0@0B-phi
RC3LSB [0B,0d:0) 0@0B-phi
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function _ZN4BaseD2Ev: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B RTS
# End machine code for function _ZN4BaseD2Ev.
********** REWRITE VIRTUAL REGISTERS **********
********** Function: _ZN4BaseD2Ev
********** REGISTER MAP **********
0B bb.0.entry:
liveins: $rs1
16B RTS
> RTS
********** Stack Slot Coloring **********
********** Function: _ZN4BaseD2Ev
MCP: BackwardCopyPropagateBlock entry
MCP: ForwardCopyPropagateBlock entry
******** Post-regalloc Machine LICM: _ZN4BaseD2Ev ********
block-frequency: _ZN4BaseD2Ev
=============================
reverse-post-order-traversal
- 0: BB0[entry]
loop-detection
compute-mass-in-function
- node: BB0[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB0[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4BaseD2Ev
- BB0[entry]: float = 1.0, int = 8
Looking for trivial roots
Found a new trivial root: %bb.0
Last visited node: %bb.0
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.0
Found roots: %bb.0
**** Analysing _ZN4BaseD2Ev
Look into: 0 entry
Nothing to shrink-wrap
MCP: BackwardCopyPropagateBlock entry
MCP: ForwardCopyPropagateBlock entry
Machine Function
********** EXPANDING POST-RA PSEUDO INSTRS **********
********** Function: _ZN4BaseD2Ev
Machine Function
********** EXPANDING POST-RA PSEUDO INSTRS **********
********** Function: _ZN4BaseD2Ev
[SafeStack] Function: _ZN4SubBD0Ev
[SafeStack] safestack is not requested for this function
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4SubBD0Ev ----
Computing probabilities for entry
Checking DILocation from tail call void @_ZdlPv(i8* nonnull %0) #6 was copied to ADJCALLSTACKDOWN implicit-def $rs0, implicit $rs0
Checking DILocation from tail call void @_ZdlPv(i8* nonnull %0) #6 was copied to COPY
Checking DILocation from tail call void @_ZdlPv(i8* nonnull %0) #6 was copied to JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
Checking DILocation from tail call void @_ZdlPv(i8* nonnull %0) #6 was copied to ADJCALLSTACKUP implicit-def $rs0, implicit $rs0
Checking DILocation from ret void was copied to RTS
Generic MI Combiner for: _ZN4SubBD0Ev
Try combining %0:_(p0) = COPY $rs1
Try combining ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Try combining $rs1 = COPY %0:_(p0)
Try combining JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
Try combining ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Try combining RTS
Legalize Machine IR for: _ZN4SubBD0Ev
=== New Iteration ===
.. No debug info was present
Generic MI Combiner for: _ZN4SubBD0Ev
Try combining %0:_(p0) = COPY $rs1
Try combining ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Try combining $rs1 = COPY %0:_(p0)
Try combining JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
Try combining ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Try combining RTS
Handling G_SELECTs in: _ZN4SubBD0Ev
Iteratively lowering G_SELECTs.
Assign register banks for: _ZN4SubBD0Ev
Assign: %0:_(p0) = COPY $rs1
Evaluating mapping cost for: %0:_(p0) = COPY $rs1
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: none against Any
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Assign: $rs1 = COPY %0:any(p0)
Evaluating mapping cost for: $rs1 = COPY %0:any(p0)
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Opd0
Does assignment already match: Any against Any
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 15], RegBank = Any]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping:
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Localize instructions for: _ZN4SubBD0Ev
Selecting function: _ZN4SubBD0Ev
Selecting:
RTS
Into:
RTS
Selecting:
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Into:
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
Selecting:
JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
Into:
JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
Selecting:
$rs1 = COPY %0:any(p0)
Into:
$rs1 = COPY %0:any(p0)
Selecting:
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Into:
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
Selecting:
%0:any(p0) = COPY $rs1
Into:
%0:imag16(p0) = COPY $rs1
Rules covered by selecting function: _ZN4SubBD0Ev:
# Machine code for function _ZN4SubBD0Ev: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
0B bb.1.entry:
liveins: $rs1
16B %0:imag16 = COPY $rs1
32B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
48B $rs1 = COPY %0:imag16
64B JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
80B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
96B RTS
# End machine code for function _ZN4SubBD0Ev.
********** Stack Coloring **********
********** Function: _ZN4SubBD0Ev
block-frequency: _ZN4SubBD0Ev
=============================
reverse-post-order-traversal
- 0: BB1[entry]
loop-detection
compute-mass-in-function
- node: BB1[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB1[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubBD0Ev
- BB1[entry]: float = 1.0, int = 8
******** Pre-regalloc Machine LICM: _ZN4SubBD0Ev ********
block-frequency: _ZN4SubBD0Ev
=============================
reverse-post-order-traversal
- 0: BB1[entry]
loop-detection
compute-mass-in-function
- node: BB1[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB1[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubBD0Ev
- BB1[entry]: float = 1.0, int = 8
Entering: entry
Exiting: entry
Looking for trivial roots
Found a new trivial root: %bb.1
Last visited node: %bb.1
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.1
Found roots: %bb.1
******** Machine Sinking ********
********** PEEPHOLE OPTIMIZER **********
********** Function: _ZN4SubBD0Ev
Encountered load fold barrier on JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
Defined/Used lanes:
%0 Used: 0000000000000022 Def: 0000000000000022
********** PROCESS IMPLICIT DEFS **********
********** Function: _ZN4SubBD0Ev
********** REWRITING TWO-ADDR INSTRS **********
********** Function: _ZN4SubBD0Ev
# Machine code for function _ZN4SubBD0Ev: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B %0:imag16 = COPY killed $rs1
32B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
48B $rs1 = COPY killed %0:imag16
64B JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit killed $rs1
80B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
96B RTS
# End machine code for function _ZN4SubBD0Ev.
Computing live-in reg-units in ABI blocks.
0B %bb.0 RC2LSB#0 RC3LSB#0
Created 2 new intervals.
********** INTERVALS **********
RC2LSB [0B,16r:0)[48r,64r:1) 0@0B-phi 1@48r
RC3LSB [0B,16r:0)[48r,64r:1) 0@0B-phi 1@48r
%0 [16r,48r:0) 0@16r weight:0.000000e+00
RegMasks: 64r
********** MACHINEINSTRS **********
# Machine code for function _ZN4SubBD0Ev: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B %0:imag16 = COPY $rs1
32B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
48B $rs1 = COPY %0:imag16
64B JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
80B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
96B RTS
# End machine code for function _ZN4SubBD0Ev.
********** SIMPLE REGISTER COALESCING **********
********** Function: _ZN4SubBD0Ev
********** JOINING INTERVALS ***********
entry:
16B %0:imag16 = COPY $rs1
Considering merging %0 with $rs1
Can only merge into reserved registers.
48B $rs1 = COPY %0:imag16
Considering merging %0 with $rs1
Can only merge into reserved registers.
48B $rs1 = COPY %0:imag16
Considering merging %0 with $rs1
Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
RC2LSB [0B,16r:0)[48r,64r:1) 0@0B-phi 1@48r
RC3LSB [0B,16r:0)[48r,64r:1) 0@0B-phi 1@48r
%0 [16r,48r:0) 0@16r weight:0.000000e+00
RegMasks: 64r
********** MACHINEINSTRS **********
# Machine code for function _ZN4SubBD0Ev: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B %0:imag16 = COPY $rs1
32B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
48B $rs1 = COPY %0:imag16
64B JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
80B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
96B RTS
# End machine code for function _ZN4SubBD0Ev.
Renaming independent subregister live ranges in _ZN4SubBD0Ev
Before MISched:
# Machine code for function _ZN4SubBD0Ev: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
bb.0.entry:
liveins: $rs1
%0:imag16 = COPY $rs1
ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
$rs1 = COPY %0:imag16
JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
RTS
# End machine code for function _ZN4SubBD0Ev.
********** INTERVALS **********
RC2LSB [0B,16r:0)[48r,64r:1) 0@0B-phi 1@48r
RC3LSB [0B,16r:0)[48r,64r:1) 0@0B-phi 1@48r
%0 [16r,48r:0) 0@16r weight:0.000000e+00
RegMasks: 64r
********** MACHINEINSTRS **********
# Machine code for function _ZN4SubBD0Ev: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B %0:imag16 = COPY $rs1
32B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
48B $rs1 = COPY %0:imag16
64B JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
80B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
96B RTS
# End machine code for function _ZN4SubBD0Ev.
block-frequency: _ZN4SubBD0Ev
=============================
reverse-post-order-traversal
- 0: BB0[entry]
loop-detection
compute-mass-in-function
- node: BB0[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB0[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubBD0Ev
- BB0[entry]: float = 1.0, int = 8
********** GREEDY REGISTER ALLOCATION **********
********** Function: _ZN4SubBD0Ev
********** Compute Spill Weights **********
********** Function: _ZN4SubBD0Ev
********** INTERVALS **********
RC2LSB [0B,16r:0)[48r,64r:1) 0@0B-phi 1@48r
RC3LSB [0B,16r:0)[48r,64r:1) 0@0B-phi 1@48r
%0 [16r,48r:0) 0@16r weight:4.675926e-03
RegMasks: 64r
********** MACHINEINSTRS **********
# Machine code for function _ZN4SubBD0Ev: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B %0:imag16 = COPY $rs1
32B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
48B $rs1 = COPY %0:imag16
64B JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
80B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
96B RTS
# End machine code for function _ZN4SubBD0Ev.
selectOrSplit Imag16:%0 [16r,48r:0) 0@16r weight:4.675926e-03 w=4.675926e-03
hints: $rs1
assigning %0 to $rs1: RC2LSB [16r,48r:0) 0@16r RC3LSB [16r,48r:0) 0@16r
********** REWRITE VIRTUAL REGISTERS **********
********** Function: _ZN4SubBD0Ev
********** REGISTER MAP **********
[%0 -> $rs1] Imag16
0B bb.0.entry:
liveins: $rs1
16B %0:imag16 = COPY $rs1
32B ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
48B $rs1 = COPY killed %0:imag16
64B JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
80B ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
96B RTS
> renamable $rs1 = COPY $rs1
Identity copy: renamable $rs1 = COPY $rs1
deleted.
> ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
> $rs1 = COPY killed renamable $rs1
Identity copy: $rs1 = COPY killed renamable $rs1
deleted.
> JSR @_ZdlPv, <regmask $rc30 $rc31 $rc32 $rc33 $rc34 $rc35 $rc36 $rc37 $rc38 $rc39 $rc40 $rc41 $rc42 $rc43 $rc44 $rc45 $rc46 $rc47 $rc48 $rc49 $rc50 $rc51 $rc52 $rc53 $rc54 $rc55 $rc56 $rc57 $rc58 $rc59 $rc60 $rc61 $rc62 and 532 more...>, implicit $rs1
> ADJCALLSTACKUP 0, 0, implicit-def $rs0, implicit $rs0
> RTS
********** Stack Slot Coloring **********
********** Function: _ZN4SubBD0Ev
MCP: BackwardCopyPropagateBlock entry
MCP: ForwardCopyPropagateBlock entry
******** Post-regalloc Machine LICM: _ZN4SubBD0Ev ********
block-frequency: _ZN4SubBD0Ev
=============================
reverse-post-order-traversal
- 0: BB0[entry]
loop-detection
compute-mass-in-function
- node: BB0[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB0[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubBD0Ev
- BB0[entry]: float = 1.0, int = 8
Looking for trivial roots
Found a new trivial root: %bb.0
Last visited node: %bb.0
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.0
Found roots: %bb.0
**** Analysing _ZN4SubBD0Ev
Look into: 0 entry
Frame instruction: ADJCALLSTACKDOWN 0, 0, implicit-def $rs0, implicit $rs0
No Shrink wrap candidate found
MCP: BackwardCopyPropagateBlock entry
MCP: ForwardCopyPropagateBlock entry
Machine Function
********** EXPANDING POST-RA PSEUDO INSTRS **********
********** Function: _ZN4SubBD0Ev
Machine Function
********** EXPANDING POST-RA PSEUDO INSTRS **********
********** Function: _ZN4SubBD0Ev
[SafeStack] Function: _ZN4SubB2fnEv
[SafeStack] safestack is not requested for this function
Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry
---- Branch Probability Info : _ZN4SubB2fnEv ----
Computing probabilities for entry
Checking DILocation from ret void was copied to RTS
Generic MI Combiner for: _ZN4SubB2fnEv
%0:_(p0) = COPY $rs1
Is dead; erasing.
Erasing: %0:_(p0) = COPY $rs1
Try combining RTS
Legalize Machine IR for: _ZN4SubB2fnEv
=== New Iteration ===
.. No debug info was present
Generic MI Combiner for: _ZN4SubB2fnEv
Try combining RTS
Handling G_SELECTs in: _ZN4SubB2fnEv
Iteratively lowering G_SELECTs.
Assign register banks for: _ZN4SubB2fnEv
Localize instructions for: _ZN4SubB2fnEv
Selecting function: _ZN4SubB2fnEv
Selecting:
RTS
Into:
RTS
Rules covered by selecting function: _ZN4SubB2fnEv:
# Machine code for function _ZN4SubB2fnEv: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
0B bb.1.entry:
liveins: $rs1
16B RTS
# End machine code for function _ZN4SubB2fnEv.
********** Stack Coloring **********
********** Function: _ZN4SubB2fnEv
block-frequency: _ZN4SubB2fnEv
==============================
reverse-post-order-traversal
- 0: BB1[entry]
loop-detection
compute-mass-in-function
- node: BB1[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB1[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubB2fnEv
- BB1[entry]: float = 1.0, int = 8
******** Pre-regalloc Machine LICM: _ZN4SubB2fnEv ********
block-frequency: _ZN4SubB2fnEv
==============================
reverse-post-order-traversal
- 0: BB1[entry]
loop-detection
compute-mass-in-function
- node: BB1[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB1[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubB2fnEv
- BB1[entry]: float = 1.0, int = 8
Entering: entry
Exiting: entry
Looking for trivial roots
Found a new trivial root: %bb.1
Last visited node: %bb.1
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.1
Found roots: %bb.1
******** Machine Sinking ********
********** PEEPHOLE OPTIMIZER **********
********** Function: _ZN4SubB2fnEv
Defined/Used lanes:
%0 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
********** PROCESS IMPLICIT DEFS **********
********** Function: _ZN4SubB2fnEv
********** REWRITING TWO-ADDR INSTRS **********
********** Function: _ZN4SubB2fnEv
# Machine code for function _ZN4SubB2fnEv: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B RTS
# End machine code for function _ZN4SubB2fnEv.
Computing live-in reg-units in ABI blocks.
0B %bb.0 RC2LSB#0 RC3LSB#0
Created 2 new intervals.
********** INTERVALS **********
RC2LSB [0B,0d:0) 0@0B-phi
RC3LSB [0B,0d:0) 0@0B-phi
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function _ZN4SubB2fnEv: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B RTS
# End machine code for function _ZN4SubB2fnEv.
********** SIMPLE REGISTER COALESCING **********
********** Function: _ZN4SubB2fnEv
********** JOINING INTERVALS ***********
entry:
Trying to inflate 0 regs.
********** INTERVALS **********
RC2LSB [0B,0d:0) 0@0B-phi
RC3LSB [0B,0d:0) 0@0B-phi
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function _ZN4SubB2fnEv: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B RTS
# End machine code for function _ZN4SubB2fnEv.
Renaming independent subregister live ranges in _ZN4SubB2fnEv
Before MISched:
# Machine code for function _ZN4SubB2fnEv: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
bb.0.entry:
liveins: $rs1
RTS
# End machine code for function _ZN4SubB2fnEv.
********** INTERVALS **********
RC2LSB [0B,0d:0) 0@0B-phi
RC3LSB [0B,0d:0) 0@0B-phi
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function _ZN4SubB2fnEv: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B RTS
# End machine code for function _ZN4SubB2fnEv.
block-frequency: _ZN4SubB2fnEv
==============================
reverse-post-order-traversal
- 0: BB0[entry]
loop-detection
compute-mass-in-function
- node: BB0[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB0[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubB2fnEv
- BB0[entry]: float = 1.0, int = 8
********** GREEDY REGISTER ALLOCATION **********
********** Function: _ZN4SubB2fnEv
********** Compute Spill Weights **********
********** Function: _ZN4SubB2fnEv
********** INTERVALS **********
RC2LSB [0B,0d:0) 0@0B-phi
RC3LSB [0B,0d:0) 0@0B-phi
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function _ZN4SubB2fnEv: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
0B bb.0.entry:
liveins: $rs1
16B RTS
# End machine code for function _ZN4SubB2fnEv.
********** REWRITE VIRTUAL REGISTERS **********
********** Function: _ZN4SubB2fnEv
********** REGISTER MAP **********
0B bb.0.entry:
liveins: $rs1
16B RTS
> RTS
********** Stack Slot Coloring **********
********** Function: _ZN4SubB2fnEv
MCP: BackwardCopyPropagateBlock entry
MCP: ForwardCopyPropagateBlock entry
******** Post-regalloc Machine LICM: _ZN4SubB2fnEv ********
block-frequency: _ZN4SubB2fnEv
==============================
reverse-post-order-traversal
- 0: BB0[entry]
loop-detection
compute-mass-in-function
- node: BB0[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB0[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubB2fnEv
- BB0[entry]: float = 1.0, int = 8
Looking for trivial roots
Found a new trivial root: %bb.0
Last visited node: %bb.0
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.0
Found roots: %bb.0
**** Analysing _ZN4SubB2fnEv
Look into: 0 entry
Nothing to shrink-wrap
MCP: BackwardCopyPropagateBlock entry
MCP: ForwardCopyPropagateBlock entry
Machine Function
********** EXPANDING POST-RA PSEUDO INSTRS **********
********** Function: _ZN4SubB2fnEv
Machine Function
********** EXPANDING POST-RA PSEUDO INSTRS **********
********** Function: _ZN4SubB2fnEv
block-frequency: _Z11testIndCallc
=================================
reverse-post-order-traversal
- 0: BB0[entry]
- 1: BB2[select.false]
- 2: BB1
- 3: BB3[select.end]
- 4: BB5[select.false9]
- 5: BB4
- 6: BB6[select.end8]
loop-detection
compute-mass-in-function
- node: BB0[entry]
=> [ local ] weight = 805306368, succ = BB1
=> [ local ] weight = 1342177280, succ = BB2[select.false]
=> mass: ffffffffffffffff
=> assign 9fffffffffffffff (6000000000000000) to BB2[select.false]
=> assign 6000000000000000 (0000000000000000) to BB1
- node: BB2[select.false]
=> [ local ] weight = 2147483648, succ = BB3[select.end]
=> mass: 9fffffffffffffff
=> assign 9fffffffffffffff (0000000000000000) to BB3[select.end]
- node: BB1
=> [ local ] weight = 2147483648, succ = BB3[select.end]
=> mass: 6000000000000000
=> assign 6000000000000000 (0000000000000000) to BB3[select.end]
- node: BB3[select.end]
=> [ local ] weight = 805306368, succ = BB4
=> [ local ] weight = 1342177280, succ = BB5[select.false9]
=> mass: ffffffffffffffff
=> assign 9fffffffffffffff (6000000000000000) to BB5[select.false9]
=> assign 6000000000000000 (0000000000000000) to BB4
- node: BB5[select.false9]
=> [ local ] weight = 2147483648, succ = BB6[select.end8]
=> mass: 9fffffffffffffff
=> assign 9fffffffffffffff (0000000000000000) to BB6[select.end8]
- node: BB4
=> [ local ] weight = 2147483648, succ = BB6[select.end8]
=> mass: 6000000000000000
=> assign 6000000000000000 (0000000000000000) to BB6[select.end8]
- node: BB6[select.end8]
=> mass: ffffffffffffffff
float-to-int: min = 0.375, max = 1.0, factor = 21.33333333
- BB0[entry]: float = 1.0, scaled = 21.33333333, int = 21
- BB2[select.false]: float = 0.625, scaled = 13.33333333, int = 13
- BB1: float = 0.375, scaled = 8.0, int = 8
- BB3[select.end]: float = 1.0, scaled = 21.33333333, int = 21
- BB5[select.false9]: float = 0.625, scaled = 13.33333333, int = 13
- BB4: float = 0.375, scaled = 8.0, int = 8
- BB6[select.end8]: float = 1.0, scaled = 21.33333333, int = 21
block-frequency-info: _Z11testIndCallc
- BB0[entry]: float = 1.0, int = 21
- BB1: float = 0.375, int = 8
- BB2[select.false]: float = 0.625, int = 13
- BB3[select.end]: float = 1.0, int = 21
- BB4: float = 0.375, int = 8
- BB5[select.false9]: float = 0.625, int = 13
- BB6[select.end8]: float = 1.0, int = 21
Looking for trivial roots
Found a new trivial root: %bb.6
Last visited node: %bb.5
Looking for non-trivial roots
Total: 7, Num: 8
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.6
3: %bb.4
4: %bb.3
5: %bb.1
6: %bb.0
7: %bb.2
8: %bb.5
Found roots: %bb.6
Pre-computing triangle chains.
Selecting best successor for: %bb.0 ('entry')
Candidate: %bb.1 (''), probability: 0x30000000 / 0x80000000 = 37.50%
Setting it as best candidate
Candidate: %bb.2 ('select.false'), probability: 0x50000000 / 0x80000000 = 62.50%
Setting it as best candidate
Selected: %bb.2 ('select.false')
Merging from %bb.0 ('entry') to %bb.2 ('select.false')
Selecting best successor for: %bb.2 ('select.false')
Not a candidate: %bb.3 ('select.end') -> 0x80000000 / 0x80000000 = 100.00% (prob) (non-cold CFG conflict)
%bb.1 ('') -> 0.380952381 (freq)
Merging from %bb.2 ('select.false') to %bb.1 ('')
Selecting best successor for: %bb.1 ('')
Candidate: %bb.3 ('select.end'), probability: 0x80000000 / 0x80000000 = 100.00%
Setting it as best candidate
Selected: %bb.3 ('select.end')
Merging from %bb.1 ('') to %bb.3 ('select.end')
Selecting best successor for: %bb.3 ('select.end')
Candidate: %bb.4 (''), probability: 0x30000000 / 0x80000000 = 37.50%
Setting it as best candidate
Candidate: %bb.5 ('select.false9'), probability: 0x50000000 / 0x80000000 = 62.50%
Setting it as best candidate
Selected: %bb.5 ('select.false9')
Merging from %bb.3 ('select.end') to %bb.5 ('select.false9')
Selecting best successor for: %bb.5 ('select.false9')
Not a candidate: %bb.6 ('select.end8') -> 0x80000000 / 0x80000000 = 100.00% (prob) (non-cold CFG conflict)
%bb.4 ('') -> 0.380952381 (freq)
Merging from %bb.5 ('select.false9') to %bb.4 ('')
Selecting best successor for: %bb.4 ('')
Candidate: %bb.6 ('select.end8'), probability: 0x80000000 / 0x80000000 = 100.00%
Setting it as best candidate
Selected: %bb.6 ('select.end8')
Merging from %bb.4 ('') to %bb.6 ('select.end8')
Selecting best successor for: %bb.6 ('select.end8')
Finished forming chain for header block %bb.0 ('entry')
[MBP] Function: _Z11testIndCallc
Placing chain %bb.0 ('entry')
... %bb.2 ('select.false')
Updating terminators on %bb.0
... %bb.1 ('')
Updating terminators on %bb.2
... %bb.3 ('select.end')
Updating terminators on %bb.1
... %bb.5 ('select.false9')
Updating terminators on %bb.3
... %bb.4 ('')
Updating terminators on %bb.5
... %bb.6 ('select.end8')
Updating terminators on %bb.4
TryTailMergeBlocks: %bb.2, %bb.1
with successor %bb.3
which has fall-through from %bb.1
Looking for common tails of at least 3 instructions
TryTailMergeBlocks: %bb.5, %bb.4
with successor %bb.6
which has fall-through from %bb.4
Looking for common tails of at least 3 instructions
***** BranchRelaxation *****
Basic blocks before relaxation
%bb.0 offset=00000000 size=0x51
%bb.1 offset=00000051 size=0xf
%bb.2 offset=00000060 size=0xc
%bb.3 offset=0000006c size=0x30
%bb.4 offset=0000009c size=0x9
%bb.5 offset=000000a5 size=0x6
%bb.6 offset=000000ab size=0x7b
Basic blocks after relaxation
%bb.0 offset=00000000 size=0x51
%bb.1 offset=00000051 size=0xf
%bb.2 offset=00000060 size=0xc
%bb.3 offset=0000006c size=0x30
%bb.4 offset=0000009c size=0x9
%bb.5 offset=000000a5 size=0x6
%bb.6 offset=000000ab size=0x7b
********** COMPUTING STACKMAP LIVENESS: _Z11testIndCallc **********
Debug Range Extension
block-frequency: _ZN4SubAD0Ev
=============================
reverse-post-order-traversal
- 0: BB0[entry]
loop-detection
compute-mass-in-function
- node: BB0[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB0[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubAD0Ev
- BB0[entry]: float = 1.0, int = 8
Looking for trivial roots
Found a new trivial root: %bb.0
Last visited node: %bb.0
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.0
Found roots: %bb.0
***** BranchRelaxation *****
Basic blocks before relaxation
%bb.0 offset=00000000 size=0x6
Basic blocks after relaxation
%bb.0 offset=00000000 size=0x6
********** COMPUTING STACKMAP LIVENESS: _ZN4SubAD0Ev **********
Debug Range Extension
block-frequency: _ZN4SubA2fnEv
==============================
reverse-post-order-traversal
- 0: BB0[entry]
loop-detection
compute-mass-in-function
- node: BB0[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB0[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubA2fnEv
- BB0[entry]: float = 1.0, int = 8
Looking for trivial roots
Found a new trivial root: %bb.0
Last visited node: %bb.0
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.0
Found roots: %bb.0
***** BranchRelaxation *****
Basic blocks before relaxation
%bb.0 offset=00000000 size=0x3
Basic blocks after relaxation
%bb.0 offset=00000000 size=0x3
********** COMPUTING STACKMAP LIVENESS: _ZN4SubA2fnEv **********
Debug Range Extension
block-frequency: _ZN4BaseD2Ev
=============================
reverse-post-order-traversal
- 0: BB0[entry]
loop-detection
compute-mass-in-function
- node: BB0[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB0[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4BaseD2Ev
- BB0[entry]: float = 1.0, int = 8
Looking for trivial roots
Found a new trivial root: %bb.0
Last visited node: %bb.0
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.0
Found roots: %bb.0
***** BranchRelaxation *****
Basic blocks before relaxation
%bb.0 offset=00000000 size=0x3
Basic blocks after relaxation
%bb.0 offset=00000000 size=0x3
********** COMPUTING STACKMAP LIVENESS: _ZN4BaseD2Ev **********
Debug Range Extension
block-frequency: _ZN4SubBD0Ev
=============================
reverse-post-order-traversal
- 0: BB0[entry]
loop-detection
compute-mass-in-function
- node: BB0[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB0[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubBD0Ev
- BB0[entry]: float = 1.0, int = 8
Looking for trivial roots
Found a new trivial root: %bb.0
Last visited node: %bb.0
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.0
Found roots: %bb.0
***** BranchRelaxation *****
Basic blocks before relaxation
%bb.0 offset=00000000 size=0x6
Basic blocks after relaxation
%bb.0 offset=00000000 size=0x6
********** COMPUTING STACKMAP LIVENESS: _ZN4SubBD0Ev **********
Debug Range Extension
block-frequency: _ZN4SubB2fnEv
==============================
reverse-post-order-traversal
- 0: BB0[entry]
loop-detection
compute-mass-in-function
- node: BB0[entry]
=> mass: ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 8.0
- BB0[entry]: float = 1.0, scaled = 8.0, int = 8
block-frequency-info: _ZN4SubB2fnEv
- BB0[entry]: float = 1.0, int = 8
Looking for trivial roots
Found a new trivial root: %bb.0
Last visited node: %bb.0
Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.0
Found roots: %bb.0
***** BranchRelaxation *****
Basic blocks before relaxation
%bb.0 offset=00000000 size=0x3
Basic blocks after relaxation
%bb.0 offset=00000000 size=0x3
********** COMPUTING STACKMAP LIVENESS: _ZN4SubB2fnEv **********
Debug Range Extension
2 errors generated.
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