- [Compilation] Continue to push the minimum framework content to the official repository to meet the goal of "successful compilation on RISC-V" (including cross-compilation).
Basic definition of RISC-VDone, commit@@b0848b5Architecture-dependent basic functions and definitions,Done https://github.com/DynamoRIO/dynamorio/commit/0bac803f91d5b67d91666fb2330c9b68a9892e13 https://github.com/DynamoRIO/dynamorio/commit/91f3aa0a804904a40adb9b1b8bd79f21ae9f0428 https://github.com/DynamoRIO/dynamorio/commit/04dbe293311fffe60e73c6a0cf9013d31109b7e6core/arch
directory- minimum support for atomic operation implementation,
atomic_exports.h
file - the basic files required by riscv64 are in the
riscv64
directory, refer to @cc19b1a, the relevant content of decode/encode/opcode/instr is refactored to thecore/ir
directory, and *_shared.asm is refactored tocore/drlibc
, please be aware - minimal support for generating stubs related, patch_branches and load/save register related functions,
arch{,_exports}.h
,riscv64/emit_utils.c
files - modify other files in this directory to make the compilation pass, refer to @793392d
- minimum support for atomic operation implementation,
Architecture-dependent drlibc related content,Done https://github.com/DynamoRIO/dynamorio/commit/0bac803f91d5b67d91666fb2330c9b68a9892e13core/drlibc
directory- define a minimal framework for architecture-specific assembly and trampoline code shared with non-core DR libraries, file
drlibc_riscv64.asm
, refer to @cc19b1a *_shared.asm file - solve other problems that may be encountered when compiling
- define a minimal framework for architecture-specific assembly and trampoline code shared with non-core DR libraries, file
- Architecture-dependent Instruction Representation related content,
core/ir
directoryopcode and instruction create macro/information query functions and other related minimal frameworksDone, commit@@50b5c7cencoder/decoder related minimal framework,Done https://github.com/DynamoRIO/dynamorio/commit/837c98ac0374141871cffa930534f71073d96109core/ir{/riscv64}/{d,en}coder*
related filesrelated definitions and logic for outputting instruction content to files/buffers,probably done https://github.com/DynamoRIO/dynamorio/commit/837c98ac0374141871cffa930534f71073d96109core/ir{/riscv64}/disassemble*
related files
The core library,Done https://github.com/DynamoRIO/dynamorio/commit/0bac803f91d5b67d91666fb2330c9b68a9892e13core/lib
directory, most of the architecture-dependent content has been completed in the RISC-V basic definition, but there are still omissions- definition of RISC-V related registers under
instrument.c
file
- definition of RISC-V related registers under
Some architecture-dependent logic underDone https://github.com/DynamoRIO/dynamorio/commit/0bac803f91d5b67d91666fb2330c9b68a9892e13core/unix
, refer to @793392d- Some other architecture-dependent undefined logic and other definitions in the
core
directory, refer to @793392d Extensions underprobably done https://github.com/DynamoRIO/dynamorio/commit/8092f319fe7ea7b728dc968a25c771e80a52f912ext
, the following requires adapt to RISC-V- drbbdup/drbbdup.c
- drreg/drreg.c
- drstatecmp/drstatecmp.c
- drsyms
- drutil/drutil.c
- drwrap
- drx
Client drcachesim support,clients/drcachesim
directory, please refer to @fe1024cSupport for sample tools,probably done commit@@5e10394api/samples
directory, refer to @793392dCMakeLists.txt related contentDone https://github.com/DynamoRIO/dynamorio/commit/25c81f80c7cf8173caf1cde4293cabb603fd2b16 https://github.com/DynamoRIO/dynamorio/commit/6c97e8a4bdabe64a32df7409526cb3e681ac840d https://github.com/DynamoRIO/dynamorio/commit/f4b6b9665fcd0db6052558d17d54d43bd303da0e
- Use CI to compile and test on RISC-V
- [Function] Realize the instructions that can use the built-in sample tool under
api/samples
to observe and manipulate its execution instructions of a simple program. The specific work is to supplement and repair the above-mentioned minimization framework. During the implementation process, Please refer to the porting process of AArch64 #1569, and related summary AArch64 port:core/arch
- Implement atomic operations
- Implement memory copy/set/move related asm
- Implement the functions required by the clients
- Others (waiting for improvement)
core/drlibc
- Determine what RISC-V supports under
drlibc_module_elf.c
- Others (waiting for improvement)
- Determine what RISC-V supports under
core/fragment.h
frag isa mode?- under
core/ir
- Implement encoder/decoder, decode table? refer to #2626
- implements basic decoder
- https://github.com/DynamoRIO/dynamorio/commit/7bc0b6ad19a398f03321fc7a2465ac0f3a11e854
- https://github.com/DynamoRIO/dynamorio/commit/29125fcb08178b8dd73e8a9f54447e67484100e7
- https://github.com/DynamoRIO/dynamorio/commit/449df27adb1ae9ae25975fa25bb2b3cb425a8faf
- https://github.com/DynamoRIO/dynamorio/commit/4513e2041e0666db00553f6c95af74fa27bc2fc3
- https://github.com/DynamoRIO/dynamorio/commit/1e57d270dad62298a89ad0a5827d8b7c1d9aea58
- Implement functions related to responding to query information,
instr*.{c,h}
- Others (waiting for improvement)
- Implement encoder/decoder, decode table? refer to #2626
- under
core/lib
- RISC-V support under dr_annotations_asm.h (low priority?)
- statsx.h for additional RISC-V related content
- Others (waiting for improvement)
- under
core/unix
- Implement thread-local storage
tls.h
tls_linux_riscv64.c
- Adapting system calls
include/syscall.h
include/syscall_linux_riscv64.h
- Implement signal processing
signal.c
signal_linux_riscv64.c
signal_private.h
- Others (waiting for improvement)
- Implement thread-local storage
ext
clients
- Others (waiting for improvement)
- Write test cases under RISC-V and use CI to test their functions
- While implementing the function, you can write the corresponding unit test according to the situation
- Improve support for RISC-V for more complex programs
Last active
February 5, 2023 08:51
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