i2c_clock.c

/*
  enable_task outputs a 38.400MHz clock on GPIO 0.

  Writing 0 into its queue will turn this output off
  Writing 1 into its queue will turn the output on

*/

static void enable_task(void *ignore)
{
  uint8_t state;

  periph_module_enable(PERIPH_I2S0_MODULE);

  rtc_clk_apll_enable(1, 31 /*sdm0*/, 133 /*sdm1*/, 7 /*sdm2*/, 1 /*odiv*/);

  WRITE_PERI_REG(I2S_CLKM_CONF_REG(0),
                    I2S_CLKA_ENA | // Use APLL_CLK
                    //I2S_CLK_EN | // Use PLL_D2_CLK
                    (0 << I2S_CLKM_DIV_A_S) |
                    (0 << I2S_CLKM_DIV_B_S) |
                    (1 << I2S_CLKM_DIV_NUM_S)); // Divide by 2

      // Output I2C clock to CLK_OUT1
      // Refer to "Register 4.33: IO_MUX_PIN_CTRL"" description in "ESP32 Technical Reference Manual"
      WRITE_PERI_REG(PIN_CTRL, (0x0 << CLK_OUT1_S) | (0xF << CLK_OUT2_S) | (0xF << CLK_OUT3_S));

      // Output CLK_OUT1 on GPIO0
      PIN_FUNC_SELECT(GPIO_PIN_REG_0, FUNC_GPIO0_CLK_OUT1);
      PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO17_U, FUNC_GPIO17_EMAC_CLK_OUT_180);

      ESP_LOGD("EnableTask","*** Startup *** Enabled PLL Output");

  while(1)
  {
        if(xQueueReceive(enable_evt_queue, &state, portMAX_DELAY)) {
          if(state == 1)
          {
            WRITE_PERI_REG(I2S_CLKM_CONF_REG(0),
                              I2S_CLKA_ENA | // Use APLL_CLK
                              //I2S_CLK_EN | // Use PLL_D2_CLK
                              (0 << I2S_CLKM_DIV_A_S) |
                              (0 << I2S_CLKM_DIV_B_S) |
                              (1 << I2S_CLKM_DIV_NUM_S)); // Divide by 1
            ESP_LOGD("EnableTask","Enabled PLL Output");
          }
          else if(state == 0)
          {
            WRITE_PERI_REG(I2S_CLKM_CONF_REG(0),
                              I2S_CLKA_ENA | // Use APLL_CLK
                              //I2S_CLK_EN | // Use PLL_D2_CLK
                              (0 << I2S_CLKM_DIV_A_S) |
                              (0 << I2S_CLKM_DIV_B_S) |
                              (0 << I2S_CLKM_DIV_NUM_S)); // Divide by 0
            ESP_LOGD("EnableTask","Disabled PLL Output");
          }
        }
  }

}

May I ask how to implement a similar function on ESP32-S3? It seems that rtc_clk_apll_enable is not included in the hal.