test.v

module top (
	input  clk,
	output LED0,
	output LED1,
	output LED2,
	output LED3,
	output LED4,
	output LED5,
	output LED6,
	output LED7
);

    wire [7:0] WDATA;
    wire [7:0] MASK;
    wire [8:0] WADDR;
    wire       WE;
    wire       WCLK;
    wire       WCLKE;
    wire [7:0] RDATA;
    wire [8:0] RADDR;
    wire       RE;
    wire       RCLK;
    wire       RCLKE;

    SB_RAM40_4K #(
        .WRITE_MODE(1),
        .READ_MODE(1),
        .INIT_0(256'h000102030405060708090A0B0C0D0E0F000102030405060708090A0B0C0D0E0F)
    ) ram40_4kinst_physical(
        .RDATA(RDATA),
        .RADDR(RADDR),
        .WADDR(WADDR),
        .MASK(MASK),
        .WDATA(WDATA),
        .RCLKE(RCLKE),
        .RCLK(RCLK),
        .RE(RE),
        .WCLKE(WCLKE),
        .WCLK(WCLK),
        .WE(WE)
    );

    localparam LOG2DELAY = 24;

    reg [LOG2DELAY-1:0] delay = 0;
    reg inclk;
    
    assign RCLK = clk;
    assign WCLK = 0;
    
    assign WCLKE = 0;
    assign RCLKE = 1;
    assign WE    = 0;
    assign RE    = 1;
    
    reg [8:0] count = 0;
    
    assign RADDR = count;

	always@(posedge clk) begin
        delay <= delay + 1;
	end
    
    always@(posedge delay[LOG2DELAY-1]) begin
        inclk <= inclk + 1;
        count <= count + 1;
    end

	assign {LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7} = RDATA;
endmodule