Test.vhdl

-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.silmarils_firmware_types.all;

entity silmarils_firmware is
  port(-- clock
       clock                            : in std_logic;
       -- asynchronous reset: active high
       reset                            : in std_logic;
       ctrlAxi_arvalid                : in std_logic_vector(0 downto 0);
       ctrlAxi_arid            : in std_logic_vector(11 downto 0);
       ctrlAxi_araddr          : in std_logic_vector(31 downto 0);
       ctrlAxi_arlen           : in std_logic_vector(7 downto 0);
       ctrlAxi_arsize          : in std_logic_vector(2 downto 0);
       ctrlAxi_arburst         : in std_logic_vector(1 downto 0);
       ctrlAxi_arlock          : in std_logic_vector(1 downto 0);
       ctrlAxi_arcache         : in std_logic_vector(3 downto 0);
       ctrlAxi_arprot          : in std_logic_vector(2 downto 0);
       ctrlAxi_arqos           : in std_logic_vector(3 downto 0);
       ctrlAxi_arregion        : in std_logic_vector(3 downto 0);
       ctrlAxi_rready                 : in std_logic_vector(0 downto 0);
       ctrlAxi_awvalid                : in std_logic_vector(0 downto 0);
       ctrlAxi_awid            : in std_logic_vector(11 downto 0);
       ctrlAxi_awaddr          : in std_logic_vector(31 downto 0);
       ctrlAxi_awlen           : in std_logic_vector(7 downto 0);
       ctrlAxi_awsize          : in std_logic_vector(2 downto 0);
       ctrlAxi_awburst         : in std_logic_vector(1 downto 0);
       ctrlAxi_awlock          : in std_logic_vector(1 downto 0);
       ctrlAxi_awcache         : in std_logic_vector(3 downto 0);
       ctrlAxi_awprot          : in std_logic_vector(2 downto 0);
       ctrlAxi_awqos           : in std_logic_vector(3 downto 0);
       ctrlAxi_awregion        : in std_logic_vector(3 downto 0);
       ctrlAxi_wvalid                 : in std_logic_vector(0 downto 0);
       ctrlAxi_wid              : in std_logic_vector(11 downto 0);
       ctrlAxi_wdata            : in std_logic_vector(31 downto 0);
       ctrlAxi_wstrb            : in std_logic_vector(3 downto 0);
       ctrlAxi_wlast            : in std_logic_vector(0 downto 0);
       ctrlAxi_bready                 : in std_logic_vector(0 downto 0);
       memAxi_arready                : in std_logic_vector(0 downto 0);
       memAxi_rvalid                 : in std_logic_vector(0 downto 0);
       memAxi_rid              : in std_logic_vector(5 downto 0);
       memAxi_rdata            : in std_logic_vector(31 downto 0);
       memAxi_rresp            : in std_logic_vector(1 downto 0);
       memAxi_rlast            : in std_logic_vector(0 downto 0);
       memAxi_awready                : in std_logic_vector(0 downto 0);
       memAxi_wready                 : in std_logic_vector(0 downto 0);
       memAxi_bvalid                 : in std_logic_vector(0 downto 0);
       memAxi_bid              : in std_logic_vector(5 downto 0);
       memAxi_bresp            : in std_logic_vector(1 downto 0);
       adcIn_SDOA                       : in boolean;
       adcIn_SDOB                       : in boolean;
       adcIn_BUSY                       : in boolean;
       ctrlAxi_arready       : out std_logic_vector(0 downto 0);
       ctrlAxi_rvalid        : out std_logic_vector(0 downto 0);
       ctrlAxi_rid     : out std_logic_vector(11 downto 0);
       ctrlAxi_rdata   : out std_logic_vector(31 downto 0);
       ctrlAxi_rresp   : out std_logic_vector(1 downto 0);
       ctrlAxi_rlast   : out std_logic_vector(0 downto 0);
       ctrlAxi_awready       : out std_logic_vector(0 downto 0);
       ctrlAxi_wready        : out std_logic_vector(0 downto 0);
       ctrlAxi_bvalid        : out std_logic_vector(0 downto 0);
       ctrlAxi_bid     : out std_logic_vector(11 downto 0);
       ctrlAxi_bresp   : out std_logic_vector(1 downto 0);
       memAxi_arvalid         : out std_logic_vector(0 downto 0);
       memAxi_arid     : out std_logic_vector(5 downto 0);
       memAxi_araddr   : out std_logic_vector(31 downto 0);
       memAxi_arlen    : out std_logic_vector(7 downto 0);
       memAxi_arsize   : out std_logic_vector(2 downto 0);
       memAxi_arburst  : out std_logic_vector(1 downto 0);
       memAxi_arlock   : out std_logic_vector(1 downto 0);
       memAxi_arcache  : out std_logic_vector(3 downto 0);
       memAxi_arprot   : out std_logic_vector(2 downto 0);
       memAxi_arqos    : out std_logic_vector(3 downto 0);
       memAxi_arregion : out std_logic_vector(3 downto 0);
       memAxi_rready          : out std_logic_vector(0 downto 0);
       memAxi_awvalid         : out std_logic_vector(0 downto 0);
       memAxi_awid     : out std_logic_vector(5 downto 0);
       memAxi_awaddr   : out std_logic_vector(31 downto 0);
       memAxi_awlen    : out std_logic_vector(7 downto 0);
       memAxi_awsize   : out std_logic_vector(2 downto 0);
       memAxi_awburst  : out std_logic_vector(1 downto 0);
       memAxi_awlock   : out std_logic_vector(1 downto 0);
       memAxi_awcache  : out std_logic_vector(3 downto 0);
       memAxi_awprot   : out std_logic_vector(2 downto 0);
       memAxi_awqos    : out std_logic_vector(3 downto 0);
       memAxi_awregion : out std_logic_vector(3 downto 0);
       memAxi_wvalid          : out std_logic_vector(0 downto 0);
       memAxi_wid       : out std_logic_vector(5 downto 0);
       memAxi_wdata     : out std_logic_vector(31 downto 0);
       memAxi_wstrb     : out std_logic_vector(3 downto 0);
       memAxi_wlast     : out std_logic_vector(0 downto 0);
       memAxi_bready          : out std_logic_vector(0 downto 0);
       irq                      : out boolean;
       aregEn                   : out boolean;
       status_running           : out boolean;
       status_ind1              : out boolean;
       status_ind2              : out boolean;
       status_error             : out boolean;
       unitAOut_dio             : out unsigned(31 downto 0);
       unitAOut_dacOut_SYNC     : out boolean;
       unitAOut_dacOut_SDI      : out boolean;
       unitAOut_dacOut_SCLK     : out boolean;
       unitAOut_dacOut_LDACn    : out boolean;
       unitAOut_dacOut_RESETn   : out boolean;
       unitAOut_dacOut_RSTSET   : out boolean;
       unitAOut_dacOut_GAIN     : out boolean;
       unitBOut_dio             : out unsigned(31 downto 0);
       unitBOut_dacOut_SYNC     : out boolean;
       unitBOut_dacOut_SDI      : out boolean;
       unitBOut_dacOut_SCLK     : out boolean;
       unitBOut_dacOut_LDACn    : out boolean;
       unitBOut_dacOut_RESETn   : out boolean;
       unitBOut_dacOut_RSTSET   : out boolean;
       unitBOut_dacOut_GAIN     : out boolean;
       adcOut_CSn               : out boolean;
       adcOut_CONVST            : out boolean;
       adcOut_SCLK              : out boolean;
       adcOut_SDI               : out boolean;
       adcOut_M0                : out boolean);
end;

architecture structural of silmarils_firmware is
  signal a8              : silmarils_firmware_types.axiout_0;
  signal a9              : silmarils_firmware_types.axiin_0;
  signal a10             : boolean;
  signal a11             : boolean;
  signal a12             : silmarils_firmware_types.statusindicators;
  signal a13             : silmarils_firmware_types.unitoutputs;
  signal a14             : silmarils_firmware_types.unitoutputs;
  signal a15             : silmarils_firmware_types.adcout;
  signal ds              : silmarils_firmware_types.tup8;
  signal \#ds_app_arg\   : silmarils_firmware_types.axiout_0;
  signal \#ds_app_arg_0\ : silmarils_firmware_types.axiin_0;
  signal c2              : boolean;
  signal d2              : boolean;
  signal e2              : silmarils_firmware_types.statusindicators;
  signal f3              : silmarils_firmware_types.unitoutputs;
  signal g2              : silmarils_firmware_types.unitoutputs;
  signal h2              : silmarils_firmware_types.adcout;
  signal a2              : silmarils_firmware_types.axiout;
  signal b1              : silmarils_firmware_types.axiin_1;
  signal ds_0            : silmarils_firmware_types.tup8_0;
  signal \#ds_app_arg_1\ : silmarils_firmware_types.axiin;
  signal \#ds_app_arg_2\ : silmarils_firmware_types.axiout_1;
  signal ctrlAxiIn       : silmarils_firmware_types.axiin_2;
  signal memAxiOut       : silmarils_firmware_types.axiout_2;
  signal adcIn           : silmarils_firmware_types.adcin;
  signal ds_0_fun_arg    : silmarils_firmware_types.product;
  signal outputs         : silmarils_firmware_types.tup8;
  signal ctrlAxiOut      : silmarils_firmware_types.axiout_0;
  signal rPort           : silmarils_firmware_types.rport;
  signal bPort           : silmarils_firmware_types.bport;
  signal memAxiIn        : silmarils_firmware_types.axiin_0;
  signal arPort          : silmarils_firmware_types.arport;
  signal awPort          : silmarils_firmware_types.awport;
  signal wPort           : silmarils_firmware_types.wport;
  signal status          : silmarils_firmware_types.statusindicators;
  signal unitAOut        : silmarils_firmware_types.unitoutputs;
  signal dacOut          : silmarils_firmware_types.dacout;
  signal unitBOut        : silmarils_firmware_types.unitoutputs;
  signal dacOut          : silmarils_firmware_types.dacout;
  signal adcOut          : silmarils_firmware_types.adcout;
begin
  ctrlAxiIn <= ( axiin_2_sel0 => ctrlAxi_arvalid
               , axiin_2_sel1 => ( arport_0_sel0 => ctrlAxi_arid
               , arport_0_sel1 => ctrlAxi_araddr
               , arport_0_sel2 => ctrlAxi_arlen
               , arport_0_sel3 => ctrlAxi_arsize
               , arport_0_sel4 => ctrlAxi_arburst
               , arport_0_sel5 => ctrlAxi_arlock
               , arport_0_sel6 => ctrlAxi_arcache
               , arport_0_sel7 => ctrlAxi_arprot
               , arport_0_sel8 => ctrlAxi_arqos
               , arport_0_sel9 => ctrlAxi_arregion )
               , axiin_2_sel2 => ctrlAxi_rready
               , axiin_2_sel3 => ctrlAxi_awvalid
               , axiin_2_sel4 => ( awport_0_sel0 => ctrlAxi_awid
               , awport_0_sel1 => ctrlAxi_awaddr
               , awport_0_sel2 => ctrlAxi_awlen
               , awport_0_sel3 => ctrlAxi_awsize
               , awport_0_sel4 => ctrlAxi_awburst
               , awport_0_sel5 => ctrlAxi_awlock
               , awport_0_sel6 => ctrlAxi_awcache
               , awport_0_sel7 => ctrlAxi_awprot
               , awport_0_sel8 => ctrlAxi_awqos
               , awport_0_sel9 => ctrlAxi_awregion )
               , axiin_2_sel5 => ctrlAxi_wvalid
               , axiin_2_sel6 => ( wport_0_sel0 => ctrlAxi_wid
               , wport_0_sel1 => ctrlAxi_wdata
               , wport_0_sel2 => ctrlAxi_wstrb
               , wport_0_sel3 => ctrlAxi_wlast )
               , axiin_2_sel7 => ctrlAxi_bready );

  memAxiOut <= ( axiout_2_sel0 => memAxi_arready
               , axiout_2_sel1 => memAxi_rvalid
               , axiout_2_sel2 => ( rport_0_sel0 => memAxi_rid
               , rport_0_sel1 => memAxi_rdata
               , rport_0_sel2 => memAxi_rresp
               , rport_0_sel3 => memAxi_rlast )
               , axiout_2_sel3 => memAxi_awready
               , axiout_2_sel4 => memAxi_wready
               , axiout_2_sel5 => memAxi_bvalid
               , axiout_2_sel6 => ( bport_0_sel0 => memAxi_bid
               , bport_0_sel1 => memAxi_bresp ) );

  adcIn <= ( adcin_sel0 => adcIn_SDOA
           , adcin_sel1 => adcIn_SDOB
           , adcin_sel2 => adcIn_BUSY );

  outputs <= ( tup8_sel0 => a8
             , tup8_sel1 => a9
             , tup8_sel2 => a10
             , tup8_sel3 => a11
             , tup8_sel4 => a12
             , tup8_sel5 => a13
             , tup8_sel6 => a14
             , tup8_sel7 => a15 );

  a8 <= ds.tup8_sel0;

  a9 <= ds.tup8_sel1;

  a10 <= ds.tup8_sel2;

  a11 <= ds.tup8_sel3;

  a12 <= ds.tup8_sel4;

  a13 <= ds.tup8_sel5;

  a14 <= ds.tup8_sel6;

  a15 <= ds.tup8_sel7;

  ds <= ( tup8_sel0 => \#ds_app_arg\
        , tup8_sel1 => \#ds_app_arg_0\
        , tup8_sel2 => c2
        , tup8_sel3 => d2
        , tup8_sel4 => e2
        , tup8_sel5 => f3
        , tup8_sel6 => g2
        , tup8_sel7 => h2 );

  silmarilsfirmware_toaxiout_ds_app_arg : entity silmarilsfirmware_toaxiout
    port map
      (result => \#ds_app_arg\, ds     => a2);

  silmarilsfirmware_toaxiin_ds_app_arg_0 : entity silmarilsfirmware_toaxiin
    port map
      (result => \#ds_app_arg_0\, ds     => b1);

  c2 <= ds_0.tup8_0_sel2;

  d2 <= ds_0.tup8_0_sel3;

  e2 <= ds_0.tup8_0_sel4;

  f3 <= ds_0.tup8_0_sel5;

  g2 <= ds_0.tup8_0_sel6;

  h2 <= ds_0.tup8_0_sel7;

  a2 <= ds_0.tup8_0_sel0;

  b1 <= ds_0.tup8_0_sel1;

  ds_0_fun_arg <= ( product_sel0 => clock
                  , product_sel1 => reset );

  controller_controller_ds_0 : entity controller_controller
    port map
      ( result      => ds_0
      , \$d(%,%)\   => ds_0_fun_arg
      , \ctrlAxiIn\ => \#ds_app_arg_1\
      , \memAxiIn\  => \#ds_app_arg_2\
      , \adcIn\     => adcIn );

  axi_port_fromaxiin_ds_app_arg_1 : entity axi_port_fromaxiin
    port map
      ( \#case_alt\ => \#ds_app_arg_1\
      , ds          => ctrlAxiIn );

  axi_port_fromaxiout_ds_app_arg_2 : entity axi_port_fromaxiout
    port map
      ( \#case_alt\ => \#ds_app_arg_2\
      , ds          => memAxiOut );

  ctrlAxiOut <= outputs.tup8_sel0;

  memAxiIn <= outputs.tup8_sel1;

  irq <= outputs.tup8_sel2;

  aregEn <= outputs.tup8_sel3;

  status <= outputs.tup8_sel4;

  unitAOut <= outputs.tup8_sel5;

  unitBOut <= outputs.tup8_sel6;

  adcOut <= outputs.tup8_sel7;

  ctrlAxi_arready <= ctrlAxiOut.axiout_0_sel0;

  ctrlAxi_rvalid <= ctrlAxiOut.axiout_0_sel1;

  rPort <= ctrlAxiOut.axiout_0_sel2;

  ctrlAxi_awready <= ctrlAxiOut.axiout_0_sel3;

  ctrlAxi_wready <= ctrlAxiOut.axiout_0_sel4;

  ctrlAxi_bvalid <= ctrlAxiOut.axiout_0_sel5;

  bPort <= ctrlAxiOut.axiout_0_sel6;

  ctrlAxi_rid <= rPort.rport_sel0;

  ctrlAxi_rdata <= rPort.rport_sel1;

  ctrlAxi_rresp <= rPort.rport_sel2;

  ctrlAxi_rlast <= rPort.rport_sel3;

  ctrlAxi_bid <= bPort.bport_sel0;

  ctrlAxi_bresp <= bPort.bport_sel1;

  memAxi_arvalid <= memAxiIn.axiin_0_sel0;

  arPort <= memAxiIn.axiin_0_sel1;

  memAxi_rready <= memAxiIn.axiin_0_sel2;

  memAxi_awvalid <= memAxiIn.axiin_0_sel3;

  awPort <= memAxiIn.axiin_0_sel4;

  memAxi_wvalid <= memAxiIn.axiin_0_sel5;

  wPort <= memAxiIn.axiin_0_sel6;

  memAxi_bready <= memAxiIn.axiin_0_sel7;

  memAxi_arid <= arPort.arport_sel0;

  memAxi_araddr <= arPort.arport_sel1;

  memAxi_arlen <= arPort.arport_sel2;

  memAxi_arsize <= arPort.arport_sel3;

  memAxi_arburst <= arPort.arport_sel4;

  memAxi_arlock <= arPort.arport_sel5;

  memAxi_arcache <= arPort.arport_sel6;

  memAxi_arprot <= arPort.arport_sel7;

  memAxi_arqos <= arPort.arport_sel8;

  memAxi_arregion <= arPort.arport_sel9;

  memAxi_awid <= awPort.awport_sel0;

  memAxi_awaddr <= awPort.awport_sel1;

  memAxi_awlen <= awPort.awport_sel2;

  memAxi_awsize <= awPort.awport_sel3;

  memAxi_awburst <= awPort.awport_sel4;

  memAxi_awlock <= awPort.awport_sel5;

  memAxi_awcache <= awPort.awport_sel6;

  memAxi_awprot <= awPort.awport_sel7;

  memAxi_awqos <= awPort.awport_sel8;

  memAxi_awregion <= awPort.awport_sel9;

  memAxi_wid <= wPort.wport_sel0;

  memAxi_wdata <= wPort.wport_sel1;

  memAxi_wstrb <= wPort.wport_sel2;

  memAxi_wlast <= wPort.wport_sel3;

  status_running <= status.statusindicators_sel0;

  status_ind1 <= status.statusindicators_sel1;

  status_ind2 <= status.statusindicators_sel2;

  status_error <= status.statusindicators_sel3;

  unitAOut_dio <= unitAOut.unitsel0;

  dacOut <= unitAOut.unitsel1;

  unitAOut_dacOut_SYNC <= dacOut.dacout_sel0;

  unitAOut_dacOut_SDI <= dacOut.dacout_sel1;

  unitAOut_dacOut_SCLK <= dacOut.dacout_sel2;

  unitAOut_dacOut_LDACn <= dacOut.dacout_sel3;

  unitAOut_dacOut_RESETn <= dacOut.dacout_sel4;

  unitAOut_dacOut_RSTSET <= dacOut.dacout_sel5;

  unitAOut_dacOut_GAIN <= dacOut.dacout_sel6;

  unitBOut_dio <= unitBOut.unitsel0;

  dacOut <= unitBOut.unitsel1;

  unitBOut_dacOut_SYNC <= dacOut.dacout_sel0;

  unitBOut_dacOut_SDI <= dacOut.dacout_sel1;

  unitBOut_dacOut_SCLK <= dacOut.dacout_sel2;

  unitBOut_dacOut_LDACn <= dacOut.dacout_sel3;

  unitBOut_dacOut_RESETn <= dacOut.dacout_sel4;

  unitBOut_dacOut_RSTSET <= dacOut.dacout_sel5;

  unitBOut_dacOut_GAIN <= dacOut.dacout_sel6;

  adcOut_CSn <= adcOut.adcout_sel0;

  adcOut_CONVST <= adcOut.adcout_sel1;

  adcOut_SCLK <= adcOut.adcout_sel2;

  adcOut_SDI <= adcOut.adcout_sel3;

  adcOut_M0 <= adcOut.adcout_sel4;
end;