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bgamari/Test.hs

Created November 30, 2017 19:57
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Test.hs
module Hello where
import Clash.Prelude
{-# ANN maybeTest (defTop { t_name = "test"
, t_inputs = [PortName "hi"]
, t_output = PortName "out"}) #-}
maybeTest :: Signal clk (Unsigned 32) -> Signal clk (Unsigned 16) -> Signal clk (Unsigned 32)
maybeTest x y = x
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bgamari commented Nov 30, 2017 

Clash.Prelude> :verilog Hello.hs
Loading dependencies took 0.724603588s
Compiling: Hello.maybeTest
Applied 1 transformations
Normalisation took 0.001997219s
*** Exception: Clash.Netlist.Util(82): Not in normal from: no Letrec:

Λclk ->
λ(x :: Clash.Signal.Internal.Signal
         clk (Clash.Sized.Internal.Unsigned.Unsigned 32)) ->
λ(y :: Clash.Signal.Internal.Signal
         clk (Clash.Sized.Internal.Unsigned.Unsigned 16)) ->
x

Which has type:

∀ (clk :: Clash.Signal.Internal.Domain).
Clash.Signal.Internal.Signal
  clk (Clash.Sized.Internal.Unsigned.Unsigned 32)
-> Clash.Signal.Internal.Signal
     clk (Clash.Sized.Internal.Unsigned.Unsigned 16)
-> Clash.Signal.Internal.Signal
     clk (Clash.Sized.Internal.Unsigned.Unsigned 32)

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