Created
November 7, 2012 18:18
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patch to Freescale Linux kernel 2.6.38 (11.09.01) drivers/tty/serial/imx.c to allow KDB operation
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--- imx.c.orig 2012-10-16 12:05:17.288634650 -0700 | |
+++ drivers/tty/serial/imx.c 2012-11-06 15:13:33.561522579 -0800 | |
@@ -102,6 +102,7 @@ | |
#define UCR2_STPB (1<<6) /* Stop */ | |
#define UCR2_WS (1<<5) /* Word size */ | |
#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ | |
+#define UCR2_ATEN (1<<3) /* Aging Timer Enable */ | |
#define UCR2_TXEN (1<<2) /* Transmitter enabled */ | |
#define UCR2_RXEN (1<<1) /* Receiver enabled */ | |
#define UCR2_SRST (1<<0) /* SW reset */ | |
@@ -196,6 +197,12 @@ | |
struct clk *clk; | |
}; | |
+struct imx_port_ucrs { | |
+ unsigned int ucr1; | |
+ unsigned int ucr2; | |
+ unsigned int ucr3; | |
+}; | |
+ | |
#ifdef CONFIG_IRDA | |
#define USE_IRDA(sport) ((sport)->use_irda) | |
#else | |
@@ -203,6 +210,27 @@ | |
#endif | |
/* | |
+ * Save and restore functions for UCR1, UCR2 and UCR3 registers | |
+ */ | |
+static void imx_port_ucrs_save(struct uart_port *port, | |
+ struct imx_port_ucrs *ucr) | |
+{ | |
+ /* save control registers */ | |
+ ucr->ucr1 = readl(port->membase + UCR1); | |
+ ucr->ucr2 = readl(port->membase + UCR2); | |
+ ucr->ucr3 = readl(port->membase + UCR3); | |
+} | |
+ | |
+static void imx_port_ucrs_restore(struct uart_port *port, | |
+ struct imx_port_ucrs *ucr) | |
+{ | |
+ /* restore control registers */ | |
+ writel(ucr->ucr1, port->membase + UCR1); | |
+ writel(ucr->ucr2, port->membase + UCR2); | |
+ writel(ucr->ucr3, port->membase + UCR3); | |
+} | |
+ | |
+/* | |
* Handle any change of modem status signal since we were last called. | |
*/ | |
static void imx_mctrl_check(struct imx_port *sport) | |
@@ -1025,6 +1053,70 @@ | |
return ret; | |
} | |
+#if defined(CONFIG_CONSOLE_POLL) | |
+static int imx_poll_get_char(struct uart_port *port) | |
+{ | |
+ struct imx_port_ucrs old_ucr; | |
+ unsigned int status; | |
+ unsigned char c; | |
+ | |
+ /* save control registers */ | |
+ imx_port_ucrs_save(port, &old_ucr); | |
+ | |
+ /* disable interrupts */ | |
+ writel(UCR1_UARTEN, port->membase + UCR1); | |
+ writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), | |
+ port->membase + UCR2); | |
+ writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), | |
+ port->membase + UCR3); | |
+ | |
+ /* poll */ | |
+ do { | |
+ status = readl(port->membase + USR2); | |
+ } while (~status & USR2_RDR); | |
+ | |
+ /* read */ | |
+ c = readl(port->membase + URXD0); | |
+ | |
+ /* restore control registers */ | |
+ imx_port_ucrs_restore(port, &old_ucr); | |
+ | |
+ return c; | |
+} | |
+ | |
+static void imx_poll_put_char(struct uart_port *port, unsigned char c) | |
+{ | |
+ struct imx_port_ucrs old_ucr; | |
+ unsigned int status; | |
+ | |
+ /* save control registers */ | |
+ imx_port_ucrs_save(port, &old_ucr); | |
+ | |
+ /* disable interrupts */ | |
+ writel(UCR1_UARTEN, port->membase + UCR1); | |
+ writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), | |
+ port->membase + UCR2); | |
+ writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), | |
+ port->membase + UCR3); | |
+ | |
+ /* drain */ | |
+ do { | |
+ status = readl(port->membase + USR1); | |
+ } while (~status & USR1_TRDY); | |
+ | |
+ /* write */ | |
+ writel(c, port->membase + URTX0); | |
+ | |
+ /* flush */ | |
+ do { | |
+ status = readl(port->membase + USR2); | |
+ } while (~status & USR2_TXDC); | |
+ | |
+ /* restore control registers */ | |
+ imx_port_ucrs_restore(port, &old_ucr); | |
+} | |
+#endif | |
+ | |
static struct uart_ops imx_pops = { | |
.tx_empty = imx_tx_empty, | |
.set_mctrl = imx_set_mctrl, | |
@@ -1042,6 +1134,10 @@ | |
.request_port = imx_request_port, | |
.config_port = imx_config_port, | |
.verify_port = imx_verify_port, | |
+#if defined(CONFIG_CONSOLE_POLL) | |
+ .poll_get_char = imx_poll_get_char, | |
+ .poll_put_char = imx_poll_put_char, | |
+#endif | |
}; | |
static struct imx_port *imx_ports[UART_NR]; |
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