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@bjonnh
Created December 5, 2022 02:04
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module top
(
input clk_25mhz,
output [27:0] gp,
);
wire [3:0] clocks;
wire [3:0] clocks2;
ecp5pll
#(
.in_hz(25000000),
.out0_hz(12500000), .out0_tol_hz(0),
.out1_hz( 6250000), .out1_tol_hz(0),
.out2_hz( 6250000), .out2_tol_hz(10),
.out3_hz( 6250000), .out3_tol_hz(0)
)
ecp5pll_inst
(
.clk_i(clk_25mhz),
.clk_o(clocks)
);
ecp5pll
#(
.in_hz( 6250000),
.out0_hz( 97656), .out0_tol_hz(10),
.out1_hz( 48828), .out1_tol_hz(10),
.out2_hz( 6250000), .out2_tol_hz(0),
.out3_hz( 6250000), .out3_tol_hz(0)
)
ecp5pll_inst2
(
.clk_i(clocks[1]),
.clk_o(clocks2)
);
assign gp[0] = clocks[1];
assign gp[1] = clocks2[0];
assign gp[2] = clocks2[1];
endmodule
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