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September 30, 2020 17:25
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1568 SERV core count resource utilization on DE5-Net using corescorer
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+----------------------------------------------------------------------------------------------------+ | |
; Fitter Resource Usage Summary ; | |
+------------------------------------------------------------------+-------------------------+-------+ | |
; Resource ; Usage ; % ; | |
+------------------------------------------------------------------+-------------------------+-------+ | |
; Logic utilization (ALMs needed / total ALMs on device) ; 233,293 / 234,720 ; 99 % ; | |
; ALMs needed [=A-B+C] ; 233,293 ; ; | |
; [A] ALMs used in final placement [=a+b+c+d] ; 232,725 / 234,720 ; 99 % ; | |
; [a] ALMs used for LUT logic and registers ; 119,886 ; ; | |
; [b] ALMs used for LUT logic ; 38,783 ; ; | |
; [c] ALMs used for registers ; 74,056 ; ; | |
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ; | |
; [B] Estimate of ALMs recoverable by dense packing ; 1,050 / 234,720 ; < 1 % ; | |
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 1,618 / 234,720 ; < 1 % ; | |
; [a] Due to location constrained logic ; 0 ; ; | |
; [b] Due to LAB-wide signal conflicts ; 1,609 ; ; | |
; [c] Due to LAB input limits ; 9 ; ; | |
; [d] Due to virtual I/Os ; 0 ; ; | |
; ; ; ; | |
; Difficulty packing design ; High ; ; | |
; ; ; ; | |
; Total LABs: partially or completely used ; 23,455 / 23,472 ; 100 % ; | |
; -- Logic LABs ; 23,455 ; ; | |
; -- Memory LABs (up to half of total LABs) ; 0 ; ; | |
; ; ; ; | |
; Combinational ALUT usage for logic ; 304,242 ; ; | |
; -- 7 input functions ; 6,360 ; ; | |
; -- 6 input functions ; 48,246 ; ; | |
; -- 5 input functions ; 69,996 ; ; | |
; -- 4 input functions ; 54,127 ; ; | |
; -- <=3 input functions ; 125,513 ; ; | |
; Combinational ALUT usage for route-throughs ; 97,444 ; ; | |
; ; ; ; | |
; Dedicated logic registers ; 425,991 ; ; | |
; -- By type: ; ; ; | |
; -- Primary logic registers ; 387,883 / 469,440 ; 83 % ; | |
; -- Secondary logic registers ; 38,108 / 469,440 ; 8 % ; | |
; -- By function: ; ; ; | |
; -- Design implementation registers ; 400,093 ; ; | |
; -- Routing optimization registers ; 25,898 ; ; | |
; ; ; ; | |
; Virtual pins ; 0 ; ; | |
; I/O pins ; 9 / 1,064 ; < 1 % ; | |
; -- Clock pins ; 1 / 40 ; 3 % ; | |
; -- Dedicated input pins ; 0 / 109 ; 0 % ; | |
; ; ; ; | |
; M20K blocks ; 1,570 / 2,560 ; 61 % ; | |
; Total MLAB memory bits ; 0 ; ; | |
; Total block memory bits ; 3,214,336 / 52,428,800 ; 6 % ; | |
; Total block memory implementation bits ; 32,153,600 / 52,428,800 ; 61 % ; | |
; ; ; ; | |
; Total DSP Blocks ; 0 / 256 ; 0 % ; | |
; ; ; ; | |
; Fractional PLLs ; 1 / 28 ; 4 % ; | |
; Global signals ; 2 ; ; | |
; -- Global clocks ; 1 / 16 ; 6 % ; | |
; -- Quadrant clocks ; 0 / 92 ; 0 % ; | |
; -- Horizontal periphery clocks and Vertical periphery clocks ; 0 / 306 ; 0 % ; | |
; SERDES transmitters ; 0 / 210 ; 0 % ; | |
; SERDES receivers ; 0 / 210 ; 0 % ; | |
; JTAGs ; 0 / 1 ; 0 % ; | |
; ASMI blocks ; 0 / 1 ; 0 % ; | |
; CRC blocks ; 0 / 1 ; 0 % ; | |
; Remote update blocks ; 0 / 1 ; 0 % ; | |
; Oscillator blocks ; 0 / 1 ; 0 % ; | |
; Standard RX PCSs ; 0 / 48 ; 0 % ; | |
; 10G RX PCSs ; 0 / 48 ; 0 % ; | |
; HSSI PMA RX Deserializers ; 0 / 48 ; 0 % ; | |
; Standard TX PCSs ; 0 / 48 ; 0 % ; | |
; 10G TX PCSs ; 0 / 48 ; 0 % ; | |
; HSSI PMA TX Serializers ; 0 / 48 ; 0 % ; | |
; CHANNEL PLLs ; 0 / 48 ; 0 % ; | |
; HSSI ATX PLL ; 0 / 16 ; 0 % ; | |
; Impedance control blocks ; 0 / 4 ; 0 % ; | |
; Average interconnect usage (total/H/V) ; 46.8% / 46.4% / 47.6% ; ; | |
; Peak interconnect usage (total/H/V) ; 65.4% / 66.4% / 68.5% ; ; | |
; ; ; ; | |
; Programmable power technology high-speed tiles ; 1,572 / 14,556 ; 11 % ; | |
; Programmable power technology low-power tiles ; 12,984 / 14,556 ; 89 % ; | |
; -- low-power tiles that are used by the design ; 11,734 / 12,984 ; 90 % ; | |
; -- unused tiles (low-power) ; 1,250 / 12,984 ; 10 % ; | |
; ; ; ; | |
; Programmable power technology high-speed LAB tiles ; 2 / 11,736 ; < 1 % ; | |
; Programmable power technology low-power LAB tiles ; 11,734 / 11,736 ; 100 % ; | |
; -- low-power LAB tiles that are used by the design ; 11,734 / 11,734 ; 100 % ; | |
; -- unused LAB tiles (low-power) ; 0 / 11,734 ; 0 % ; | |
; ; ; ; | |
; Maximum fan-out ; 427561 ; ; | |
; Highest non-global fan-out ; 89073 ; ; | |
; Total fan-out ; 2862179 ; ; | |
; Average fan-out ; 3.45 ; ; | |
+------------------------------------------------------------------+-------------------------+-------+ |
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