Last active
September 7, 2020 17:10
-
-
Save bluecmd/fe70d5279bfcaca470c6556ccd502933 to your computer and use it in GitHub Desktop.
cocotb 1.40 freeze bug with Verilator
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
TOPLEVEL_LANG = verilog | |
VERILOG_SOURCES = $(shell pwd)/test.v | |
TOPLEVEL = thing | |
MODULE = test | |
SIM ?= verilator | |
include $(shell cocotb-config --makefiles)/Makefile.sim |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
import cocotb | |
from cocotb.clock import Clock, Timer | |
from cocotb.monitors.avalon import AvalonSTPkts as AvalonSTMonitor | |
from cocotb.triggers import RisingEdge | |
async def new(dut): | |
rx_clock = Clock(dut.rx_clk, 10, units='us') | |
tx_clock = Clock(dut.tx_clk, 10, units='us') | |
cocotb.fork(rx_clock.start()) | |
cocotb.fork(tx_clock.start()) | |
# This works | |
# _ = AvalonSTMonitor(dut, 'st_out', dut.rx_clk) | |
await Timer(50, units='us') | |
# This freezes | |
_ = AvalonSTMonitor(dut, 'st_out', dut.rx_clk) | |
@cocotb.test() | |
async def test_a(dut): | |
await new(dut) | |
await RisingEdge(dut.tx_clk) | |
@cocotb.test() | |
async def test_b(dut): | |
await new(dut) | |
await RisingEdge(dut.tx_clk) |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
`timescale 1 us / 1 us | |
module thing ( | |
input wire tx_clk, | |
input wire rx_clk, | |
input wire reset, | |
output wire [7:0] st_out_data, | |
output wire st_out_valid, | |
output wire st_out_startofpacket, | |
output wire st_out_endofpacket, | |
output wire st_out_empty | |
); | |
endmodule |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment