bbb enc28j60

BB-ENC28J60-01-00A0.dts

/*
 * Copyright (C) 2013 CircuitCo
 *
 * Virtual cape for SPI0 on connector pins P9.22 P9.21 P9.18 P9.17
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;
/plugin/;

/ {
        compatible = "ti,beaglebone", "ti,beaglebone-black";

        /* identification */
        part-number = "BB-ENC28J60-01";
        version = "00A0";

        /* state the resources this cape uses */
        exclusive-use =
                /* the pin header uses */
                "P9.17",        /* spi0_cs0 */
                "P9.18",        /* spi0_d1 */
                "P9.21",        /* spi0_d0 */
                "P9.22",        /* spi0_sclk */
                /* the hardware ip uses */
                "spi0";

        fragment@0 {
                target = <&am33xx_pinmux>;
                __overlay__ {
                        /* default state has all gpios released and mode set to uart1 */
                        bb_spi0_pins: pinmux_bb_spi0_pins {
                                pinctrl-single,pins = <
                                        0x150 0x30      /* spi0_sclk.spi0_sclk, INPUT_PULLUP | MODE0 */
                                        0x154 0x30      /* spi0_d0.spi0_d0, INPUT_PULLUP | MODE0 */
                                        0x158 0x10      /* spi0_d1.spi0_d1, OUTPUT_PULLUP | MODE0 */
                                        0x15c 0x10      /* spi0_cs0.spi0_cs0, OUTPUT_PULLUP | MODE0 */
                                >;
                        };
                };
        };

        fragment@1 {
                target = <&spi0>;       /* spi0 is numbered correctly */
                __overlay__ {
                        #address-cells = <1>;
                        #size-cells = <0>;

                        status = "okay";
                        pinctrl-names = "default";
                        pinctrl-0 = <&bb_spi0_pins>;



                        channel@0 {
                                #address-cells = <1>;
                                #size-cells = <0>;

                                compatible = "spidev";

                                reg = <0>;
                                spi-max-frequency = <16000000>;
                                spi-cpha;

                                //reg = < 0x00002160 0x00000020 >;
                                interrupt-parent = < &cpu >;
                                interrupts = < 2 >;
                                clock-frequency = < 100000000 >;
                                baud-width = < 8 >;     /* BAUD_WIDTH type NUMBER */
                                gpios = < &spi1_cs 0 0 >;
                                ethernet: enc28j60@0 {
                                        compatible = "microchip,enc28j60";
                                        spi-max-frequency = < 20000000 >;
                                        reg = < 0 >;
                                        interrupts = < 4 >;
                                        interrupt_deassert_reg = < 0x00003000 >;
                                };
                        };


                        channel@1 {
                                #address-cells = <1>;
                                #size-cells = <0>;

                                compatible = "spidev";

                                reg = <1>;
                                spi-max-frequency = <16000000>;
                        };
                };
        };
};

enc28j60.diff

diff -uprN 
a/Documentation/devicetree/bindings/net/microchip-enc28j60.txt 
b/Documentation/devicetree/bindings/net/microchip-enc28j60.txt
--- a/Documentation/devicetree/bindings/net/microchip-enc28j60.txt 
1969-12-31 19:00:00.000000000 -0500
+++ b/Documentation/devicetree/bindings/net/microchip-enc28j60.txt 
2011-10-14 13:46:58.000000000 -0400
@@ -0,0 +1,31 @@
+* Microchip enc28j60 Ethernet
+
+Required properties:
+- compatible : Should be "microchip,enc28j60"
+- interrupts : Should contain 1 interrupt.
+- reg : Should be 0
+
+Optional properties:
+- interrupt_deassert_reg : should contain address of additional (FPGA)
+  interrupt deassert hardware for processors with level triggered interrupts
+
+
+Example (for enc28j60 under opencores tinyspi controller):
+
+tiny_spi_1: spi at 0x2160 {
+ compatible = "opencores,tiny-spi-1.0", "opencores,tiny-spi-rtlsvn2";
+  reg = < 0x00002160 0x00000020 >;
+	interrupt-parent = < &cpu >;
+	interrupts = < 2 >;
+	clock-frequency = < 100000000 >;
+	baud-width = < 8 >;	/* BAUD_WIDTH type NUMBER */
+	gpios = < &spi1_cs 0 0 >;
+	ethernet: enc28j60 at 0 {
+		compatible = "microchip,enc28j60";
+		spi-max-frequency = < 20000000 >;
+		reg = < 0 >;
+		interrupts = < 4 >;
+		interrupt_deassert_reg = < 0x00003000 >;
+	};			
+}; //end spi at 0x2160 (tiny_spi_1)
+
diff -uprN a/drivers/net/ethernet/microchip/enc28j60.c 
b/drivers/net/ethernet/microchip/enc28j60.c
--- a/drivers/net/ethernet/microchip/enc28j60.c	2011-10-02 
07:31:43.000000000 -0400
+++ b/drivers/net/ethernet/microchip/enc28j60.c	2011-10-14 
13:54:15.000000000 -0400
@@ -32,7 +32,7 @@
  #include "enc28j60_hw.h"

  #define DRV_NAME	"enc28j60"
-#define DRV_VERSION	"1.01"
+#define DRV_VERSION	"1.02"

  #define SPI_OPLEN	1

@@ -73,6 +73,7 @@ struct enc28j60_net {
  	int rxfilter;
  	u32 msg_enable;
  	u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN];
+	u8 *interrupt_deassert_reg;
  };

  /* use ethtool to change the level for any given device */
@@ -1320,6 +1321,10 @@ static irqreturn_t enc28j60_irq(int irq,
  	 * Remember that we access enc28j60 registers through SPI bus
  	 * via spi_sync() call.
  	 */
+
+	if(priv->interrupt_deassert_reg)
+		writeb(1,priv->interrupt_deassert_reg);
+
  	schedule_work(&priv->irq_work);

  	return IRQ_HANDLED;
@@ -1541,6 +1546,36 @@ static const struct net_device_ops enc28
  	.ndo_validate_addr	= eth_validate_addr,
  };

+#ifdef CONFIG_OF
+#include <linux/of.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+
+static int __devinit enc28j60_of_probe(struct spi_device *spi,struct enc28j60_net *priv)
+{
+
+	u8 *reg;
+	const __be32 *prop;
+	int len;
+	
+	if (!of_device_is_available(spi->dev.of_node))
+		return -ENODEV;	
+
+	prop = of_get_property(spi->dev.of_node, "interrupt_deassert_reg", &len);
+	
+	if(prop && len>=sizeof(__be32))
+		reg = be32_to_cpup(prop);
+	else
+		return -ENODEV;
+
+	if(!devm_request_mem_region(&spi->dev, reg, 4, DRV_NAME))
+		return -ENOMEM;
+
+	priv->interrupt_deassert_reg = devm_ioremap_nocache(&spi->dev, reg, 4);
+	return 0;	
+}
+#endif
+
  static int __devinit enc28j60_probe(struct spi_device *spi)
  {
  	struct net_device *dev;
@@ -1569,6 +1604,10 @@ static int __devinit enc28j60_probe(stru
  	INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler);
  	dev_set_drvdata(&spi->dev, priv);	/* spi to priv reference */
  	SET_NETDEV_DEV(dev, &spi->dev);
+	priv->interrupt_deassert_reg = 0;
+#ifdef CONFIG_OF
+	enc28j60_of_probe(spi,priv);
+#endif	

  	if (!enc28j60_chipset_init(dev)) {
  		if (netif_msg_probe(priv))
@@ -1631,10 +1670,20 @@ static int __devexit enc28j60_remove(str
  	return 0;
  }

+#ifdef CONFIG_OF
+static const struct of_device_id enc28j60_dt_ids[] = {
+	{ .compatible = "microchip,enc28j60", },
+	{ /* sentinel */ }
+};
+#else
+#define enc28j60_dt_ids NULL
+#endif
+
  static struct spi_driver enc28j60_driver = {
  	.driver = {
  		   .name = DRV_NAME,
  		   .owner = THIS_MODULE,
+		   .of_match_table = enc28j60_dt_ids,
  	 },
  	.probe = enc28j60_probe,
  	.remove = __devexit_p(enc28j60_remove),