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BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz | |
Board ID = 8 | |
Set cpu clk to 24M | |
Set clk81 to 24M | |
Use GP1_pll as DSU clk. | |
DSU clk: 1200 Mhz | |
CPU clk: 1200 MHz | |
Set clk81 to 166.6M | |
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45 | |
board id: 8 | |
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg | |
DATA transfer complete... | |
fw parse done | |
DATA transfer complete... | |
AML DDR FW load done | |
DATA transfer complete... | |
PIEI prepare done | |
LPDDR4 probe | |
ddr clk to 1608MHz | |
DATA transfer complete... | |
dmc_version 0001 | |
Check phy result | |
INFO : ERROR : Training has failed! | |
Cfg max: 4, cur: 2. Board id: 255. Force loop cfg | |
ddr probe id done | |
DATA transfer complete... | |
fw parse done | |
DATA transfer complete... | |
AML DDR FW load done | |
DATA transfer complete... | |
PIEI prepare done | |
LPDDR4 probe | |
ddr clk to 1608MHz | |
DATA transfer complete... | |
dmc_version 0001 | |
Check phy result | |
INFO : End of CA training | |
INFO : End of initialization | |
INFO : Training has run successfully! | |
Check phy result | |
INFO : End of initialization | |
INFO : End of read enable training | |
INFO : End of fine write leveling | |
INFO : End of Write leveling coarse delay | |
INFO : Training has run successfully! | |
Check phy result | |
INFO : End of initialization | |
INFO : End of read dq deskew training | |
INFO : End of MPR read delay center optimization | |
INFO : End of write delay center optimization | |
INFO : End of read delay center optimization | |
INFO : End of max read latency training | |
INFO : Training has run successfully! | |
1D init succeed | |
DATA transfer complete... | |
Check phy result | |
INFO : End of initialization | |
INFO : End of 2D read delay Voltage center optimization | |
INFO : End of 2D read delay Voltage center optimization | |
INFO : End of 2D write delay Voltage center optimization | |
INFO : End of 2D write delay Voltage center optimization | |
INFO : Training has run successfully! | |
channel==0 | |
RxClkDly_Margin_A0==97 ps 10 | |
TxDqDly_Margin_A0==97 ps 10 | |
RxClkDly_Margin_A1==0 ps 0 | |
TxDqDly_Margin_A1==0 ps 0 | |
TrainedVREFDQ_A0==30 | |
TrainedVREFDQ_A1==0 | |
VrefDac_Margin_A0==28 | |
DeviceVref_Margin_A0==30 | |
VrefDac_Margin_A1==0 | |
DeviceVref_Margin_A1==0 | |
channel==1 | |
RxClkDly_Margin_A0==77 ps 8 | |
TxDqDly_Margin_A0==116 ps 12 | |
RxClkDly_Margin_A1==0 ps 0 | |
TxDqDly_Margin_A1==0 ps 0 | |
TrainedVREFDQ_A0==28 | |
TrainedVREFDQ_A1==0 | |
VrefDac_Margin_A0==27 | |
DeviceVref_Margin_A0==28 | |
VrefDac_Margin_A1==0 | |
DeviceVref_Margin_A1==0 | |
dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 | |
soc_vref_reg_value 0x 00000026 00000026 00000028 00000025 00000026 00000026 00000027 00000027 00000027 00000024 00000025 00000027 0000005 | |
2D init succeed | |
ddr init done, boot next stage | |
result report | |
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:53:31 | |
auto size-- 65535DDR cs0 size: 2048MB | |
DDR cs1 size: 0MB | |
DMC_DDR_CTRL: 00c0002cDDR size: 2048MB | |
cs0 DataBus test pass | |
cs0 AddrBus test pass | |
DATA transfer complete... | |
DATA transfer complete... | |
Data req end | |
DATA transfer complete... | |
RUN bl2 usb boot | |
bl2z: ptr: 05129330, size: 00001e40 | |
0.0;M3 CHK:0;cm4_sp_mode 0 | |
MVN_1=0x00000000 | |
MVN_2=0x00000000 | |
[Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz] | |
OPS=0x04 | |
ring efuse init | |
2b 0c 04 00 01 14 16 00 00 17 32 31 38 54 33 50 | |
[0.017354 Inits done] | |
secure task start! | |
high task start! | |
low task start! | |
run into bl31 | |
NOTICE: BL31: v1.3(release):4fc40b1 | |
NOTICE: BL31: Built : 15:57:33, May 22 2019 | |
NOTICE: BL31: G12A normal boot! | |
NOTICE: BL31: BL33 decompress pass | |
ERROR: Error initializing runtime service opteed_fast | |
U-Boot 2021.07 (Nov 12 2021 - 11:31:11 +0800) khadas-vim3l | |
Model: Khadas VIM3L | |
SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2) | |
DRAM: 2 GiB | |
MMC: sd@ffe03000: 0, sd@ffe05000: 1, mmc@ffe07000: 2 | |
Loading Environment from MMC... ignored booted from other source! | |
Loading Environment from SPIFlash... SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB | |
*** Warning - bad CRC, using default environment | |
In: serial | |
Out: serial | |
Err: serial | |
fusb302_init: Device ID: 0x91 | |
CC connected in 0 as UFP | |
fusb302 detect chip.port_num = 0 | |
Net: eth0: ethernet@ff3f0000 | |
Card did not respond to voltage select! : -110 | |
Couldn't find partition mmc 1 | |
Can't set block device | |
** Unrecognized filesystem type ** | |
Can't set block device | |
Card did not respond to voltage select! : -110 | |
Couldn't find partition mmc 1:2 | |
Can't set block device | |
** Unrecognized filesystem type ** | |
Can't set block device | |
[i] display embed logo | |
starting USB... | |
Bus usb@ff500000: Register 3000140 NbrPorts 3 | |
Starting the controller | |
USB XHCI 1.10 | |
scanning bus usb@ff500000 for devices... Failed to get keyboard state from device 0406:2814 | |
2 USB Device(s) found | |
scanning usb for storage devices... 0 Storage Device(s) found | |
Setting bus to 0 | |
port mode is usb3.0 | |
Hit SPACE in 2 seconds to stop autoboot=> | |
=> fastboot | |
Unknown command 'fastboot' - try 'help' | |
=> | |
C |
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