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July 27, 2020 01:10
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iDRAC7 U-boot interrupt
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U-Boot 2009.08-00088-g121cddc (Nov 17 2014 - 05:50:46) Avocent (0.0.3) EVB, Build: jenkins-idrac-yocto-release-505 | |
CPU: SH-4A | |
BOARD: R0P7757LC00xxRL (C0 step) board | |
BOOT: Secure, HRK not generated | |
DRAM: 240MB | |
(240MB of 256MB total DRAM is available on U-Boot) | |
ENV: Using primary env area. | |
In: serial | |
Out: serial | |
Err: serial | |
WDT2: Booted Lower Vector, 'uboot1' | |
sh_mmcif: 0, sh-sdhi: 1 | |
Net: sh_eth.0, sh_g_eth.0 | |
INFO: 00:002 Start-up -to- util_idrac_main() | |
INFO: 00:004 U-Boot 2009.08-00088-g121cddc (Nov 17 2014 - 05:50:46) Avocent (0.0.3) EVB | |
INFO: 00:008 U-Boot checkin date(05-10-2013) Version(1.0.183) | |
INFO: 00:006 iDRAC PPID <NULL> | |
INFO: 00:003 SPI NOR init 4096 KiB AT25DF321A bus=0 cs=0, speed=1000000, mode=3 | |
INFO: 00:007 SH-4A Product: Major Ver=0x31 Minor Ver=0x14 C4 Little endian | |
Family=0x10 Major Ver=0x30 Minor Ver=0x0b | |
PASS: 00:016 Dedicated monolithic mgmt NIC enabled (vendor mode override) | |
INFO: 00:130 BCM54610 OUI=0x00d897 Model=0x26 Revision=0x0a PhyAddr=1 | |
INFO: 00:092 SD CARD: Device: sh-sdhi Manufacturer ID: 2 OEM: 544d | |
Name: SD32G Tran Speed: 25000000 Rd Block Len: 512 | |
SD version 2.0 High Capacity: Yes Capacity: 1828716544 | |
INFO: 00:058 EMMC: Device: sh_mmcif Manufacturer ID: 90 OEM: 14a | |
Name: HYNIX Tran Speed: 25000000 Rd Block Len: 512 | |
MMC version 4.0 High Capacity: Yes Capacity: 0 | |
INFO: 00:019 CPLD: Major Ver=0x1 Minor Ver=0x0 Maint Ver=0x3 | |
Planar: Type=0x04 Rev=0x8 Rework=0x0 Scratch/PathRetry=0x00 | |
PASS: 00:014 Coin cell detected good, AD=0x3aa low water=0x2c1 | |
PASS: 00:008 PCIe C0 Ver=0.15 MCTP en, CRC=0x8e9b6875 @0x8efbf954 cnt=0x18000 | |
INFO: 00:007 Init PCIe mailbox(PCIe 0xFFEE0150=0x40010000) | |
INFO: 00:005 mode=vhard | |
INFO: 00:003 reset_cause=board | |
PASS: 00:004 Booted Lower Vector, 'uboot1' wdt2cnt=0 | |
INFO: 00:006 wdt0cnt=0 | |
PASS: 00:002 SMR0 no sermux env, default 0xd4 | |
INFO: 00:004 GRACR=0x3c HISEL=0x00 SIRQCR5_D=0x03 SIRQCR6_D=0x01 LADMSK0=0xff2 | |
MRSTCR0=0xfedffe7f MRSTCR1=0xfff3ff0f MRSTCR2=0x7f80feff | |
BARMAP=0x1 BCR=0x85000000 NCER=0x01fc NCMCR=0x0006 NCCSR=0x0303 | |
PASS: 00:021 etherc0=F0:1F:AF:D0:B4:71 | |
getherc0=F0:1F:AF:D0:B4:72 | |
INFO: 00:008 Fan logic is not modified on Non-AC power up | |
INFO: 00:052 Env and backup CRC'ed ok | |
*** no text signature found *** | |
INFO: 00:657 Sync eMMC/SPI NOR/Alternate u-boot images | |
PASS: 00:075 Current u-boot1 1.0.183 verified with 'ubootN' | |
Trailer Struct - Missing start token, exp=0xc0de1111 rec=0x0 | |
PASS: 04:081 Verify OS Images N: CRC32 OK: Kernel=0x8c86b2b Rootfs=0xb0e73b0 | |
PASS: 00:007 Boot device=emmc Boot partition1/N | |
Boot Path Retry:P1/N=0 P5/N-1=0 | |
INFO: 03:405 Dedicated NIC has no link, switch to use NCSI | |
INFO: 00:006 No 'userexe' defined | |
INFO: 00:000 08:713 | |
Hit any key to stop autoboot: 0 | |
WDT2: Disable in abortboot() | |
OSWDT: Disable in abortboot() | |
CPLD_BMCRDY: Enable BMC_MIN_RDY in abortboot(). Prevent BIOS reset. | |
NOTE: After stopping u-boot in this development mode. You may need to | |
warm/cold reset the server when booting iDRAC manually as BIOS | |
may have already viewed iDRAC as unresponsive. | |
iDRAC7=> | |
iDRAC7=> mmcinfo | |
Device: sh_mmcif | |
Manufacturer ID: 90 | |
OEM: 14a | |
Name: HYNIX | |
Tran Speed: 25000000 | |
Rd Block Len: 512 | |
MMC version 4.0 | |
High Capacity: Yes | |
Capacity: 0 | |
Bus Width: 4-bit | |
iDRAC7=> |
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