Phase-Locked Loop (PLL) is used to compensate delay in its feedback path, which can be used for different purposes. The most frequent uses are to compensate the clock tree delay/depth or to compensate the IO delay (or both).
A decade ago, accounting for the compensation in STA timing used to be a haedache. See P. Zimmer. Working with PLLs in PrimeTime – avoiding the phase locked oops, SNUG San Jose 2005, http://www.zimmerdesignservices.com/mydownloads/zimmer_pll_update_051405.pdf
Presently, EDA vendors provide methods to identify a PLL cell and its feedback path, hence letting STA engines to account for the compensation themselves.
The timing model has to achieve the following:
- Identify a cell is indeed a PLL.
- Identify the critical pin functions (i.e. the reference clock input, feedback input and PLL clock output) that create the compensation loop.
- Identify PLL internal delay (from the reference input to the clock output).
Here is an example we will be using:
cell(xpll) {
is_pll_cell : true;
pin( REFCLK ) {
direction : input;
is_pll_reference_pin : true;
}
pin( FBKCLK ) {
direction : input;
is_pll_feedback_pin : true;
}
pin (PLLCLK) {
direction : output;
is_pll_output_pin : true;
timing() {
related_pin: "REFCLK";
timing_sense: positive_unate;
cell_fall(scalar) { values("1.5"); }
cell_rise(scalar) { values("1.5"); }
fall_transition(scalar) { values("0.1"); }
rise_transition(scalar) { values("0.1"); }
}
}
}Let us consider the following circuit:
module circ_pll(clk);
wire clkref, clkpll;
wire cts1, clkfb;
wire a, b, c;
bufx4 buf1( .A(clk), .Y(clkref) );
xpll pll( .REFCLK(clkref), .FBKCLK(clkfb), .PLLCLK(clkpll) );
bufx4 buf1( .A(clkpll), .Y(cts1) );
bufx4 buf1( .A(cts1), .Y(clkfb) );
dffrx1 FF1( .CK(clkref), .RB(1'b1), .D(a), .Q(b) );
dffrx1 FF2( .CK(clkfb), .RB(1'b1), .D(b), .Q(c) );
dffrx1 FF2a( .CK(cts1), .RB(1'b1), .D(b), .Q() );
dffrx1 FF3( .CK(clkref), .RB(1'b1), .D(c), .Q() );
endmodulecreate_clock -name CLK -period 10 clk
create_generated_clock -name PLLCLK -multiply_by 1 -source pll/REFCLK pll/PLLCLK
Startpoint: FF2 (rising edge-triggered flip-flop clocked by PLLCLK)
Endpoint: FF3 (rising edge-triggered flip-flop clocked by CLK)
Last common pin: buf1/Y
Path Group: CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PLLCLK (rise edge) 0.00 0.00
clock CLK (source latency) 0.00 0.00
clk (in) 0.00 0.00 r
buf1/Y (bufx4) 1.00 1.00 r
pll/PLLCLK (xpll) (gclock source) 1.50 2.50 r
buf2/Y (bufx4) 1.00 3.50 r
buf3/Y (bufx4) 1.00 4.50 r
FF2/CK (dffrx1) 0.00 4.50 r
FF2/Q (dffrx1) 3.00 7.50 r
FF3/D (dffrx1) 0.00 7.50 r
data arrival time 7.50
clock CLK (rise edge) 10.00 10.00
clock source latency 0.00 10.00
clk (in) 0.00 10.00 r
buf1/Y (bufx4) 1.00 11.00 r
FF3/CK (dffrx1) 0.00 11.00 r
clock reconvergence pessimism 0.00 11.00
library setup time -0.70 10.30
data required time 10.30
------------------------------------------------------------------------------
data required time 10.30
data arrival time -7.50
------------------------------------------------------------------------------
slack (MET) 2.80
create_generated_clock -name PLLCLK -multiply_by 1 -source pll/REFCLK pll/PLLCLK -pll_output pll/PLLCLK -pll_feedback pll/FBKCLK
Startpoint: FF2 (rising edge-triggered flip-flop clocked by PLLCLK)
Endpoint: FF3 (rising edge-triggered flip-flop clocked by CLK)
Last common pin: clk
Path Group: CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PLLCLK (rise edge) 0.00 0.00
clock CLK (source latency) 0.00 0.00
clk (in) 0.00 0.00 r
buf1/Y (bufx4) 1.00 1.00 r
pll/PLLCLK (xpll) (gclock source) -2.00 H -1.00 r
buf2/Y (bufx4) 1.00 0.00 r
buf3/Y (bufx4) 1.00 1.00 r
FF2/CK (dffrx1) 0.00 1.00 r
FF2/Q (dffrx1) <- 3.00 4.00 r
FF3/D (dffrx1) 0.00 4.00 r
data arrival time 4.00
clock CLK (rise edge) 10.00 10.00
clock source latency 0.00 10.00
clk (in) 0.00 10.00 r
buf1/Y (bufx4) 1.00 11.00 r
FF3/CK (dffrx1) 0.00 11.00 r
clock reconvergence pessimism 0.00 11.00
library setup time -0.70 10.30
data required time 10.30
------------------------------------------------------------------------------
data required time 10.30
data arrival time -4.00
------------------------------------------------------------------------------
slack (MET) 6.30
Startpoint: FF1 (rising edge-triggered flip-flop clocked by CLK)
Endpoint: FF2a (rising edge-triggered flip-flop clocked by PLLCLK)
Last common pin: clk
Path Group: PLLCLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock CLK (rise edge) 0.00 0.00
clock source latency 0.00 0.00
clk (in) 0.00 0.00 r
buf1/Y (bufx4) 1.00 1.00 r
FF1/CK (dffrx1) 0.00 1.00 r
FF1/Q (dffrx1) 3.00 4.00 r
FF2a/D (dffrx1) 0.00 4.00 r
data arrival time 4.00
clock PLLCLK (rise edge) 10.00 10.00
clock CLK (source latency) 0.00 10.00
clk (in) 0.00 10.00 r
buf1/Y (bufx4) 1.00 11.00 r
pll/PLLCLK (xpll) (gclock source) -2.00 H 9.00 r
buf2/Y (bufx4) 1.00 10.00 r
FF2a/CK (dffrx1) 0.00 10.00 r
clock reconvergence pessimism 0.00 10.00
library setup time -0.70 9.30
data required time 9.30
------------------------------------------------------------------------------
data required time 9.30
data arrival time -4.00
------------------------------------------------------------------------------
slack (MET) 5.30
Path 1: MET Setup Check with Pin FF3/CK
Endpoint: FF3/D (v) checked with leading edge of 'CLK'
Beginpoint: FF2/Q (v) triggered by leading edge of 'PLLCLK'
Path Groups: {CLK}
Other End Arrival Time 1.000
- Setup 0.700
+ Phase Shift 10.000
= Required Time 10.300
- Arrival Time 7.500
= Slack Time 2.800
Clock Rise Edge 0.000
= Beginpoint Arrival Time 0.000
Timing Path:
-------------------------------------------------------------------------------------
Instance Arc Cell Delay Arrival Required Generated Clock
Time Time Adjustment
-------------------------------------------------------------------------------------
- clk ^ - - 0.000 2.800 -
buf1 A ^ -> Y ^ bufx4 1.000 1.000 3.800 -
pll REFCLK ^ -> PLLCLK ^ xpll 1.500 2.500 5.300 PLLCLK Adj. = 0.000
buf2 A ^ -> Y ^ bufx4 1.000 3.500 6.300 -
buf3 A ^ -> Y ^ bufx4 1.000 4.500 7.300 -
FF2 CK ^ -> Q v dffrx1 3.000 7.500 10.300 -
FF3 D v dffrx1 0.000 7.500 10.300 -
-------------------------------------------------------------------------------------
Clock Rise Edge 0.000
= Beginpoint Arrival Time 0.000
Other End Path:
-----------------------------------------------------------------------
Instance Arc Cell Delay Arrival Required Generated Clock
Time Time Adjustment
-----------------------------------------------------------------------
- clk ^ - - 0.000 -2.800 -
buf1 A ^ -> Y ^ bufx4 1.000 1.000 -1.800 -
FF3 CK ^ dffrx1 0.000 1.000 -1.800 -
-----------------------------------------------------------------------
set_pll_timing [get_cells pll] -reference_pin REFCLK -feedback_pin FBKCLK -output_pin PLLCLK -output_clock [get_clock PLLCLK]
Path 1: MET Setup Check with Pin FF3/CK
Endpoint: FF3/D (v) checked with leading edge of 'CLK'
Beginpoint: FF2/Q (v) triggered by leading edge of 'PLLCLK'
Path Groups: {CLK}
Other End Arrival Time 1.000
- Setup 0.700
+ Phase Shift 10.000
= Required Time 10.300
- Arrival Time 4.000
= Slack Time 6.300
Clock Rise Edge 0.000
= Beginpoint Arrival Time 0.000
Timing Path:
---------------------------------------------------------------------------------
Instance Arc Cell Delay Arrival Required Generated Clock
Time Time Adjustment
---------------------------------------------------------------------------------
- clk ^ - - 0.000 6.300 -
buf1 A ^ -> Y ^ bufx4 1.000 1.000 7.300 -
pll PLLCLK ^ - - -1.000 5.300 PLLCLK Pll Adj. = -2.000
buf2 A ^ -> Y ^ bufx4 1.000 0.000 6.300 -
buf3 A ^ -> Y ^ bufx4 1.000 1.000 7.300 -
FF2 CK ^ -> Q v dffrx1 3.000 4.000 10.300 -
FF3 D v dffrx1 0.000 4.000 10.300 -
---------------------------------------------------------------------------------
Clock Rise Edge 0.000
= Beginpoint Arrival Time 0.000
Other End Path:
-----------------------------------------------------------------------
Instance Arc Cell Delay Arrival Required Generated Clock
Time Time Adjustment
-----------------------------------------------------------------------
- clk ^ - - 0.000 -6.300 -
buf1 A ^ -> Y ^ bufx4 1.000 1.000 -5.300 -
FF3 CK ^ dffrx1 0.000 1.000 -5.300 -
-----------------------------------------------------------------------