STA's primary function is to check a data signal timing to a clock signal timing, such as setup and hold constraints that require the data signal to remain stable around the active clock edge. In certain cases, we need to constrain the data change not to a clock event but another data signal event. These are called data-to-data checks. You can find them frequently in hard macros with asynchronous interfaces; but also in flip-flops with both asynchronous set and reset to enforce priority of one over the other.
Data-to-data checks can be expressed as user constraints (set_data_check) or as Liberty timing arcs (a.k.a. non-sequential timing arcs). While mostly similar there are some slight differences1. User constraints can be expressed between physically unrelated pins (e.g. inputs of two different cells). Timing arcs can be properly characterized and represented up to 2D timing tables; as a library figure they can also be easily made PVT dependent.
cell(macro1) {
is_macro_cell: true;
interface_timing: true;
...
pin(A) {
direction: input;
timing () {
related_pin : "C" ;
timing_type : non_seq_setup_falling ;
fall_constraint(scalar) { values("2.3"); }
}
}
pin(B) {
direction: input;
timing () {
related_pin : "A" ;
timing_type : non_seq_hold_falling ;
fall_constraint(scalar) { values("2.3"); }
}
timing () {
related_pin : "A" ;
timing_type : non_seq_setup_rising ;
rise_constraint(scalar) { values("1.7"); }
}
}
pin(C) {
direction: input;
timing () {
related_pin : "A" ;
timing_type : non_seq_setup_rising ;
rise_constraint(scalar) { values("1.7"); }
}
}
...PrimeTime analysis:
pt_shell> create_clock clk -name CLK -period 10.0
pt_shell> report_timing -from CLK -to m/B -delay_type max pt_shell> report_timing -from CLK -to m/C
Startpoint: ff2 (rising edge-triggered flip-flop clocked by CLK) Startpoint: ff2 (rising edge-triggered flip-flop clocked by CLK)
Endpoint: m (rising edge-triggered data to data check clocked by CLK) Endpoint: m (rising edge-triggered data to data check clocked by CLK)
Path Group: CLK Path Group: CLK
Path Type: max Path Type: max
Point Incr Path Point Incr Path
--------------------------------------------------------------- ---------------------------------------------------------------
clock CLK (rise edge) 0.00 0.00 clock CLK (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00 clock network delay (ideal) 0.00 0.00
ff2/CK (dffrx1) 0.00 0.00 r ff2/CK (dffrx1) 0.00 0.00 r
ff2/Q (dffrx1) 3.00 3.00 r ff2/Q (dffrx1) 3.00 3.00 r
m/B (macro1) 0.00 3.00 r m/C (macro1) 0.00 3.00 r
data arrival time 3.00 data arrival time 3.00
clock CLK (rise edge) 0.00 0.00 clock CLK (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00 clock network delay (ideal) 0.00 0.00
clock reconvergence pessimism 0.00 0.00 clock reconvergence pessimism 0.00 0.00
ff1/CK (dffrx1) 0.00 0.00 r ff1/CK (dffrx1) 0.00 0.00 r
ff1/Q (dffrx1) 3.00 3.00 r ff1/Q (dffrx1) 3.00 3.00 r
g1/Y (bufx1) 2.00 5.00 r g1/Y (bufx1) 2.00 5.00 r
m/A (macro1) 0.00 5.00 r m/A (macro1) 0.00 5.00 r
data check setup time -1.70 3.30 data check setup time -1.70 3.30
data required time 3.30 data required time 3.30
--------------------------------------------------------------- ---------------------------------------------------------------
data required time 3.30 data required time 3.30
data arrival time -3.00 data arrival time -3.00
--------------------------------------------------------------- ---------------------------------------------------------------
slack (MET) 0.30 slack (MET) 0.30
pt_shell> report_timing -from CLK -to m/B -delay_type min pt_shell> report_timing -from CLK -to m/A
Startpoint: ff2 (rising edge-triggered flip-flop clocked by CLK) Startpoint: ff1 (rising edge-triggered flip-flop clocked by CLK)
Endpoint: m (rising edge-triggered data to data check clocked by CLK) Endpoint: m (falling edge-triggered data to data check clocked by CLK)
Path Group: CLK Path Group: CLK
Path Type: min Path Type: max
Point Incr Path Point Incr Path
--------------------------------------------------------------- ---------------------------------------------------------------
clock CLK (rise edge) 10.00 10.00 clock CLK (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 10.00 clock network delay (ideal) 0.00 0.00
ff2/CK (dffrx1) 0.00 10.00 r ff1/CK (dffrx1) 0.00 0.00 r
ff2/Q (dffrx1) 3.00 13.00 f ff1/Q (dffrx1) 3.00 3.00 f
m/B (macro1) 0.00 13.00 f g1/Y (bufx1) 2.00 5.00 f
data arrival time 13.00 m/A (macro1) 0.00 5.00 f
data arrival time 5.00
clock CLK (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00 clock CLK (rise edge) 0.00 0.00
clock reconvergence pessimism 0.00 0.00 clock network delay (ideal) 0.00 0.00
ff1/CK (dffrx1) 0.00 0.00 r clock reconvergence pessimism 0.00 0.00
ff1/Q (dffrx1) 3.00 3.00 f ff2/CK (dffrx1) 0.00 0.00 r
g1/Y (bufx1) 2.00 5.00 f ff2/Q (dffrx1) 3.00 3.00 f
m/A (macro1) 0.00 5.00 f m/C (macro1) 0.00 3.00 f
data check hold time 2.30 7.30 data check setup time -2.30 0.70
data required time 7.30 data required time 0.70
--------------------------------------------------------------- ---------------------------------------------------------------
data required time 7.30 data required time 0.70
data arrival time -13.00 data arrival time -5.00
--------------------------------------------------------------- ---------------------------------------------------------------
slack (MET) 5.70 slack (VIOLATED) -4.30In certain cases, there may be a solution to time the macro inputs within a single cycle. One example is shown below. Finding the proper buffering that satisfies the timing over the complete PVT range is what you expect from the P&R tool. Timings in the example we chosen to meet the macro timing.
It is not all that simple as STA does no logic function checks (and hence does not test) validity of the latest and earliest data paths. It is then no surprise that both A-to-C and C-to-A non-sequential setup checks get violated:
pt_shell> report_timing -input_pins -rise_through ff1/Q pt_shell> report_timing -fall_through ff1/Q
Startpoint: ff1 (rising edge-triggered flip-flop clocked by CLK) Startpoint: ff1 (rising edge-triggered flip-flop clocked by CLK)
Endpoint: m (rising edge-triggered data to data check clocked by CLK) Endpoint: m (falling edge-triggered data to data check clocked by CLK)
Path Group: CLK Path Group: CLK
Path Type: max Path Type: max
Point Incr Path Point Incr Path
--------------------------------------------------------------- ---------------------------------------------------------------
clock CLK (rise edge) 0.00 0.00 clock CLK (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00 clock network delay (ideal) 0.00 0.00
ff1/CK (dffrx1) 0.00 0.00 r ff1/CK (dffrx1) 0.00 0.00 r
ff1/Q (dffrx1) <- 3.00 3.00 r ff1/Q (dffrx1) <- 3.00 3.00 f
g1/Y (bufx1) 2.00 5.00 r g1/Y (bufx1) 2.00 5.00 f
g4/Y (nor2x1) 2.00 7.00 f g2/Y (nand2x1) 2.00 7.00 r
g5/Y (invx1) 2.00 9.00 r g3/Y (invx1) 2.00 9.00 f
m/B (macro2) 0.00 9.00 r m/A (macro2) 0.00 9.00 f
data arrival time 9.00 data arrival time 9.00
clock CLK (rise edge) 0.00 0.00 clock CLK (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00 clock network delay (ideal) 0.00 0.00
clock reconvergence pessimism 0.00 0.00 clock reconvergence pessimism 0.00 0.00
ff1/CK (dffrx1) 0.00 0.00 r ff1/CK (dffrx1) 0.00 0.00 r
ff1/Q (dffrx1) 3.00 3.00 r ff1/Q (dffrx1) 3.00 3.00 f
g2/Y (nand2x1) 2.00 5.00 f g4/Y (nor2x1) 2.00 5.00 r
g3/Y (invx1) 2.00 7.00 r g5/Y (invx1) 2.00 7.00 f
m/A (macro2) 0.00 7.00 r m/B (macro2) 0.00 7.00 f
data check setup time -1.40 5.60 data check setup time -1.30 5.70
data required time 5.60 data required time 5.70
--------------------------------------------------------------- ---------------------------------------------------------------
data required time 5.60 data required time 5.70
data arrival time -9.00 data arrival time -9.00
--------------------------------------------------------------- ---------------------------------------------------------------
slack (VIOLATED) -3.40 slack (VIOLATED) -3.30We need to tell the tool that the paths it chose are all wrong by design:
pt_shell> set_false_path -rise_through ff1/Q -rise_through g4/A
pt_shell> set_false_path -rise_through ff1/Q -rise_through g2/B
pt_shell> set_false_path -fall_through ff1/Q -fall_through g2/A
pt_shell> set_false_path -fall_through ff1/Q -fall_through g4/B
pt_shell> report_timing -input_pins -rise_through ff1/Q pt_shell> report_timing -fall_through ff1/Q
Startpoint: ff1 (rising edge-triggered flip-flop clocked by CLK) Startpoint: ff1 (rising edge-triggered flip-flop clocked by CLK)
Endpoint: m (rising edge-triggered data to data check clocked by CLK) Endpoint: m (falling edge-triggered data to data check clocked by CLK)
Path Group: CLK Path Group: CLK
Path Type: max Path Type: max
Point Incr Path Point Incr Path
--------------------------------------------------------------- ---------------------------------------------------------------
clock CLK (rise edge) 0.00 0.00 clock CLK (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00 clock network delay (ideal) 0.00 0.00
ff1/CK (dffrx1) 0.00 0.00 r ff1/CK (dffrx1) 0.00 0.00 r
ff1/Q (dffrx1) <- 3.00 3.00 r ff1/Q (dffrx1) <- 3.00 3.00 f
g4/Y (nor2x1) 2.00 5.00 f g2/Y (nand2x1) 2.00 5.00 r
g5/Y (invx1) 2.00 7.00 r g3/Y (invx1) 2.00 7.00 f
m/B (macro2) 0.00 7.00 r m/A (macro2) 0.00 7.00 f
data arrival time 7.00 data arrival time 7.00
clock CLK (rise edge) 0.00 0.00 clock CLK (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00 clock network delay (ideal) 0.00 0.00
clock reconvergence pessimism 0.00 0.00 clock reconvergence pessimism 0.00 0.00
ff1/CK (dffrx1) 0.00 0.00 r ff1/CK (dffrx1) 0.00 0.00 r
ff1/Q (dffrx1) 3.00 3.00 r ff1/Q (dffrx1) 3.00 3.00 f
g1/Y (bufx1) 2.00 5.00 r g1/Y (bufx1) 2.00 5.00 f
g2/Y (nand2x1) 2.00 7.00 f g4/Y (nor2x1) 2.00 7.00 r
g3/Y (invx1) 2.00 9.00 r g5/Y (invx1) 2.00 9.00 f
m/A (macro2) 0.00 9.00 r m/B (macro2) 0.00 9.00 f
data check setup time -1.40 7.60 data check setup time -1.30 7.70
data required time 7.60 data required time 7.70
--------------------------------------------------------------- ---------------------------------------------------------------
data required time 7.60 data required time 7.70
data arrival time -7.00 data arrival time -7.00
--------------------------------------------------------------- ---------------------------------------------------------------
slack (MET) 0.60 slack (MET) 0.70What is the Difference Between set_data_check and Non-Sequential Library Arcs?, Synopsys Solvnet article 000004915, Dec 2019.↩