Shows how to list include files needed by Verilog/SystemVerilog source files.

getting_verilog_includes.md

Verilog/SystemVerilog are similar to C/C++ by using the ```include`` directive, but not exactly the same by strictly separating header (.h) and code (`.c`, `.cpp`) files. The end result is, though, the same: If one wants to create a `make` target to compile a code file, she will need to know the dependencies on any included files.

In C/C++, where one can use the compiler/preprocessor to get such dependencies. Unfortunately none (to my knowledge) of the major EDA vendors do not equip their compilers with similar functionality. Accidentally I stumbled upon the Verilog-perl module (also on CPAN) that, among other things, provides a full Verilog/SystemVerilog preprocessor. With its help and little bit of coding, one gets a tool to automatically discover include depenedencies.

Note that using the full parser provided with Verilog-perl, one can discover all the dependcies automatically.

package VlogIncludeResolver;
use strict;
use warnings;
use parent 'Verilog::Preproc';

my @incFiles;

  # parse, parse_file, etc are inherited from Verilog::Parser
  sub new {
      my $class = shift;
      my $self = $class->SUPER::new(@_);
      bless $self, $class;
      return $self;
  }

  # override
  sub include {
    my ($self,$filename)=@_;
    push( @incFiles, $filename );
    $self->SUPER::include($filename);
  }

  # method specific to this class -> report includes
  sub report {
      my $self = shift;

      foreach my $f (@incFiles) {
         printf "$f\n",
      }
  }


package main;
use Getopt::Long;
use IO::File;

use Verilog::Netlist;
use Verilog::Getopt;
use strict;
use warnings;

my $opt = new Verilog::Getopt;
    @ARGV = $opt->parameter(@ARGV);

my $vp = VlogIncludeResolver->new(
  options=>$opt,
#  debug=>1
);

# *** TBD *** file name(s) to be passed from cmd line
$vp->open(filename=>"verilog/mod.v");

while (defined (my $line = $vp->getline())) {
}

$vp->report();