Multiplex

multiplex.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity multiplex is 
    Port ( 
        MIn0  : in  STD_LOGIC_VECTOR (1 downto 0);
        MIn1  : in  STD_LOGIC_VECTOR (1 downto 0);
        MOut  : out STD_LOGIC_VECTOR (1 downto 0);
        MCtrl : in  STD_LOGIC
    );
end multiplex;

architecture Behavioral of multiplex is
begin
    MOut <= MIn0 when MCtrl ='0' else MIn1;
end Behavioral;

multiplex_test.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity multiplex_tb is
    --  Port ( );
end multiplex_tb;

architecture Behavioral of multiplex_tb is
    
    component multiplex
        Port (
            MIn0  : in  STD_LOGIC_VECTOR (1 downto 0);
            MIn1  : in  STD_LOGIC_VECTOR (1 downto 0);
            MOut  : out STD_LOGIC_VECTOR (1 downto 0);
            MCtrl : in  STD_LOGIC
        );
    end component;
    
    signal in0_sig  : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal in1_sig  : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal out_sig  : STD_LOGIC_VECTOR (1 downto 0);
    signal ctrl_sig : STD_LOGIC;
    
begin
    
    U1_Test : Multiplex
        port map(
            MIn0  => in0_sig,
            MIn1  => in1_sig,
            MOut  => out_sig,
            MCtrl => ctrl_sig
        );
    
    tb : process
    begin
        in0_sig  <= "00";
        in1_sig  <= "11";
        ctrl_sig <= '0';
        wait for 1 ns;
        assert out_sig = "00"
            report "wrong bus result" severity error;
        wait for 10 ns;
        
        in0_sig  <= "00";
        in1_sig  <= "11";
        ctrl_sig <= '1';
        wait for 1 ns;
        assert out_sig = "11"
            report "wrong bus result" severity error;
        wait for 10 ns;
        
        in0_sig  <= "01";
        in1_sig  <= "10";
        ctrl_sig <= '0';
        wait for 1 ns;
        assert out_sig = "01"
            report "wrong bus result" severity error;
        wait for 10 ns;
        
        in0_sig  <= "01";
        in1_sig  <= "10";
        ctrl_sig <= '1';
        wait for 1 ns;
        assert out_sig = "10"
            report "wrong bus result" severity error;
        wait for 10 ns;
        
        in0_sig  <= "10";
        in1_sig  <= "01";
        ctrl_sig <= '0';
        wait for 1 ns;
        assert out_sig = "10"
            report "wrong bus result" severity error;
        wait for 10 ns;
        
        in0_sig  <= "10";
        in1_sig  <= "01";
        ctrl_sig <= '1';
        wait for 1 ns;
        assert out_sig = "01"
            report "wrong bus result" severity error;
        wait for 10 ns;
        
        in0_sig  <= "11";
        in1_sig  <= "00";
        ctrl_sig <= '0';
        wait for 1 ns;
        assert out_sig = "11"
            report "wrong bus result" severity error;
        wait for 10 ns;
        
        in0_sig  <= "11";
        in1_sig  <= "00";
        ctrl_sig <= '1';
        wait for 1 ns;
        assert out_sig = "00"
            report "wrong bus result" severity error;
        wait for 10 ns;
        
        assert false report "Tests successful" severity note;
        wait;
    end process;
    
end Behavioral;