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brinsche/Adder.vhd

Created December 6, 2017 11:09
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Adder.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OneBitAdder is
Port (
in0 : in STD_LOGIC;
in1 : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC
);
end OneBitAdder;
architecture Behavioral of OneBitAdder is
begin
sum <= in0 XOR in1 XOR cin;
cout <= (in0 AND in1) OR (cin AND in0) OR (cin AND in1);
end Behavioral;
Raw
Adder_tb.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adder_tb is
-- Port ( );
end adder_tb;
architecture Behavioral of adder_tb is
component OneBitAdder
Port (
in0 : in STD_LOGIC;
in1 : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC
);
end component;
signal tin0 : STD_LOGIC := '0';
signal tin1 : STD_LOGIC := '0';
signal tcin : STD_LOGIC := '0';
signal tsum : STD_LOGIC;
signal tcout : STD_LOGIC;
begin
U1_Test : OneBitAdder
port map(
in0 => tin0,
in1 => tin1,
cin => tcin,
sum => tsum,
cout => tcout
);
tb : process
begin
tin0 <= '0';
tin1 <= '0';
tcin <= '0';
wait for 1 ns;
assert tsum = '0'
report "wrong sum" severity error;
assert tcout = '0'
report "wrong carry out" severity error;
wait for 10 ns;
tin0 <= '0';
tin1 <= '1';
tcin <= '0';
wait for 1 ns;
assert tsum = '1'
report "wrong sum" severity error;
assert tcout = '0'
report "wrong carry out" severity error;
wait for 10 ns;
tin0 <= '1';
tin1 <= '0';
tcin <= '0';
wait for 1 ns;
assert tsum = '1'
report "wrong sum" severity error;
assert tcout = '0'
report "wrong carry out" severity error;
wait for 10 ns;
tin0 <= '1';
tin1 <= '1';
tcin <= '0';
wait for 1 ns;
assert tsum = '0'
report "wrong sum" severity error;
assert tcout = '1'
report "wrong carry out" severity error;
wait for 10 ns;
tin0 <= '0';
tin1 <= '0';
tcin <= '1';
wait for 1 ns;
assert tsum = '1'
report "wrong sum" severity error;
assert tcout = '0'
report "wrong carry out" severity error;
wait for 10 ns;
tin0 <= '0';
tin1 <= '1';
tcin <= '1';
wait for 1 ns;
assert tsum = '0'
report "wrong sum" severity error;
assert tcout = '1'
report "wrong carry out" severity error;
wait for 10 ns;
tin0 <= '1';
tin1 <= '0';
tcin <= '1';
wait for 1 ns;
assert tsum = '0'
report "wrong sum" severity error;
assert tcout = '1'
report "wrong carry out" severity error;
wait for 10 ns;
tin0 <= '1';
tin1 <= '1';
tcin <= '1';
wait for 1 ns;
assert tsum = '1'
report "wrong sum" severity error;
assert tcout = '1'
report "wrong carry out" severity error;
wait for 10 ns;
wait;
end process;
end Behavioral;
Raw
two_bit_adder.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TwoBitAdder is
Port (
t_in0 : in STD_LOGIC_VECTOR (1 downto 0);
t_in1 : in STD_LOGIC_VECTOR (1 downto 0);
t_cin : in STD_LOGIC;
t_sum : out STD_LOGIC_VECTOR (2 downto 0)
);
end TwoBitAdder;
architecture Behavioral of TwoBitAdder is
component OneBitAdder is
Port (
in0 : in STD_LOGIC;
in1 : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC
);
end component;
signal sum : STD_LOGIC_VECTOR (2 downto 0);
signal carry_over : STD_LOGIC;
begin
adder1 : OneBitAdder port map(
in0 => t_in0(0),
in1 => t_in1(0),
cin => t_cin,
sum => sum(0),
cout => carry_over
);
adder2 : OneBitAdder port map(
in0 => t_in0(1),
in1 => t_in1(1),
cin => carry_over,
sum => sum(1),
cout => sum(2)
);
t_sum <= sum;
end Behavioral;
Raw
two_bit_adder_tb.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity two_bit_adder_tb is
-- Port ( );
end two_bit_adder_tb;
architecture Behavioral of two_bit_adder_tb is
component TwoBitAdder is
Port (
t_in0 : in STD_LOGIC_VECTOR (1 downto 0);
t_in1 : in STD_LOGIC_VECTOR (1 downto 0);
t_cin : in STD_LOGIC;
t_sum : out STD_LOGIC_VECTOR (2 downto 0)
);
end component;
signal tin0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal tin1 : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal tcin : STD_LOGIC := '0';
signal tsum : STD_LOGIC_VECTOR (2 downto 0);
begin
U1_Test : TwoBitAdder
port map(
t_in0 => tin0,
t_in1 => tin1,
t_cin => tcin,
t_sum => tsum
);
tb : process
begin
-- tin0 = 00
tin0 <= "00";
tin1 <= "00";
wait for 1 ns;
assert tsum = "000"
report "wrong sum" severity error;
wait for 10 ns;
tin0 <= "00";
tin1 <= "01";
wait for 1 ns;
assert tsum = "001"
report "wrong sum" severity error;
wait for 10 ns;
tin0 <= "00";
tin1 <= "10";
wait for 1 ns;
assert tsum = "010"
report "wrong sum" severity error;
wait for 10 ns;
tin0 <= "00";
tin1 <= "11";
wait for 1 ns;
assert tsum = "011"
report "wrong sum" severity error;
wait for 10 ns;
-- tin0 = 01
tin0 <= "01";
tin1 <= "00";
wait for 1 ns;
assert tsum = "001"
report "wrong sum" severity error;
wait for 10 ns;
tin0 <= "01";
tin1 <= "01";
wait for 1 ns;
assert tsum = "010"
report "wrong sum" severity error;
wait for 10 ns;
tin0 <= "01";
tin1 <= "10";
wait for 1 ns;
assert tsum = "011"
report "wrong sum" severity error;
wait for 10 ns;
tin0 <= "01";
tin1 <= "11";
wait for 1 ns;
assert tsum = "100"
report "wrong sum" severity error;
wait for 10 ns;
-- tin0 = 10
tin0 <= "10";
tin1 <= "00";
wait for 1 ns;
assert tsum = "010"
report "wrong sum" severity error;
wait for 10 ns;
tin0 <= "10";
tin1 <= "01";
wait for 1 ns;
assert tsum = "011"
report "wrong sum" severity error;
wait for 10 ns;
tin0 <= "10";
tin1 <= "10";
wait for 1 ns;
assert tsum = "100"
report "wrong sum" severity error;
wait for 10 ns;
tin0 <= "10";
tin1 <= "11";
wait for 1 ns;
assert tsum = "101"
report "wrong sum" severity error;
wait for 10 ns;
-- tin0 = 11
tin0 <= "11";
tin1 <= "00";
wait for 1 ns;
assert tsum = "011"
report "wrong sum" severity error;
wait for 10 ns;
tin0 <= "11";
tin1 <= "01";
wait for 1 ns;
assert tsum = "100"
report "wrong sum" severity error;
wait for 10 ns;
tin0 <= "11";
tin1 <= "10";
wait for 1 ns;
assert tsum = "101"
report "wrong sum" severity error;
wait for 10 ns;
tin0 <= "11";
tin1 <= "11";
wait for 1 ns;
assert tsum = "110"
report "wrong sum" severity error;
wait for 10 ns;
wait;
end process;
end Behavioral;
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