verilog file's correct tool

conv.py

import re
import sys

re_v = re.compile('(\s+)(reg|wire)(\s+)(\w+)\s*(\[\d+:0\]);')

for line in sys.stdin:
    line = line[:-1]  # to remove new line
    result = re_v.search(line)
    if result:
        g = result.groups()
        print "%s%s\t%s\t%s;" % (g[0], g[1], g[4], g[3])
    else:
        print line