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Phung Cheng Fei buttercutter

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buttercutter / PKGBUILD
Created Oct 3, 2021
PKGBUILD for Modelsim
View PKGBUILD
pkgname=modelsim
# Keep dot in _patchver
_mainver=20.1; _patchver=.1; _buildver=720
pkgver=${_mainver}${_patchver}.${_buildver}
pkgrel=1
# According to the installer script, these dependencies are needed for the installer
depends=('ld-lsb' 'lib32-expat' 'lib32-fontconfig' 'lib32-freetype2' 'lib32-glibc'
'lib32-gtk2' 'lib32-libcanberra' 'lib32-libpng' 'lib32-libice' 'lib32-libsm'
View Sub-1_Volt_OTA.asc

Version 4 SHEET 1 2232 772 WIRE -96 -240 -128 -240 WIRE 48 -240 -16 -240 WIRE 96 -240 48 -240 WIRE 224 -240 176 -240 WIRE 704 -192 704 -240 WIRE 1216 -192 1216 -240 WIRE 1728 -176 1728 -224 WIRE 1920 -176 1920 -224

@buttercutter
buttercutter / gdas.py
Last active Jun 17, 2022
GDAS : Searching for A Robust Neural Architecture in Four GPU Hours
View gdas.py
# https://github.com/D-X-Y/AutoDL-Projects/issues/99
import torch
import torch.utils.data
import torch.nn as nn
import torch.nn.functional as F
import torch.optim as optim
import torchvision
import torchvision.transforms as transforms
@buttercutter
buttercutter / Data_strobe_enable_circuitry.asc
Last active Mar 14, 2021
Circuit replication of "Data strobe enable circuitry" as described in https://patents.google.com/patent/US9001595
View Data_strobe_enable_circuitry.asc

Version 4 SHEET 1 1032 900 WIRE -1408 -624 -1664 -624 WIRE -1248 -624 -1408 -624 WIRE -976 -624 -1184 -624 WIRE -1248 -592 -1408 -592 WIRE -1104 -592 -1184 -592 WIRE -1664 -544 -1664 -624 WIRE 640 -480 640 -560 WIRE 880 -480 880 -560

@buttercutter
buttercutter / darts.py
Created Feb 27, 2021
DARTS: DIFFERENTIABLE ARCHITECTURE SEARCH https://arxiv.org/pdf/1806.09055.pdf
View darts.py
import torch
import torch.utils.data
import torch.nn as nn
import torch.nn.functional as F
import torch.optim as optim
import torchvision
import torchvision.transforms as transforms
import numpy as np
View clock_gate_post_control.v
// Credit : https://github.com/YosysHQ/yosys-bigsim/blob/master/openmsp430/rtl/omsp_clock_gate.v
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
@buttercutter
buttercutter / GFSK.asc
Last active Feb 12, 2021
A simple GFSK demodulator inspired from the paper : A GFSK demodulator for low-IF Bluetooth receiver
View GFSK.asc

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@buttercutter
buttercutter / ddr3_memory_controller.sby
Last active Feb 12, 2022
A simple DDR3 memory controller
View ddr3_memory_controller.sby
[tasks]
proof
cover
[options]
proof: mode prove
proof: depth 10
cover: mode cover
cover: depth 40
@buttercutter
buttercutter / phase_shifter.sch
Last active Jan 29, 2021
A phase shifter circuit from the paper: A Full X-Band Phased-Array Transmit Receive Module Chip in 65-nm CMOS Technology
View phase_shifter.sch
v {xschem version=2.9.9 file_version=1.2 }
G {}
K {}
V {}
S {}
E {}
N 60 -10 180 -10 { lab=Vs1}
N 180 -10 270 -10 { lab=Vs1}
N 60 310 270 310 { lab=#net1}
N -80 290 -80 310 { lab=#net2}
@buttercutter
buttercutter / Net.py
Last active Jan 31, 2021
A simple neural network for tic-tac-toe game
View Net.py
import torch
import torch.utils.data
import torch.nn as nn
import torch.optim as optim
import numpy as np
import pandas as pd
from collections import Counter
from sklearn.model_selection import train_test_split