Version 4 SHEET 1 2232 772 WIRE -96 -240 -128 -240 WIRE 48 -240 -16 -240 WIRE 96 -240 48 -240 WIRE 224 -240 176 -240 WIRE 704 -192 704 -240 WIRE 1216 -192 1216 -240 WIRE 1728 -176 1728 -224 WIRE 1920 -176 1920 -224
View PKGBUILD
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pkgname=modelsim | |
# Keep dot in _patchver | |
_mainver=20.1; _patchver=.1; _buildver=720 | |
pkgver=${_mainver}${_patchver}.${_buildver} | |
pkgrel=1 | |
# According to the installer script, these dependencies are needed for the installer | |
depends=('ld-lsb' 'lib32-expat' 'lib32-fontconfig' 'lib32-freetype2' 'lib32-glibc' | |
'lib32-gtk2' 'lib32-libcanberra' 'lib32-libpng' 'lib32-libice' 'lib32-libsm' |
View gdas.py
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# https://github.com/D-X-Y/AutoDL-Projects/issues/99 | |
import torch | |
import torch.utils.data | |
import torch.nn as nn | |
import torch.nn.functional as F | |
import torch.optim as optim | |
import torchvision | |
import torchvision.transforms as transforms |
View Data_strobe_enable_circuitry.asc
Version 4 SHEET 1 1032 900 WIRE -1408 -624 -1664 -624 WIRE -1248 -624 -1408 -624 WIRE -976 -624 -1184 -624 WIRE -1248 -592 -1408 -592 WIRE -1104 -592 -1184 -592 WIRE -1664 -544 -1664 -624 WIRE 640 -480 640 -560 WIRE 880 -480 880 -560
View darts.py
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import torch | |
import torch.utils.data | |
import torch.nn as nn | |
import torch.nn.functional as F | |
import torch.optim as optim | |
import torchvision | |
import torchvision.transforms as transforms | |
import numpy as np |
View clock_gate_post_control.v
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// Credit : https://github.com/YosysHQ/yosys-bigsim/blob/master/openmsp430/rtl/omsp_clock_gate.v | |
//---------------------------------------------------------------------------- | |
// Copyright (C) 2009 , Olivier Girard | |
// | |
// Redistribution and use in source and binary forms, with or without | |
// modification, are permitted provided that the following conditions | |
// are met: | |
// * Redistributions of source code must retain the above copyright | |
// notice, this list of conditions and the following disclaimer. | |
// * Redistributions in binary form must reproduce the above copyright |
View GFSK.asc
Version 4 SHEET 1 1976 956 WIRE 512 -480 416 -480 WIRE 656 -480 592 -480 WIRE 1104 -416 1104 -464 WIRE -832 -384 -832 -432 WIRE -1296 -256 -1536 -256 WIRE -1152 -256 -1296 -256 WIRE -1088 -256 -1152 -256 WIRE -976 -256 -1024 -256
View ddr3_memory_controller.sby
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[tasks] | |
proof | |
cover | |
[options] | |
proof: mode prove | |
proof: depth 10 | |
cover: mode cover | |
cover: depth 40 |
View phase_shifter.sch
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v {xschem version=2.9.9 file_version=1.2 } | |
G {} | |
K {} | |
V {} | |
S {} | |
E {} | |
N 60 -10 180 -10 { lab=Vs1} | |
N 180 -10 270 -10 { lab=Vs1} | |
N 60 310 270 310 { lab=#net1} | |
N -80 290 -80 310 { lab=#net2} |
View Net.py
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import torch | |
import torch.utils.data | |
import torch.nn as nn | |
import torch.optim as optim | |
import numpy as np | |
import pandas as pd | |
from collections import Counter | |
from sklearn.model_selection import train_test_split |
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