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module detect_start_bit(clk, serial_in, start_detected); // just a falling edge detector | |
input clk, serial_in; | |
output reg start_detected = 0; | |
reg previously_idle = 1; | |
always @(posedge clk) | |
begin | |
if((!serial_in) && (previously_idle) && (!start_detected)) |
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`timescale 1ps/100fs | |
module baud_generator_tb; | |
reg clk; | |
wire baud_out; | |
baud_generator BG1 | |
( | |
.clk(clk), | |
.baud_out(baud_out) |
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#include <pthread.h> | |
#include <semaphore.h> | |
#include <stdio.h> | |
#include <stdlib.h> | |
#include <unistd.h> | |
#include <errno.h> | |
#include <sys/mman.h> | |
#include <sys/types.h> | |
#include <sys/stat.h> | |
#include <fcntl.h> |
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module xillydemo | |
( | |
input clk_100, | |
input otg_oc, | |
inout [55:0] PS_GPIO, | |
output [3:0] GPIO_LED, | |
output [3:0] vga4_blue, | |
output [3:0] vga4_green, | |
output [3:0] vga4_red, | |
output vga_hsync, |
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############################################################################### | |
# Copyright (c) 2016, Xilinx, Inc. | |
# All rights reserved. | |
# | |
# Redistribution and use in source and binary forms, with or without | |
# modification, are permitted provided that the following conditions are met: | |
# | |
# 1. Redistributions of source code must retain the above copyright notice, | |
# this list of conditions and the following disclaimer. |
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#include <stdio.h> | |
#include <pthread.h> | |
#include <stdlib.h> | |
#include <unistd.h> | |
#include <errno.h> | |
#include <sys/types.h> | |
#include <sys/stat.h> | |
#include <fcntl.h> | |
#include <string.h> | |
#include <stdint.h> |
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// ---------------------------------------------------------------------- | |
// Copyright (c) 2016, The Regents of the University of California All | |
// rights reserved. | |
// | |
// Redistribution and use in source and binary forms, with or without | |
// modification, are permitted provided that the following conditions are | |
// met: | |
// | |
// * Redistributions of source code must retain the above copyright | |
// notice, this list of conditions and the following disclaimer. |
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`timescale 1ns/1ns | |
//---------------------------------------------------------------------------- | |
// This software is Copyright © 2012 The Regents of the University of | |
// California. All Rights Reserved. | |
// | |
// Permission to copy, modify, and distribute this software and its | |
// documentation for educational, research and non-profit purposes, without | |
// fee, and without a written agreement is hereby granted, provided that the | |
// above copyright notice, this paragraph and the following three paragraphs | |
// appear in all copies. |
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* gnetlist -g spice-noqsi -o test_active_inductor.net test_active_inductor.sch | |
AC Analysis Mon Feb 12 23:17:37 2018 | |
-------------------------------------------------------------------------------- | |
Index frequency s11 | |
-------------------------------------------------------------------------------- | |
0 1.000000e+02 9.997594e-01, 1.132451e-13 | |
1 1.001001e+02 9.997594e-01, 1.133585e-13 | |
2 1.002002e+02 9.997594e-01, 1.134718e-13 | |
3 1.003003e+02 9.997594e-01, 1.135852e-13 | |
4 1.004004e+02 9.997594e-01, 1.136985e-13 |
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`default_nettype none | |
// for connecting Tx and Rx together | |
`define LOOPBACK 1 | |
module test_UART(reset_tx, reset_rx, serial_out, enable, i_data, o_busy, received_data, data_is_valid, rx_error, | |
`ifndef FORMAL | |
clk | |
`endif); |