md86783.cfg

# Marvell SheevaPlug

source [find target/feroceon.cfg]

set reset_mode halt
set speed 5000

proc sp_is_halted {} {
    global _TARGETNAME
    return [expr [string compare [$_TARGETNAME curstate] "halted" ] == 0]
}

proc init_board { } {
    global _TARGETNAME
    global _CHIPNAME
    global speed

    $_TARGETNAME configure \
        -work-area-phys 0x100000 \
        -work-area-size 65536 \
        -work-area-backup 0

    adapter_khz $speed
    adapter_nsrst_delay 500

    $_TARGETNAME configure -event reset-start {
        adapter_khz 2000
    }

    $_TARGETNAME configure -event reset-assert {
        global reset_mode
        global speed

        jtag_reset 0 1
        feroceon.cpu arp_examine
        halt 0
        jtag_reset 0 0
        wait_halt
        setup_dram

        if ([string match run $reset_mode]) {
            resume
        }
        set reset_mode halt
        adapter_khz $speed
    }

    set _FLASHNAME $_CHIPNAME.flash
    nand device $_FLASHNAME orion 0 0xd8000000
}

proc init_reset {mode} {
    global reset_mode
    set reset_mode $mode

    # We need to detect CPU get halted, so exit from halt
    if { [sp_is_halted] } {
        echo "Resuming CPU to detect reset"
        resume
    }

    # Execute default init_reset{mode}
    jtag arp_init-reset
}

proc setup_dram {} {
    puts "Configuring SDRAM controller"
    arm mcr 15 0 0 1 0 0x00052078
    mww 0xd00100e0 0x1b1b1b1b ;#  DDR SDRAM Configuration Register
    mww 0xd0001400 0x43010C30 ;#  DDR SDRAM Configuration Register
    mww 0xd0001404 0x39543000 ;#  Dunit Control Low Register<
    mww 0xd0001408 0x22125451 ;#  DDR SDRAM Timing (Low) Register
    mww 0xd000140C 0x00000833 ;#  DDR SDRAM Timing (High) Register
    mww 0xd0001410 0x0000000C ;#  DDR SDRAM Address Control Register
    mww 0xd0001414 0x00000000 ;#  DDR SDRAM Open Pages Control Register
    mww 0xd0001418 0x00000000 ;#  DDR SDRAM Operation Register
    mww 0xd000141C 0x00000652 ;#  DDR SDRAM Mode Register
    mww 0xd0001420 0x00000004 ;#  DDR SDRAM Extended Mode Register
    mww 0xd0001424 0x0000F17F ;#  Dunit Control High Register
    mww 0xd0001428 0x00085520 ;#  Dunit Control High Register
    mww 0xd000147c 0x00008552 ;#  Dunit Control High Register
    mww 0xd0001504 0x0FFFFFF1 ;#  CS0n Size Register
    mww 0xd0001508 0x10000000 ;#  CS1n Base Register
    mww 0xd000150C 0x00FFFFF0 ;#  CS1n Size Register
    mww 0xd0001514 0x00FFFFF0 ;#  CS2n Size Register
    mww 0xd000151C 0x00FFFFF0 ;#  CS3n Size Register
    mww 0xd0001494 0x00010000 ;#  DDR2 SDRAM ODT Control (Low) Register
    mww 0xd0001498 0x00000000 ;#  DDR2 SDRAM ODT Control (High) REgister
    mww 0xd000149C 0x0000e403 ;#  DDR2 Dunit ODT Control Register
    mww 0xd0001480 0x00000001 ;#  DDR SDRAM Initialization Control Register
    mww 0xd0020204 0x00000000 ;#  Main IRQ Interrupt Mask Register
    mww 0xD0010000 0x21111111 ;#  MPP  0 to 7
    mww 0xD0010004 0x30002211 ;#  MPP  8 to 15
    mww 0xD0010008 0x00551130 ;#  MPP 16 to 23
}


proc board_flash_uboot { } {
    # reflash the u-Boot binary and reboot into it
    reset init
    nand probe 0
    nand erase 0 0x0 0xa0000
    nand write 0 u-boot.kwb 0 oob_softecc_kw
    resume

}

proc board_flash_uboot_env { } {
    # reflash the u-Boot environment variables area
    reset init
    nand probe 0
    nand erase 0 0xa0000 0x40000
    nand write 0 uboot-env.bin 0xa0000 oob_softecc_kw
    resume

}

proc board_load_uboot { } {
    reset init
    load_image u-boot
    verify_image u-boot
    resume 0x00600000
}