G-Sync Arria V Module Reverse notes

readme

Location of the zip with the quartus project, scans and this note:

https://drive.google.com/file/d/19l7rQpiQJmDnbOJQavnp8BZulNxUG0uI/view?usp=sharing


Power 

	I injected 5V on C60 (Fat ceramic cap , on top lower right corner near the sodimm edge)
	The Module needs a fair ammount of current to start up properly. I had my lab supply at 3A current 
	limit, with the original config bitstream off the config prom  on the module it draws about 700mA after startup

J501 , FPC Footprint on bottom layer

	Pin
	1	VCC(2.5?)
	2	D9 (With pulldown resistor)
	3	A10 (With pulldown resistor)
	4	GND
	5	E9 (With pulldown resistor)
	6	B10

J503, Top Pinheader

	1 	TMS
	2 	TDI
	3 	2.5V (Vtarget)
	4	TDO
	5	TCK
	6	GND

J502 , Top Pinheader

	Unknown , but seems I2C to the MSP430 and Powermanagment.
	Leave all open and the Module seems to powerup 

Clocks
   
   T1 CLK1 (not yet confirmed!)
   T4 CLK2 (39.80MHz Measured (40MHz??) )



LEDs

	Red	A26
	Green A27

Burried / Tented Vias near S1 
	Found some pictures of very early G-Sync boards , these have a Pinheader at that location.
	Probably some kind of Jtag for an IP Core 
	Pinout from looking from above at the module , sodimm edge facing to you

    

	(Hole)

		1  (*)  (*)  8
		2  (*)  (*)  7
		3  (*)  (*)  6
		4  (*)  (*)  5

	 ----
	| S |
	| 1 | 
	 ----

	1 AE7
	2 AF7
	3 AK4
	4 AK5
	5 AJ6
	6 AK6
	7 AE6
	8 AF6

	I used them for DVI output :
	hdmi_out_

	These pins are also on bottom on some testpoints


DDR3 Pinout
	See the 3 Scans in the ZIP
	The numbers I wrote on the pins are the UART assignements according to the Quartus Project
	Still need to map these to the actual FPGA Pins
	The CK and CK_ differential line is terminated with 100Ohm , so it was a bit hard to scope the serial uart stream on
	these. After removing the termination resistor i'm quite sure its 137 for CK and 346 for CK_

	The Altera DDR3 IP Core doesnt support the 48bit wide interface used on the module out of the box.
	A little hack is needed to support the full width, the hack is using a custom user ECC controller, that way user logic can use the 3rd
	ddr chip and full 48bit data width
	https://fpgawiki.intel.com/wiki/Reference_Design_-_Cyclone_V_Hard_Memory_Controller_with_Avalon_MM_data_width_expanded_for_User_ECC

SODIMM Connector
	So far completley unprobed. I see many lines wiggle with the uart data , but didn't bother so far to map out.
	Further the SERDES is completely unconnected in the quartus project , so supply uart data on the serdes pins it 
        needs to switched into a passive mode. But i'm not even sure if one can do that with altera fpgas

Claude Schwarz 20.06.2019