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//AVR gcc config: workspace/.vscode/c_cpp_properties.json
{
"configurations": [
{
"name": "Linux avr-gcc",
"intelliSenseMode": "clang-x64",
"includePath": ["/usr/lib/avr/include"/*, "~/Dev/libavr"*/],
"compilerPath": "/usr/lib/avr/bin",
"browse": {
"path": ["${workspaceFolder}"],
@captdam
captdam / notes.md
Created March 31, 2021 05:31
AVR programmer notes

AVR programmer notes

Download from MCU (debug/backup):

sudo avrdude -p m328p -c arduino -P /dev/ttyACM0 -U flash:r:dump.hex:i
avr-objdump -m avr5 -s dump.hex			//Dump all w/o disassembly, avr5 is the arch name of m328p
avr-objdump -m avr5 -s -d -j .secX dump.hex	//Dump and disassembly sectionX

Upload to MCU (compile and program):

@captdam
captdam / process.c
Created March 30, 2021 14:09
video filter
#include <stdint.h>
#include <stdlib.h>
#include <stdio.h>
/**
xo: orginal data
xp: processed data (applied filter)
**/
#define FILENAME "./stage1.data"
@captdam
captdam / main.c
Last active February 1, 2021 08:33
Generic linked list
#include <stdio.h>
#include <stdlib.h>
#include <inttypes.h>
#include "./util.c"
int main() {
struct myData {
int v1;
int v2;
float f1;
@captdam
captdam / runled.v
Created January 14, 2021 07:26
SoC AXI test
module runled (
input wire clk,
input wire reset,
output wire [7:0] led,
output wire [14:0] hps_memory_mem_a,
output wire [2:0] hps_memory_mem_ba,
output wire hps_memory_mem_ck,
output wire hps_memory_mem_ck_n,
output wire hps_memory_mem_cke,
@captdam
captdam / float_display.c
Created October 17, 2020 11:06
Display each bits in floating number
#include <stdio.h>
#include <stdint.h>
int main() {
float a = 123.96875f;
uint32_t* ptr = &a; //float is 32-bit
printf("%f = ", a);
for (int i = 31; i >= 0; i--) {
printf("%c", (*ptr>>i) & 1 ? '1' : '0');
if (i == 31) putc(' ', stdout);
@captdam
captdam / avr-rc_calib.c
Created July 4, 2019 22:46
Calibrate AVR internal RC clock
#include <avr/io.h>
#include <avr/interrupt.h>
#define RC_CLOCK_CALIBRATE 0xA0
int main(void) {
CLKPR = 0x80;
CLKPR = 0x03; //Clk divider = 8
OSCCAL = RC_CLOCK_CALIBRATE;
@captdam
captdam / UART.v
Last active July 16, 2019 15:11
VLSI-2
module UART (baud,txData,rxData,sendData,sendWIP,receiveRequest,txPin,rxPin,clk,reset);
input [15:0] baud;
input [7:0] txData;
output [7:0] rxData;
reg [7:0] rxData;
input sendData;
output sendWIP;
@captdam
captdam / avr-8 register.asm
Last active June 14, 2019 12:52
Temp and saved register for GCC
;Scratch, save before call child, free to use in subroutine
#define _RA R0
;Always zero, do not modify
#define _RZERO R1
;Temp register, save before call child, free to use in subroutine
#define _RT0 R18 ;Arg3
#define _RT1 R19
#define _RT2 R20 ;Arg2
@captdam
captdam / uwinsiteTimetableGenerator.js
Created April 16, 2019 19:49
Generate a timetable on the new uWinSite page.
/*
How to use:
1. Login to your uWinSite
2. Go to: Manage Classes/View my Classes
3. Choose the semester, and you should see all your classes in the page.
4. Open the page inspector of your web browser.
5. Copy the code into the debugger and hit enter. The code is now embedded into the page.
6. Execute "timetable()" in the debuger.
7. The timetable will be generated, and it will be located at the bottom of the page.
*/