verilog_predefine.v

/*
 * Verilog Simulator checker by predefined macro.
 * 
 * Copyright (C) 2017 MURAMATSU Atsushi <amura@tomato.sakura.ne.jp>
 * 
 * Permission is hereby granted, free of charge, to any person
 * obtaining a copy of this software and associated documentation files
 * (the "Software"), to deal in the Software without restriction,
 * including without limitation the rights to use, copy, modify, merge,
 * publish, distribute, sublicense, and/or sell copies of the Software,
 * and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 * 
 * The above copyright notice and this permission notice shall be
 * included in all copies or substantial portions of the Software.
 * 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

module PREDEF;

   initial begin
`ifdef VCS
      $display("Synopsis VCS");
`endif
`ifdef INCA
      $display("Cadence NC-Verilog");
`endif
`ifdef MODEL_TECH
      $display("Mentor Graphics ModelSIM/Questa");
`endif
`ifdef XILINX_ISIM
      $display("Xilinx ISE Simulator");
`endif
`ifdef XILINX_SIMULATOR
      $display("Xilinx Vivado Simulator");
`endif
`ifdef __ICARUS__
      $display("Icarus Verilog <http://iverilog.icarus.com>");
`endif
`ifdef VERILATOR
      $display("Verilator <https://www.veripool.org/wiki/verilator>");
`endif
`ifdef Veritak
      $display("Veritak <http://www.sugawara-systems.com>");
`endif
`ifdef YOSYS
      $display("YOSYS <https://www.yosyshq.com/>");
`endif
`ifdef XILINX
      $display("Xilinx ISE Path");
`endif 
`ifdef XILINX_DSP
      $display("Xilinx DSP Path");
`endif 
`ifdef XILINX_EDK
      $display("Xilinx EDK Path");
`endif 
`ifdef XILINX_PLANHEAD
      $display("Xilinx Planhead Path");
`endif 
`ifdef ALTERA_RESERVED_QIS
      $display("Quartus");
`endif

   end // initial begin

endmodule // PREDEF