MemoryMask-Circt+Firtool

MemMask.scala

//> using scala "2.13.8"
//> using lib "edu.berkeley.cs::chisel3::3.5.4"
//> using lib "com.sifive::chisel-circt::0.6.0"
//> using plugin "edu.berkeley.cs:::chisel3-plugin::3.5.4"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-P:chiselplugin:genBundleElements", "-Ywarn-unused"

import chisel3._
import circt.stage.ChiselStage
import chisel3.stage.ChiselGeneratorAnnotation

class ByteEnableMemory(val words: Int, val bits: Int, val addrBits: Int)
    extends Module {
  val io = IO(new Bundle {
    val dataOut = Output(Vec(bits / 8, UInt(8.W)))
    val dataIn = Input(Vec(bits / 8, UInt(8.W)))
    val readAddr = Input(UInt(addrBits.W))
    val readEnable = Input(Bool())
    val writeAddr = Input(UInt(addrBits.W))
    val writeMask = Input(Vec(bits / 8, Bool()))
  })

  val mem = SyncReadMem(words, Vec(bits / 8, UInt(8.W)))

  mem.write(io.writeAddr, io.dataIn, io.writeMask)
  io.dataOut := mem.read(io.readAddr, io.readEnable)
}

object MemoryMask extends App {
  println(ChiselStage.emitSystemVerilog(new ByteEnableMemory(1024, 64, 32)))
}

Memory.fir

circuit ByteEnableMemory :
  module ByteEnableMemory :
    input clock : Clock
    input reset : UInt<1>
    output io : { dataOut : UInt<8>[8], flip dataIn : UInt<8>[8], flip readAddr : UInt<32>, flip readEnable : UInt<1>, flip writeAddr : UInt<32>, flip writeMask : UInt<1>[8]}

    smem mem : UInt<8>[8] [1024] @[MemoryMask.scala 39:24]
    node _T = bits(io.writeAddr, 9, 0)
    write mport MPORT = mem[_T], clock
    when io.writeMask[0] :
      MPORT[0] <= io.dataIn[0]
    when io.writeMask[1] :
      MPORT[1] <= io.dataIn[1]
    when io.writeMask[2] :
      MPORT[2] <= io.dataIn[2]
    when io.writeMask[3] :
      MPORT[3] <= io.dataIn[3]
    when io.writeMask[4] :
      MPORT[4] <= io.dataIn[4]
    when io.writeMask[5] :
      MPORT[5] <= io.dataIn[5]
    when io.writeMask[6] :
      MPORT[6] <= io.dataIn[6]
    when io.writeMask[7] :
      MPORT[7] <= io.dataIn[7]
    wire _WIRE : UInt @[MemoryMask.scala 42:25]
    _WIRE is invalid @[MemoryMask.scala 42:25]
    when io.readEnable : @[MemoryMask.scala 42:25]
      _WIRE <= io.readAddr @[MemoryMask.scala 42:25]
      node _T_1 = or(_WIRE, UInt<10>("h0")) @[MemoryMask.scala 42:25]
      node _T_2 = bits(_T_1, 9, 0) @[MemoryMask.scala 42:25]
      read mport MPORT_1 = mem[_T_2], clock @[MemoryMask.scala 42:25]
    io.dataOut <= MPORT_1 @[MemoryMask.scala 42:14]

output.v

❯ firtool --version
LLVM (http://llvm.org/):
  LLVM version 16.0.0git
  Optimized build.
  Default target: x86_64-apple-darwin21.6.0
  Host CPU: skylake

CIRCT sifive/1/22/0
❯ scli MemoryMask.scala
Compiling project (Scala 2.13.8, JVM)
Warning: 12 feature warnings; re-run with -feature for details
Compiled project (Scala 2.13.8, JVM)
Running CIRCT: 'firtool -format=fir -warn-on-unprocessed-annotations -verify-each=false -disable-infer-rw -dedup -annotation-file ByteEnableMemory.anno.json < $input'

----------------------------------------------------------------                                 
                                 
// Generated by CIRCT sifive/1/22/0
// Standard header to adapt well known macros to our needs.
`ifdef RANDOMIZE_MEM_INIT
  `define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT

// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
  `define RANDOM $random
`endif // not def RANDOM

// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
  `define INIT_RANDOM
`endif // not def INIT_RANDOM

// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
  `define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY

// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifdef RANDOMIZE
  `ifdef VERILATOR
    `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
  `else  // VERILATOR
    `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
  `endif // VERILATOR
`else  // RANDOMIZE
  `define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE

// VCS coverage exclude_file
module mem_0_combMem(	// MemoryMask.scala:39:24
  input  [9:0] R0_addr,
  input        R0_en,
               R0_clk,
  input  [9:0] W0_addr,
  input        W0_en,
               W0_clk,
  input  [7:0] W0_data,
  output [7:0] R0_data);

  reg  [7:0] Memory[0:1023];	// MemoryMask.scala:39:24
  reg        _GEN;	// MemoryMask.scala:39:24
  reg  [9:0] _GEN_0;	// MemoryMask.scala:39:24
  always @(posedge R0_clk) begin	// MemoryMask.scala:39:24
    _GEN <= R0_en;	// MemoryMask.scala:39:24
    _GEN_0 <= R0_addr;	// MemoryMask.scala:39:24
  end // always @(posedge)
  wire [7:0] _GEN_1;	// MemoryMask.scala:39:24
  /* synopsys infer_mux_override */
  assign _GEN_1 = Memory[_GEN_0] /* cadence map_to_mux */;	// MemoryMask.scala:39:24
  always @(posedge W0_clk) begin	// MemoryMask.scala:39:24
    if (W0_en)	// MemoryMask.scala:39:24
      Memory[W0_addr] <= W0_data;	// MemoryMask.scala:39:24
  end // always @(posedge)
  `ifndef SYNTHESIS	// MemoryMask.scala:39:24
    `ifdef RANDOMIZE_MEM_INIT	// MemoryMask.scala:39:24
      integer initvar;	// MemoryMask.scala:39:24
      reg [31:0] _RANDOM_MEM;	// MemoryMask.scala:39:24
    `endif // RANDOMIZE_MEM_INIT
    `ifdef RANDOMIZE_REG_INIT	// MemoryMask.scala:39:24
      reg [31:0] _RANDOM;	// MemoryMask.scala:39:24
    `endif // RANDOMIZE_REG_INIT
    initial begin	// MemoryMask.scala:39:24
      `INIT_RANDOM_PROLOG_	// MemoryMask.scala:39:24
      `ifdef RANDOMIZE_MEM_INIT	// MemoryMask.scala:39:24
        for (initvar = 0; initvar < 1024; initvar = initvar + 1) begin
          _RANDOM_MEM = {`RANDOM};
          Memory[initvar] = _RANDOM_MEM[7:0];
        end	// MemoryMask.scala:39:24
      `endif // RANDOMIZE_MEM_INIT
      `ifdef RANDOMIZE_REG_INIT	// MemoryMask.scala:39:24
        _RANDOM = {`RANDOM};	// MemoryMask.scala:39:24
        _GEN = _RANDOM[0];	// MemoryMask.scala:39:24
        _GEN_0 = _RANDOM[10:1];	// MemoryMask.scala:39:24
      `endif // RANDOMIZE_REG_INIT
    end // initial
  `endif // not def SYNTHESIS
  assign R0_data = _GEN ? _GEN_1 : 8'bx;	// MemoryMask.scala:39:24
endmodule

module ByteEnableMemory(	// <stdin>:2:10
  input         clock,
                reset,
  input  [7:0]  io_dataIn_0,
                io_dataIn_1,
                io_dataIn_2,
                io_dataIn_3,
                io_dataIn_4,
                io_dataIn_5,
                io_dataIn_6,
                io_dataIn_7,
  input  [31:0] io_readAddr,
  input         io_readEnable,
  input  [31:0] io_writeAddr,
  input         io_writeMask_0,
                io_writeMask_1,
                io_writeMask_2,
                io_writeMask_3,
                io_writeMask_4,
                io_writeMask_5,
                io_writeMask_6,
                io_writeMask_7,
  output [7:0]  io_dataOut_0,
                io_dataOut_1,
                io_dataOut_2,
                io_dataOut_3,
                io_dataOut_4,
                io_dataOut_5,
                io_dataOut_6,
                io_dataOut_7);

  mem_0_combMem mem_0_ext (	// MemoryMask.scala:39:24
    .R0_addr (io_readAddr[9:0]),	// MemoryMask.scala:42:25
    .R0_en   (io_readEnable),
    .R0_clk  (clock),
    .W0_addr (io_writeAddr[9:0]),	// <stdin>:8:15
    .W0_en   (io_writeMask_0),
    .W0_clk  (clock),
    .W0_data (io_dataIn_0),
    .R0_data (io_dataOut_0)
  );
  mem_0_combMem mem_1_ext (	// MemoryMask.scala:39:24
    .R0_addr (io_readAddr[9:0]),	// MemoryMask.scala:42:25
    .R0_en   (io_readEnable),
    .R0_clk  (clock),
    .W0_addr (io_writeAddr[9:0]),	// <stdin>:8:15
    .W0_en   (io_writeMask_1),
    .W0_clk  (clock),
    .W0_data (io_dataIn_1),
    .R0_data (io_dataOut_1)
  );
  mem_0_combMem mem_2_ext (	// MemoryMask.scala:39:24
    .R0_addr (io_readAddr[9:0]),	// MemoryMask.scala:42:25
    .R0_en   (io_readEnable),
    .R0_clk  (clock),
    .W0_addr (io_writeAddr[9:0]),	// <stdin>:8:15
    .W0_en   (io_writeMask_2),
    .W0_clk  (clock),
    .W0_data (io_dataIn_2),
    .R0_data (io_dataOut_2)
  );
  mem_0_combMem mem_3_ext (	// MemoryMask.scala:39:24
    .R0_addr (io_readAddr[9:0]),	// MemoryMask.scala:42:25
    .R0_en   (io_readEnable),
    .R0_clk  (clock),
    .W0_addr (io_writeAddr[9:0]),	// <stdin>:8:15
    .W0_en   (io_writeMask_3),
    .W0_clk  (clock),
    .W0_data (io_dataIn_3),
    .R0_data (io_dataOut_3)
  );
  mem_0_combMem mem_4_ext (	// MemoryMask.scala:39:24
    .R0_addr (io_readAddr[9:0]),	// MemoryMask.scala:42:25
    .R0_en   (io_readEnable),
    .R0_clk  (clock),
    .W0_addr (io_writeAddr[9:0]),	// <stdin>:8:15
    .W0_en   (io_writeMask_4),
    .W0_clk  (clock),
    .W0_data (io_dataIn_4),
    .R0_data (io_dataOut_4)
  );
  mem_0_combMem mem_5_ext (	// MemoryMask.scala:39:24
    .R0_addr (io_readAddr[9:0]),	// MemoryMask.scala:42:25
    .R0_en   (io_readEnable),
    .R0_clk  (clock),
    .W0_addr (io_writeAddr[9:0]),	// <stdin>:8:15
    .W0_en   (io_writeMask_5),
    .W0_clk  (clock),
    .W0_data (io_dataIn_5),
    .R0_data (io_dataOut_5)
  );
  mem_0_combMem mem_6_ext (	// MemoryMask.scala:39:24
    .R0_addr (io_readAddr[9:0]),	// MemoryMask.scala:42:25
    .R0_en   (io_readEnable),
    .R0_clk  (clock),
    .W0_addr (io_writeAddr[9:0]),	// <stdin>:8:15
    .W0_en   (io_writeMask_6),
    .W0_clk  (clock),
    .W0_data (io_dataIn_6),
    .R0_data (io_dataOut_6)
  );
  mem_0_combMem mem_7_ext (	// MemoryMask.scala:39:24
    .R0_addr (io_readAddr[9:0]),	// MemoryMask.scala:42:25
    .R0_en   (io_readEnable),
    .R0_clk  (clock),
    .W0_addr (io_writeAddr[9:0]),	// <stdin>:8:15
    .W0_en   (io_writeMask_7),
    .W0_clk  (clock),
    .W0_data (io_dataIn_7),
    .R0_data (io_dataOut_7)
  );
endmodule