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@carlosperate
Last active July 19, 2017 13:20
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micro:bit MicroPython register access
FICR_BASE_ADDRESS = 0x10000000
CODE_PAGE_SIZE = FICR_BASE_ADDRESS + 0x010
CODE_SIZE = FICR_BASE_ADDRESS + 0x014
@micropython.asm_thumb
def reg_read(r0):
ldr(r0, [r0, 0])
@micropython.asm_thumb
def reg_write(r0, r1):
str(r1, [r0, 0])
@micropython.asm_thumb
def reg_and(r0, r1):
ldr(r2, [r0, 0])
and_(r2, r1)
str(r2, [r0, 0])
@micropython.asm_thumb
def reg_or(r0, r1):
ldr(r2, [r0, 0])
orr(r2, r1)
str(r2, [r0, 0])
@micropython.asm_thumb
def reg_bit_clear(r0, r1):
ldr(r2, [r0, 0])
bic(r2, r1)
str(r2, [r0, 0])
while True:
print("Should be 1024: {}".format(reg_read(CODE_PAGE_SIZE)))
print("Should be 256: {}".format(reg_read(CODE_SIZE)))
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