public
Last active

  • Download Gist
ghc-prefetch.patch
Diff
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489
From ea6b9bb5a9b4669120310efe6390ab31993df7ca Mon Sep 17 00:00:00 2001
From: Carter Tazio Schonwald <carter.schonwald@gmail.com>
Date: Thu, 19 Sep 2013 15:27:48 -0400
Subject: [PATCH] adding support for prefetch with locality levels 0-3, in the
style of GCC and Clang.
 
Adding support for prefetch with locality levels. Augmented the LLVM prefetch to pass in the locality level parameter.
Added support for prefetch on the native code gens. On Sparc and PPC, generates no operation (not even a nop instruction).
On x86/x86_64, generates one of prefetchNTA, prefetcht2, prefetcht1, prefetcht0.
---
compiler/cmm/CmmMachOp.hs | 8 ++-
compiler/cmm/CmmParse.y | 10 +++-
compiler/cmm/PprC.hs | 4 +-
compiler/codeGen/StgCmmPrim.hs | 53 +++++++++++---------
compiler/llvmGen/LlvmCodeGen/CodeGen.hs | 11 +++--
compiler/nativeGen/PPC/CodeGen.hs | 5 +-
compiler/nativeGen/SPARC/CodeGen.hs | 9 +++-
compiler/nativeGen/X86/CodeGen.hs | 24 ++++++++-
compiler/nativeGen/X86/Instr.hs | 16 +++++-
compiler/nativeGen/X86/Ppr.hs | 12 +++++
compiler/prelude/primops.txt.pp | 87 +++++++++++++++++++++++++++++----
11 files changed, 193 insertions(+), 46 deletions(-)
 
diff --git a/compiler/cmm/CmmMachOp.hs b/compiler/cmm/CmmMachOp.hs
index 8d42bbd..a398336 100644
--- a/compiler/cmm/CmmMachOp.hs
+++ b/compiler/cmm/CmmMachOp.hs
@@ -518,8 +518,14 @@ data CallishMachOp
| MO_Touch -- Keep variables live (when using interior pointers)
-- Prefetch
- | MO_Prefetch_Data -- Prefetch hint. May change program performance but not
+ | MO_Prefetch_Data Int -- Prefetch hint. May change program performance but not
-- program behavior.
+ -- the Int can be 0-3. Needs to be known at compile time
+ -- to interact with code generation correctly.
+ -- TODO: add support for prefetch WRITES,
+ -- currently only exposes prefetch reads, which
+ -- would the majority of use cases in ghc anyways
+
-- Note that these three MachOps all take 1 extra parameter than the
-- standard C lib versions. The extra (last) parameter contains
diff --git a/compiler/cmm/CmmParse.y b/compiler/cmm/CmmParse.y
index 8c36dea..5e436a4 100644
--- a/compiler/cmm/CmmParse.y
+++ b/compiler/cmm/CmmParse.y
@@ -923,8 +923,16 @@ callishMachOps = listToUFM $
( "write_barrier", MO_WriteBarrier ),
( "memcpy", MO_Memcpy ),
( "memset", MO_Memset ),
- ( "memmove", MO_Memmove )
+ ( "memmove", MO_Memmove ),
+
+ ("prefetch0",MO_Prefetch_Data 0),
+ ("prefetch1",MO_Prefetch_Data 1),
+ ("prefetch2",MO_Prefetch_Data 2),
+ ("prefetch3",MO_Prefetch_Data 3)
+
-- ToDo: the rest, maybe
+ -- edit: which rest?
+ -- also: how do we tell CMM Lint how to type check callish macops?
]
parseSafety :: String -> P Safety
diff --git a/compiler/cmm/PprC.hs b/compiler/cmm/PprC.hs
index d45b103..4cac298 100644
--- a/compiler/cmm/PprC.hs
+++ b/compiler/cmm/PprC.hs
@@ -750,7 +750,9 @@ pprCallishMachOp_for_C mop
MO_Add2 {} -> unsupported
MO_U_Mul2 {} -> unsupported
MO_Touch -> unsupported
- MO_Prefetch_Data -> unsupported
+ (MO_Prefetch_Data _ ) -> unsupported
+ --- we could support prefetch via "__builtin_prefetch"
+ --- Not adding it for now
where unsupported = panic ("pprCallishMachOp_for_C: " ++ show mop
++ " not supported!")
diff --git a/compiler/codeGen/StgCmmPrim.hs b/compiler/codeGen/StgCmmPrim.hs
index 8560f7c..c17aa48 100644
--- a/compiler/codeGen/StgCmmPrim.hs
+++ b/compiler/codeGen/StgCmmPrim.hs
@@ -255,15 +255,6 @@ emitPrimOp dflags [res] SizeofMutableByteArrayOp [arg]
emitPrimOp _ res@[] TouchOp args@[_arg]
= do emitPrimCall res MO_Touch args
-emitPrimOp _ res@[] PrefetchByteArrayOp args@[_arg]
- = do emitPrimCall res MO_Prefetch_Data args
-
-emitPrimOp _ res@[] PrefetchMutableByteArrayOp args@[_arg]
- = do emitPrimCall res MO_Prefetch_Data args
-
-emitPrimOp _ res@[] PrefetchAddrOp args@[_arg]
- = do emitPrimCall res MO_Prefetch_Data args
-
-- #define byteArrayContentszh(r,a) r = BYTE_ARR_CTS(a)
emitPrimOp dflags [res] ByteArrayContents_Char [arg]
= emitAssign (CmmLocal res) (cmmOffsetB dflags arg (arrWordsHdrSize dflags))
@@ -630,9 +621,22 @@ emitPrimOp _ [res] Int64X2InsertOp [v,e,i] =
doVecInsertOp Nothing vec2b64 v e i res
-- Prefetch
-emitPrimOp _ res PrefetchByteArrayOp args = doPrefetchByteArrayOp res args
-emitPrimOp _ res PrefetchMutableByteArrayOp args = doPrefetchByteArrayOp res args
-emitPrimOp _ res PrefetchAddrOp args = doPrefetchAddrOp res args
+emitPrimOp _ res PrefetchByteArrayOp3 args = doPrefetchByteArrayOp 3 res args
+emitPrimOp _ res PrefetchMutableByteArrayOp3 args = doPrefetchByteArrayOp 3 res args
+emitPrimOp _ res PrefetchAddrOp3 args = doPrefetchAddrOp 3 res args
+
+emitPrimOp _ res PrefetchByteArrayOp2 args = doPrefetchByteArrayOp 2 res args
+emitPrimOp _ res PrefetchMutableByteArrayOp2 args = doPrefetchByteArrayOp 2 res args
+emitPrimOp _ res PrefetchAddrOp2 args = doPrefetchAddrOp 2 res args
+
+emitPrimOp _ res PrefetchByteArrayOp1 args = doPrefetchByteArrayOp 1 res args
+emitPrimOp _ res PrefetchMutableByteArrayOp1 args = doPrefetchByteArrayOp 1 res args
+emitPrimOp _ res PrefetchAddrOp1 args = doPrefetchAddrOp 1 res args
+
+emitPrimOp _ res PrefetchByteArrayOp0 args = doPrefetchByteArrayOp 0 res args
+emitPrimOp _ res PrefetchMutableByteArrayOp0 args = doPrefetchByteArrayOp 0 res args
+emitPrimOp _ res PrefetchAddrOp0 args = doPrefetchAddrOp 0 res args
+
-- The rest just translate straightforwardly
emitPrimOp dflags [res] op [arg]
@@ -1287,31 +1291,34 @@ doVecInsertOp maybe_pre_write_cast ty src e idx res = do
------------------------------------------------------------------------------
-- Helpers for translating prefetching.
-doPrefetchByteArrayOp :: [LocalReg]
+doPrefetchByteArrayOp :: Int
+ -> [LocalReg]
-> [CmmExpr]
-> FCode ()
-doPrefetchByteArrayOp res [addr,idx]
+doPrefetchByteArrayOp locality res [addr,idx]
= do dflags <- getDynFlags
- mkBasicPrefetch (arrWordsHdrSize dflags) res addr idx
-doPrefetchByteArrayOp _ _
+ mkBasicPrefetch locality (arrWordsHdrSize dflags) res addr idx
+doPrefetchByteArrayOp _ _ _
= panic "StgCmmPrim: doPrefetchByteArrayOp"
-doPrefetchAddrOp :: [LocalReg]
+doPrefetchAddrOp ::Int
+ -> [LocalReg]
-> [CmmExpr]
-> FCode ()
-doPrefetchAddrOp res [addr,idx]
- = mkBasicPrefetch 0 res addr idx
-doPrefetchAddrOp _ _
+doPrefetchAddrOp locality res [addr,idx]
+ = mkBasicPrefetch locality 0 res addr idx
+doPrefetchAddrOp _ _ _
= panic "StgCmmPrim: doPrefetchAddrOp"
-mkBasicPrefetch :: ByteOff -- Initial offset in bytes
+mkBasicPrefetch :: Int -- Locality level 0-3
+ -> ByteOff -- Initial offset in bytes
-> [LocalReg] -- Destination
-> CmmExpr -- Base address
-> CmmExpr -- Index
-> FCode ()
-mkBasicPrefetch off res base idx
+mkBasicPrefetch locality off res base idx
= do dflags <- getDynFlags
- emitPrimCall [] MO_Prefetch_Data [cmmIndexExpr dflags W8 (cmmOffsetB dflags base off) idx]
+ emitPrimCall [] (MO_Prefetch_Data locality) [cmmIndexExpr dflags W8 (cmmOffsetB dflags base off) idx]
case res of
[] -> return ()
[reg] -> emitAssign (CmmLocal reg) base
diff --git a/compiler/llvmGen/LlvmCodeGen/CodeGen.hs b/compiler/llvmGen/LlvmCodeGen/CodeGen.hs
index def9e2b..28cf9a5 100644
--- a/compiler/llvmGen/LlvmCodeGen/CodeGen.hs
+++ b/compiler/llvmGen/LlvmCodeGen/CodeGen.hs
@@ -200,7 +200,8 @@ genCall (PrimTarget (MO_UF_Conv _)) [_] args =
"Can only handle 1, given" ++ show (length args) ++ "."
-- Handle prefetching data
-genCall t@(PrimTarget MO_Prefetch_Data) [] args = do
+genCall t@(PrimTarget (MO_Prefetch_Data localityInt)) [] args
+ | 0 <= localityInt && localityInt <= 3 = do
ver <- getLlvmVer
let argTy | ver <= 29 = [i8Ptr, i32, i32]
| otherwise = [i8Ptr, i32, i32, i32]
@@ -214,12 +215,13 @@ genCall t@(PrimTarget MO_Prefetch_Data) [] args = do
(argVars', stmts3) <- castVars $ zip argVars argTy
trash <- getTrashStmts
- let argSuffix | ver <= 29 = [mkIntLit i32 0, mkIntLit i32 3]
- | otherwise = [mkIntLit i32 0, mkIntLit i32 3, mkIntLit i32 1]
+ let argSuffix | ver <= 29 = [mkIntLit i32 0, mkIntLit i32 localityInt]
+ | otherwise = [mkIntLit i32 0, mkIntLit i32 localityInt, mkIntLit i32 1]
call = Expr $ Call StdCall fptr (argVars' ++ argSuffix) []
stmts = stmts1 `appOL` stmts2 `appOL` stmts3
`appOL` trash `snocOL` call
return (stmts, top1 ++ top2)
+ | otherwise = panic $ "prefetch locality level integer must be between 0 and 3, given: " ++ (show localityInt)
-- Handle PopCnt and BSwap that need to only convert arg and return types
genCall t@(PrimTarget (MO_PopCnt w)) dsts args =
@@ -545,7 +547,8 @@ cmmPrimOpFunctions mop = do
(MO_PopCnt w) -> fsLit $ "llvm.ctpop." ++ showSDoc dflags (ppr $ widthToLlvmInt w)
(MO_BSwap w) -> fsLit $ "llvm.bswap." ++ showSDoc dflags (ppr $ widthToLlvmInt w)
- MO_Prefetch_Data -> fsLit "llvm.prefetch"
+ (MO_Prefetch_Data _ )-> fsLit "llvm.prefetch"
+
MO_S_QuotRem {} -> unsupported
MO_U_QuotRem {} -> unsupported
diff --git a/compiler/nativeGen/PPC/CodeGen.hs b/compiler/nativeGen/PPC/CodeGen.hs
index 65533d8..5b35956 100644
--- a/compiler/nativeGen/PPC/CodeGen.hs
+++ b/compiler/nativeGen/PPC/CodeGen.hs
@@ -911,6 +911,9 @@ genCCall' _ _ (PrimTarget MO_WriteBarrier) _ _
genCCall' _ _ (PrimTarget MO_Touch) _ _
= return $ nilOL
+
+genCCall' _ _ (PrimTarget (MO_Prefetch_Data _)) _ _
+ = return $ nilOL
genCCall' dflags gcp target dest_regs args0
= ASSERT(not $ any (`elem` [II16]) $ map cmmTypeSize argReps)
@@ -1165,7 +1168,7 @@ genCCall' dflags gcp target dest_regs args0
MO_U_Mul2 {} -> unsupported
MO_WriteBarrier -> unsupported
MO_Touch -> unsupported
- MO_Prefetch_Data -> unsupported
+ (MO_Prefetch_Data _ ) -> unsupported
unsupported = panic ("outOfLineCmmOp: " ++ show mop
++ " not supported")
diff --git a/compiler/nativeGen/SPARC/CodeGen.hs b/compiler/nativeGen/SPARC/CodeGen.hs
index 5d2b9a9..ea88053 100644
--- a/compiler/nativeGen/SPARC/CodeGen.hs
+++ b/compiler/nativeGen/SPARC/CodeGen.hs
@@ -392,7 +392,12 @@ genCCall
-- In the SPARC case we don't need a barrier.
--
genCCall (PrimTarget MO_WriteBarrier) _ _
- = do return nilOL
+ = return $ nilOL
+
+-- For now we have prefetc
+--
+genCCall (PrimTarget (MO_Prefetch_Data _)) _ _
+ = return $ nilOL
genCCall target dest_regs args0
= do
@@ -657,7 +662,7 @@ outOfLineMachOp_table mop
MO_U_Mul2 {} -> unsupported
MO_WriteBarrier -> unsupported
MO_Touch -> unsupported
- MO_Prefetch_Data -> unsupported
+ (MO_Prefetch_Data _) -> unsupported
where unsupported = panic ("outOfLineCmmOp: " ++ show mop
++ " not supported here")
diff --git a/compiler/nativeGen/X86/CodeGen.hs b/compiler/nativeGen/X86/CodeGen.hs
index f6143d3..5617f56 100644
--- a/compiler/nativeGen/X86/CodeGen.hs
+++ b/compiler/nativeGen/X86/CodeGen.hs
@@ -1656,7 +1656,27 @@ genCCall _ (PrimTarget MO_WriteBarrier) _ _ = return nilOL
genCCall _ (PrimTarget MO_Touch) _ _ = return nilOL
-genCCall _ (PrimTarget MO_Prefetch_Data) _ _ = return nilOL
+genCCall is32bit (PrimTarget (MO_Prefetch_Data n )) _ [src] =
+ case n of
+ 0 -> genPrefetch src $ PREFETCH NTA size
+ 1 -> genPrefetch src $ PREFETCH Lvl2 size
+ 2 -> genPrefetch src $ PREFETCH Lvl1 size
+ 3 -> genPrefetch src $ PREFETCH Lvl0 size
+ l -> panic $ "unexpected prefetch level in genCCall MO_Prefetch_Data: " ++ (show l)
+ -- the c / llvm prefetch convention is 0, 1, 2, and 3
+ -- the x86 corresponding names are : NTA, 2 , 1, and 0
+ where
+ size = archWordSize is32bit
+ -- need to know what register width for pointers!
+ genPrefetch inRegSrc prefetchCTor =
+ do
+ code_src <- getAnyReg inRegSrc
+ src_r <- getNewRegNat size
+ return $ code_src src_r `appOL`
+ (unitOL (prefetchCTor (OpAddr
+ ((AddrBaseIndex (EABaseReg src_r ) EAIndexNone (ImmInt 0)))) ))
+ -- prefetch always takes an address
+
genCCall is32Bit (PrimTarget (MO_BSwap width)) [dst] [src] = do
dflags <- getDynFlags
@@ -2359,7 +2379,7 @@ outOfLineCmmOp mop res args
MO_U_Mul2 {} -> unsupported
MO_WriteBarrier -> unsupported
MO_Touch -> unsupported
- MO_Prefetch_Data -> unsupported
+ (MO_Prefetch_Data _ ) -> unsupported
unsupported = panic ("outOfLineCmmOp: " ++ show mop
++ " not supported here")
diff --git a/compiler/nativeGen/X86/Instr.hs b/compiler/nativeGen/X86/Instr.hs
index 266a4ea..1ac3689 100644
--- a/compiler/nativeGen/X86/Instr.hs
+++ b/compiler/nativeGen/X86/Instr.hs
@@ -9,7 +9,7 @@
#include "HsVersions.h"
#include "nativeGen/NCG.h"
-module X86.Instr (Instr(..), Operand(..), JumpDest,
+module X86.Instr (Instr(..), Operand(..), PrefetchVariant(..), JumpDest,
getJumpDestBlockId, canShortcut, shortcutStatics,
shortcutJump, i386_insert_ffrees, allocMoreStack,
maxSpillSlots, archWordSize)
@@ -319,7 +319,14 @@ data Instr
-- 1: popl %reg
-- SSE4.2
- | POPCNT Size Operand Reg -- src, dst
+ | POPCNT Size Operand Reg -- src, dst
+
+ -- prefetch
+ | PREFETCH PrefetchVariant Size Operand -- prefetch Variant, addr size, address to prefetch
+ -- variant can be NTA, Lvl0, Lvl1, or Lvl2
+
+data PrefetchVariant = NTA | Lvl0 | Lvl1 | Lvl2
+
data Operand
= OpReg Reg -- register
@@ -417,6 +424,9 @@ x86_regUsageOfInstr platform instr
POPCNT _ src dst -> mkRU (use_R src []) [dst]
+ -- note: might be a better way to do this
+ PREFETCH _ _ src -> mkRU (use_R src []) []
+
_other -> panic "regUsage: unrecognised instr"
where
@@ -556,6 +566,8 @@ x86_patchRegsOfInstr instr env
CLTD _ -> instr
POPCNT sz src dst -> POPCNT sz (patchOp src) (env dst)
+
+ PREFETCH lvl size src -> PREFETCH lvl size (patchOp src)
_other -> panic "patchRegs: unrecognised instr"
diff --git a/compiler/nativeGen/X86/Ppr.hs b/compiler/nativeGen/X86/Ppr.hs
index 7f9c690..2077ed1 100644
--- a/compiler/nativeGen/X86/Ppr.hs
+++ b/compiler/nativeGen/X86/Ppr.hs
@@ -577,6 +577,11 @@ pprInstr (XOR size src dst) = pprSizeOpOp (sLit "xor") size src dst
pprInstr (POPCNT size src dst) = pprOpOp (sLit "popcnt") size src (OpReg dst)
+pprInstr (PREFETCH NTA size src ) = pprSizeOp_ (sLit "prefetchnta") size src
+pprInstr (PREFETCH Lvl0 size src) = pprSizeOp_ (sLit "prefetcht0") size src
+pprInstr (PREFETCH Lvl1 size src) = pprSizeOp_ (sLit "prefetcht1") size src
+pprInstr (PREFETCH Lvl2 size src) = pprSizeOp_ (sLit "prefetcht2") size src
+
pprInstr (NOT size op) = pprSizeOp (sLit "not") size op
pprInstr (BSWAP size op) = pprSizeOp (sLit "bswap") size (OpReg op)
pprInstr (NEGI size op) = pprSizeOp (sLit "neg") size op
@@ -1025,6 +1030,13 @@ pprSizeImmOp name size imm op1
]
+pprSizeOp_ :: LitString -> Size -> Operand -> SDoc
+pprSizeOp_ name size op1
+ = hcat [
+ pprMnemonic_ name ,
+ pprOperand size op1
+ ]
+
pprSizeOp :: LitString -> Size -> Operand -> SDoc
pprSizeOp name size op1
= hcat [
diff --git a/compiler/prelude/primops.txt.pp b/compiler/prelude/primops.txt.pp
index cfd6afa..902630f 100644
--- a/compiler/prelude/primops.txt.pp
+++ b/compiler/prelude/primops.txt.pp
@@ -2848,22 +2848,91 @@ primop WriteOffAddrOp_Int64AsInt64X2 "writeInt64OffAddrAsInt64X2#" GenPrimOp
llvm_only = True
------------------------------------------------------------------------
-section "Prefetch"
- {Prefetch operations}
+
+section "Prefetch"
+ {Prefetch operations: Note how every prefetch operation has a name
+ with the pattern prefetch*N#, where N is either 0,1,2, or 3.
+
+ This suffix number, N, is the "locality level" of the prefetch, following the
+ convention in GCC and other compilers.
+ Higher locality numbers correspond to the memory being loaded in more
+ levels of the cpu cache, and being retained after initial use.
+
+ On the LLVM backend, prefetch*N# uses the LLVM prefetch intrinsic
+ with locality level N. The code generated by LLVM is target architecture
+ dependent, but should agree with the GHC NCG on x86 systems.
+
+ On the Sparc and PPC native backends, prefetch*N is a No-Op.
+
+ On the x86 NCG, N=0 will generate prefetchNTA,
+ N=1 generates prefetcht2, N=2 generates prefetcht1, and
+ N=3 generates prefetcht0.
+
+ For streaming workloads, the prefetch*0 operations are recommended.
+ For workloads which do many reads or writes to a memory location in a short period of time,
+ prefetch*3 operations are recommended.
+ }
------------------------------------------------------------------------
-primop PrefetchByteArrayOp "prefetchByteArray#" GenPrimOp
+
+--- the Int# argument for prefetch is the byte offset on the byteArray or Addr#
+
+---
+primop PrefetchByteArrayOp3 "prefetchByteArray3#" GenPrimOp
ByteArray# -> Int# -> ByteArray#
- with llvm_only = True
+ with can_fail = True
-primop PrefetchMutableByteArrayOp "prefetchMutableByteArray#" GenPrimOp
+primop PrefetchMutableByteArrayOp3 "prefetchMutableByteArray3#" GenPrimOp
MutableByteArray# s -> Int# -> State# s -> State# s
- with has_side_effects = True
- llvm_only = True
+ with can_fail = True
+
+primop PrefetchAddrOp3 "prefetchAddr3#" GenPrimOp
+ Addr# -> Int# -> Addr#
+ with can_fail = True
-primop PrefetchAddrOp "prefetchAddr#" GenPrimOp
+----
+
+primop PrefetchByteArrayOp2 "prefetchByteArray2#" GenPrimOp
+ ByteArray# -> Int# -> ByteArray#
+ with can_fail = True
+
+primop PrefetchMutableByteArrayOp2 "prefetchMutableByteArray2#" GenPrimOp
+ MutableByteArray# s -> Int# -> State# s -> State# s
+ with can_fail = True
+
+primop PrefetchAddrOp2 "prefetchAddr2#" GenPrimOp
Addr# -> Int# -> Addr#
- with llvm_only = True
+ with can_fail = True
+
+----
+
+primop PrefetchByteArrayOp1 "prefetchByteArray1#" GenPrimOp
+ ByteArray# -> Int# -> ByteArray#
+ with can_fail = True
+
+primop PrefetchMutableByteArrayOp1 "prefetchMutableByteArray1#" GenPrimOp
+ MutableByteArray# s -> Int# -> State# s -> State# s
+ with can_fail = True
+
+primop PrefetchAddrOp1 "prefetchAddr1#" GenPrimOp
+ Addr# -> Int# -> Addr#
+ with can_fail = True
+
+----
+
+primop PrefetchByteArrayOp0 "prefetchByteArray0#" GenPrimOp
+ ByteArray# -> Int# -> ByteArray#
+ with can_fail = True
+
+primop PrefetchMutableByteArrayOp0 "prefetchMutableByteArray0#" GenPrimOp
+ MutableByteArray# s -> Int# -> State# s -> State# s
+ with can_fail = True
+
+primop PrefetchAddrOp0 "prefetchAddr0#" GenPrimOp
+ Addr# -> Int# -> Addr#
+ with can_fail = True
+
+
------------------------------------------------------------------------
--- ---
--
1.8.2.3
testsuite-prefetch.patch
Diff
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
From 9fd699ea3f9763753f061faefdf154b41f4106db Mon Sep 17 00:00:00 2001
From: Carter Tazio Schonwald <carter.schonwald@gmail.com>
Date: Fri, 20 Sep 2013 16:40:10 -0400
Subject: [PATCH] updated test suite patch for prefetch
 
---
tests/codeGen/should_run/T8256.hs | 48 +++++++++++++++++++++++++++++++++++
tests/codeGen/should_run/T8256.stdout | 1 +
tests/codeGen/should_run/all.T | 2 ++
3 files changed, 51 insertions(+)
create mode 100644 tests/codeGen/should_run/T8256.hs
create mode 100644 tests/codeGen/should_run/T8256.stdout
 
diff --git a/tests/codeGen/should_run/T8256.hs b/tests/codeGen/should_run/T8256.hs
new file mode 100644
index 0000000..7f8314c
--- /dev/null
+++ b/tests/codeGen/should_run/T8256.hs
@@ -0,0 +1,48 @@
+{-# LANGUAGE MagicHash, UnboxedTuples #-}
+
+
+
+import GHC.Prim
+
+import Data.Vector.Storable.Mutable
+import Foreign.Ptr
+import GHC.ST
+import Data.Primitive.ByteArray
+import Control.Monad.Primitive
+
+
+
+sameByteArray :: Control.Monad.Primitive.PrimMonad m => ByteArray -> ByteArray -> m Bool
+sameByteArray ar1 ar2 =
+ do v1 <- unsafeThawByteArray ar1
+ v2 <- unsafeThawByteArray ar2
+ return $ sameMutableByteArray v1 v2
+
+pf0 (ByteArray by) = ByteArray ( prefetchByteArray0# by 1#)
+
+pf1 (ByteArray by) = ByteArray (prefetchByteArray1# by 1#)
+
+pf2 (ByteArray by) = ByteArray ( prefetchByteArray2# by 1#)
+
+pf3 (ByteArray by) = ByteArray ( prefetchByteArray3# by 1#)
+
+
+monoSame v f = sameByteArray v (f v)
+
+
+
+
+main :: IO ()
+main = do
+ mv1 <- newByteArray 17
+ v1 <- unsafeFreezeByteArray mv1
+ return ()
+ t0<- monoSame v1 pf0
+ t1 <- monoSame v1 pf1
+ t2 <- monoSame v1 pf2
+ t3 <- monoSame v1 pf3
+ if t0 && t1 && t2 && t3 then putStrLn "success" else error "bad prefetch operation! please report"
+
+
+
+
diff --git a/tests/codeGen/should_run/T8256.stdout b/tests/codeGen/should_run/T8256.stdout
new file mode 100644
index 0000000..2e9ba47
--- /dev/null
+++ b/tests/codeGen/should_run/T8256.stdout
@@ -0,0 +1 @@
+success
diff --git a/tests/codeGen/should_run/all.T b/tests/codeGen/should_run/all.T
index b51cc30..c5b14d9 100644
--- a/tests/codeGen/should_run/all.T
+++ b/tests/codeGen/should_run/all.T
@@ -114,3 +114,5 @@ test('T7361', normal, compile_and_run, [''])
test('T7600', normal, compile_and_run, [''])
test('T8103', only_ways(['normal']), compile_and_run, [''])
test('T7953', normal, compile_and_run, [''])
+
+test('T8256',normal, compile_and_run, [''])
--
1.8.2.3

Please sign in to comment on this gist.

Something went wrong with that request. Please try again.