Used online repositories for Fedora/RHEL/CentOS linux:
-
The VLSI repository homepage: https://copr.fedorainfracloud.org/coprs/rezso/VLSI
-
The HDL repository homepage: https://copr.fedorainfracloud.org/coprs/rezso/HDL
-
Docker variants of this: https://github.com/cbalint13/copr-packages/tree/main/docker-examples
$ sudo dnf copr enable rezso/HDL
$ sudo dnf copr enable rezso/VLSI
$ sudo dnf install openlane
Dependencies resolved.
===============================================================================================================================================================================================================================================
Package Architecture Version Repository Size
===============================================================================================================================================================================================================================================
Installing:
openlane noarch 2023.03.30-20230329.0.gited194238.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI 7.7 M
Installing dependencies:
abc x86_64 1.02-20230331.0.git36a83acf.fc39 copr:copr.fedorainfracloud.org:rezso:HDL 18 k
cu-gr x86_64 1.1-20210112.3.git1632b4b4.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI 2.1 M
cudd x86_64 3.0.0-2 copr:copr.fedorainfracloud.org:rezso:VLSI 653 k
cvc x86_64 1.1.3-20221004.2.gitdf85a637.fc38 copr:copr.fedorainfracloud.org:rezso:VLSI 504 k
def x86_64 5.8-20201214.1.git0b46cdb8.fc37 copr:copr.fedorainfracloud.org:rezso:VLSI 2.9 M
dr-cu x86_64 4.1.1-20210427.3.git3d81988d.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI 680 k
efabless-open-pdks noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI 33 M
efabless-open-pdks-gf180mcu_fd_sc_mcu7t5v0 noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI 30 M
efabless-open-pdks-gf180mcu_fd_sc_mcu9t5v0 noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI 30 M
efabless-open-pdks-sky130_fd_sc_hd noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI 47 M
efabless-open-pdks-sky130_ml_xx_hd noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI 39 k
efabless-open-pdks-sky130_sram_macros noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI 8.1 M
klayout x86_64 0.28.6-20230320.0.gitc6bfb03a.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI 37 M
lef x86_64 5.8-20201214.1.git741f6ebc.fc37 copr:copr.fedorainfracloud.org:rezso:VLSI 976 k
magic x86_64 8.3.388-1.fc39 koji 1.2 M
netgen x86_64 1.5.251-20230329.0.git66317c98.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI 254 k
openroad x86_64 2.0-20230331.0.gitcd03c5cf.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI 10 M
opensta x86_64 2.2.0-20230329.0.git882681a6.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI 5.5 M
opentimer x86_64 2.1.0-20221116.0.gita57d03b3.fc38 copr:copr.fedorainfracloud.org:rezso:VLSI 16 M
or-tools x86_64 9.6-20230310.0.git5425dedc.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI 8.2 M
padring x86_64 0-20210731.1.gitb2a64abc.fc37 copr:copr.fedorainfracloud.org:rezso:VLSI 215 k
python3-kivy x86_64 2.1.0-1.fc37 copr:copr.fedorainfracloud.org:rezso:VLSI 4.1 M
python3-kivy-garden x86_64 0.1.5-1.fc37 copr:copr.fedorainfracloud.org:rezso:VLSI 12 k
qflow x86_64 1.4.100-20221129.0.gitb0f76bf4.fc38 copr:copr.fedorainfracloud.org:rezso:VLSI 678 k
scip x86_64 802-20221121.0.git1929dc28.fc38 copr:copr.fedorainfracloud.org:rezso:VLSI 5.2 M
spdlog x86_64 1.11.0-5.1.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI 161 k
yosys x86_64 0.27-20230324.0.git53c0a6b7.fc39 copr:copr.fedorainfracloud.org:rezso:HDL 3.5 M
Transaction Summary
===============================================================================================================================================================================================================================================
Install 28 Packages
Total download size: 257 M
Installed size: 2.9 G
Is this ok [y/N]: y
$ sudo dnf update
$ sudo dnf install openlane-designs
$ rpm -ql openlane-designs | grep spm
/usr/share/openlane/designs/spm
/usr/share/openlane/designs/spm/config.json
/usr/share/openlane/designs/spm/pin_order.cfg
/usr/share/openlane/designs/spm/src
/usr/share/openlane/designs/spm/src/spm.sdc
/usr/share/openlane/designs/spm/src/spm.v
$ cp -r /usr/share/openlane/designs/spm my-spm
$ openlane-flow -design my-spm
OpenLane wrapper via [flow.tcl]
+ export PDK=sky130A
+ PDK=sky130A
+ export PDK_ROOT=/usr/share/pdk
+ PDK_ROOT=/usr/share/pdk
+ export STD_CELL_LIBRARY=sky130_fd_sc_hd
+ STD_CELL_LIBRARY=sky130_fd_sc_hd
+ export STD_CELL_LIBRARY_OPT=sky130_fd_sc_hd
+ STD_CELL_LIBRARY_OPT=sky130_fd_sc_hd
+ export OPENLANE_ROOT=/usr/share/openlane
+ OPENLANE_ROOT=/usr/share/openlane
+ trap 'tput init' err exit
+ unset module
+ unset _module_raw
+ /usr/share/openlane/flow.tcl -design my-spm
OpenLane 2023.03.30-20230329.0.gited194238.fc39
All rights reserved. (c) 2020-2022 Efabless Corporation and contributors.
Available under the Apache License, version 2.0. See the LICENSE file for more details.
[INFO]: Using configuration in 'my-spm/config.json'...
[INFO]: PDK Root: /usr/share/pdk
[INFO]: Process Design Kit: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Optimization Standard Cell Library: sky130_fd_sc_hd
[INFO]: Run Directory: /home/cbalint/rpmbuild/SPECS/MAIN/SANDBOX/my-spm/runs/RUN_2023.04.01_19.45.05
[INFO]: Preparing LEF files for the nom corner...
[INFO]: Preparing LEF files for the min corner...
[INFO]: Preparing LEF files for the max corner...
[STEP 1]
[INFO]: Running Synthesis (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/synthesis/1-synthesis.log)...
[STEP 2]
[INFO]: Running Single-Corner Static Timing Analysis (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/synthesis/2-sta.log)...
[STEP 3]
[INFO]: Running Initial Floorplanning (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/floorplan/3-initial_fp.log)...
[WARNING]: Current core area is too small for the power grid settings chosen. The power grid will be scaled down.
[INFO]: Floorplanned with width 90.62 and height 89.76.
[STEP 4]
[INFO]: Running IO Placement (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/floorplan/4-place_io.log)...
[STEP 5]
[INFO]: Running Tap/Decap Insertion (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/floorplan/5-tap.log)...
[INFO]: Power planning with power {VPWR} and ground {VGND}...
[STEP 6]
[INFO]: Generating PDN (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/floorplan/6-pdn.log)...
[STEP 7]
[INFO]: Running Global Placement (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/placement/7-global.log)...
[STEP 8]
[INFO]: Running Placement Resizer Design Optimizations (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/placement/8-resizer.log)...
[STEP 9]
[INFO]: Running Detailed Placement (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/placement/9-detailed.log)...
[STEP 10]
[INFO]: Running Clock Tree Synthesis (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/cts/10-cts.log)...
[STEP 11]
[INFO]: Running Placement Resizer Timing Optimizations (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/cts/11-resizer.log)...
[STEP 12]
[INFO]: Running Global Routing Resizer Design Optimizations (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/routing/12-resizer_design.log)...
[STEP 13]
[INFO]: Running Global Routing Resizer Timing Optimizations (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/routing/13-resizer_timing.log)...
[STEP 14]
[INFO]: Running Global Routing (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/routing/14-global.log)...
[INFO]: Starting OpenROAD Antenna Repair Iterations...
[STEP 15]
[INFO]: Writing Verilog (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/routing/14-global_write_netlist.log)...
[STEP 16]
[INFO]: Running Fill Insertion (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/routing/16-fill.log)...
[STEP 17]
[INFO]: Running Detailed Routing (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/routing/17-detailed.log)...
[INFO]: No DRC violations after detailed routing.
[STEP 18]
[INFO]: Checking Wire Lengths (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/routing/18-wire_lengths.log)...
[STEP 19]
[INFO]: Running SPEF Extraction at the min process corner (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/19-parasitics_extraction.min.log)...
[STEP 20]
[INFO]: Running Multi-Corner Static Timing Analysis at the min process corner (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/20-rcx_mcsta.min.log)...
[STEP 21]
[INFO]: Running SPEF Extraction at the max process corner (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/21-parasitics_extraction.max.log)...
[STEP 22]
[INFO]: Running Multi-Corner Static Timing Analysis at the max process corner (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/22-rcx_mcsta.max.log)...
[STEP 23]
[INFO]: Running SPEF Extraction at the nom process corner (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/23-parasitics_extraction.nom.log)...
[STEP 24]
[INFO]: Running Multi-Corner Static Timing Analysis at the nom process corner (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/24-rcx_mcsta.nom.log)...
[STEP 25]
[INFO]: Running Single-Corner Static Timing Analysis at the nom process corner (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/25-rcx_sta.log)...
[STEP 26]
[INFO]: Creating IR Drop Report (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/26-irdrop.log)...
[STEP 27]
[INFO]: Running Magic to generate various views...
[INFO]: Streaming out GDSII with Magic (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/27-gdsii.log)...
[INFO]: Generating MAGLEF views...
[STEP 28]
[INFO]: Streaming out GDSII with KLayout (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/28-gdsii-klayout.log)...
[STEP 29]
[INFO]: Running XOR on the layouts using KLayout (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/29-xor.log)...
[INFO]: No XOR differences between KLayout and Magic gds.
[STEP 30]
[INFO]: Running Magic Spice Export from LEF (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/30-spice.log)...
[STEP 31]
[INFO]: Writing Powered Verilog (logs: my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/31-write_powered_def.log, my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/31-write_powered_verilog.log)...
[STEP 32]
[INFO]: Writing Verilog (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/31-write_powered_verilog.log)...
[STEP 33]
[INFO]: Running LVS (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/33-lvs.lef.log)...
[STEP 34]
[INFO]: Running Magic DRC (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/34-drc.log)...
[INFO]: Converting Magic DRC database to various tool-readable formats...
[INFO]: No DRC violations after GDS streaming out.
[STEP 35]
[INFO]: Running OpenROAD Antenna Rule Checker (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/35-antenna.log)...
[STEP 36]
[INFO]: Running Circuit Validity Checker ERC (log: my-spm/runs/RUN_2023.04.01_19.45.05/logs/signoff/36-erc_screen.log)...
[INFO]: Saving current set of views in 'my-spm/runs/RUN_2023.04.01_19.45.05/results/final'...
[INFO]: Saving runtime environment...
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at 'my-spm/runs/RUN_2023.04.01_19.45.05/reports/manufacturability.rpt'.
[INFO]: Created metrics report at 'my-spm/runs/RUN_2023.04.01_19.45.05/reports/metrics.csv'.
[INFO]: There are no max slew, max fanout or max capacitance violations in the design at the typical corner.
[INFO]: There are no hold violations in the design at the typical corner.
[INFO]: There are no setup violations in the design at the typical corner.
[SUCCESS]: Flow complete.
[INFO]: Note that the following warnings have been generated:
[WARNING]: Current core area is too small for the power grid settings chosen. The power grid will be scaled down.
+ tput init
$ ls -l my-spm/runs/
total 0
drwxr-xr-x 1 cbalint cbalint 208 Apr 1 19:46 RUN_2023.04.01_19.45.05
$ klayout -s my-spm/runs/RUN_2023.04.01_19.45.05/results/final/gds/spm.gds -l /usr/share/pdk/sky130A/libs.tech/klayout/tech/sky130A.lyp
$ sudo dnf list all | grep efabless
efabless-open-pdks.noarch 1.0.403-20230319.0.git12df12e2.fc39 @copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-gf180mcu_fd_sc_mcu7t5v0.noarch 1.0.403-20230319.0.git12df12e2.fc39 @copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-gf180mcu_fd_sc_mcu9t5v0.noarch 1.0.403-20230319.0.git12df12e2.fc39 @copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_fd_sc_hd.noarch 1.0.403-20230319.0.git12df12e2.fc39 @copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_ml_xx_hd.noarch 1.0.403-20230319.0.git12df12e2.fc39 @copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_sram_macros.noarch 1.0.403-20230319.0.git12df12e2.fc39 @copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks.src 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-gf180mcu_fd_io.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-gf180mcu_fd_ip_sram.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-gf180mcu_osu_sc_12T.noarch 1.0.372-20221211.0.git8f01d8f4.fc38 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-gf180mcu_osu_sc_9T.noarch 1.0.372-20221211.0.git8f01d8f4.fc38 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-gf180mcu_osu_sc_gp12t3v3.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-gf180mcu_osu_sc_gp9t3v3.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_fd_io.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_fd_pr.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_fd_sc_hdll.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_fd_sc_hs.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_fd_sc_hvl.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_fd_sc_lp.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_fd_sc_ls.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_fd_sc_ms.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_osu_sc_12t_hs.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_osu_sc_12t_ls.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_osu_sc_12t_ms.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_osu_sc_15t_hs.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_osu_sc_15t_ls.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_osu_sc_15t_ms.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_osu_sc_18t_hs.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_osu_sc_18t_ls.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI
efabless-open-pdks-sky130_osu_sc_18t_ms.noarch 1.0.403-20230319.0.git12df12e2.fc39 copr:copr.fedorainfracloud.org:rezso:VLSI