cfelton

    def WriteVidPid(self, vid, pid, addr=0xA0):

        try:
            vid_lo = vid & 0xFF
            vid_hi = (vid >> 8) & 0xFF
            pid_lo = pid & 0xFF
            pid_hi = (pid >> 8) & 0xFF
            
            ControlBuffer = c_ubyte * 16
            d = ControlBuffer()

cfelton

def m_flatten(matrix, flat):
    _flat = ConcatSignal(*[col(4,0) for row in matrix for col in row])
    @always_comb
    def rtl():
        flat.next = _flat
    return rtl


def test_flatten():
    matrix = [[Signal(intbv(0)[8:]) for col in range(5)] for row in range(8)]    

cfelton

from __future__ import print_function

from random import randint
from myhdl import *

def m_top_const(clock, reset, x, y, a, b, N=10):
    # a tuple of constant ints
    coef = tuple([(randint(-19,23), randint(0,127),) 
                 for _ in range(N)])

cfelton

• Research (investigate) and understand current mem conversion (?? days), will document on daily blogs.
• Research (investigate) and understand Verilog and VHDL Ndarray support (?? days). Is the NDarray support, will document in daily blogs.
• Write a MEP for the 2D/NDarray conversion support (?? days).
• Get feedback update MEP (??days).
• Investigate the converion/general tests structure (?? days), will provide documentation on daily blogs.
• Write tests for the converstion support (?? days), will document provide status on blogs and have a complete set of tests.
• Start implementing the 2D/NDarray conversion support (?? days), blog status
• Prepare pull-request for this new and awesome feature (?? days), blog status
• Create documentation: release (what's new) and manual (?? days)
• Summer over, proad of the work accomplised :)

cfelton

def m_int_case(clock, reset, x, y):

    @always_seq(clock.posedge, reset=reset)
    def rtl():
        z = (x >> 16) & 0x3
        if z == 0:
            y.next = y - 0xDECAFBAD
        elif z == 1:
            y.next = x + 0xC0FFEE
        elif z == 2:

cfelton

from random import randint
from myhdl import *
 
def switchchannels(mem2d, q, clk):
 
    @always(clk.posedge)
    def switch():
        #print('switch')
        #print(mem2d)
        x = mem2d[0]

cfelton

import myhdl
print(myhdl.__version__)
from myhdl import *

def add_example(CLK, IN_1, IN_2, SUM_OUT):
 
     SUM_OUT.driven = 'reg'
     IN_1.read = True
     IN_2.read = True
 

cfelton

from random import randint
from myhdl import *

def m_2dlos(clock, reset, x, y, Nrows=4, Mcols=8):

    mem2d = [[Signal(intbv(randint(1, 7689), min=0, max=7690)) 
              for col in range(Mcols)] 
             for row in range(Nrows)]
    rcnt = Signal(modbv(0, min=0, max=4))
    ccnt = Signal(modbv(0, min=0, max=8))

cfelton

from myhdl import *

class Intf(object):
    def __init__(self):
        self.a = Signal(intbv(0)[8:])
        self.b = Signal(intbv(0)[8:])
        self._x = Signal(intbv(0)[8:])
    
    @property

cfelton

from myhdl import *

def largeconcat(clock, reset, addr, oldest_addr, newest_addr):
    addr_array = Signal(intbv(0)[459:0])
    wrapaddr = modbv(0)[23:0]
    @always_seq(clock.posedge, reset=reset)
    def rtl():
        wrapaddr[:] = addr-1
        addr_array.next = concat(addr_array[436:0], wrapaddr)