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# PT[200000000:23d29c044] -> HW:HW | |
# PT[23d29c044:23d29c048] -> RESERVED PMGR HACK | |
# PT[23d29c048:23d29c05c] -> HW:HW | |
# PT[23d29c05c:23d29c060] -> RESERVED PMGR HACK | |
# PT[23d29c060:28e0801d8] -> HW:HW | |
# PT[28e0801d8:28e0801dc] -> RESERVED PMGR HACK | |
# PT[28e0801dc:28e0801f0] -> HW:HW | |
# PT[28e0801f0:28e0801f4] -> RESERVED PMGR HACK | |
# PT[28e0801f4:28e080200] -> HW:HW | |
# PT[28e080200:28e080204] -> RESERVED PMGR HACK | |
# PT[28e080204:28e080218] -> HW:HW | |
# PT[28e080218:28e08021c] -> RESERVED PMGR HACK | |
# PT[28e08021c:28e080238] -> HW:HW | |
# PT[28e080238:28e08023c] -> RESERVED PMGR HACK | |
# PT[28e08023c:28e0d4000] -> HW:HW | |
# PT[28e0d4000:28e0d4020] -> RESERVED CPU_START | |
# PT[28e0d4020:28e580148] -> HW:HW | |
# PT[28e580148:28e58014c] -> RESERVED PMGR HACK | |
# PT[28e58014c:28e580150] -> HW:HW | |
# PT[28e580150:28e580154] -> RESERVED PMGR HACK | |
# PT[28e580154:28e580160] -> HW:HW | |
# PT[28e580160:28e580164] -> RESERVED PMGR HACK | |
# PT[28e580164:28e580180] -> HW:HW | |
# PT[28e580180:28e580184] -> RESERVED PMGR HACK | |
# PT[28e580184:28e580230] -> HW:HW | |
# PT[28e580230:28e580234] -> RESERVED PMGR HACK | |
# PT[28e580234:28e580240] -> HW:HW | |
# PT[28e580240:28e580244] -> RESERVED PMGR HACK | |
# PT[28e580244:292280088] -> HW:HW | |
# PT[292280088:29228008c] -> RESERVED PMGR HACK | |
# PT[29228008c:2922800d0] -> HW:HW | |
# PT[2922800d0:2922800d4] -> RESERVED PMGR HACK | |
# PT[2922800d4:39b200000] -> HW:HW | |
# PT[39b200000:39b204000] -> RESERVED VUART | |
# PT[39b204000:b0304c000] -> HW:HW | |
# PT[b0304c000:b03050000] -> ASYNC.RW DisplayCrossbarTracer@/arm-io/atc1-dpxbar | |
# PT[b03050000:f0304c000] -> HW:HW | |
# PT[f0304c000:f03050000] -> ASYNC.RW DisplayCrossbarTracer@/arm-io/atc2-dpxbar | |
# PT[f03050000:130304c000] -> HW:HW | |
# PT[130304c000:1303050000] -> ASYNC.RW DisplayCrossbarTracer@/arm-io/atc3-dpxbar | |
# PT[1303050000:1680000000] -> HW:HW | |
# PT[10000000000:10001e0c000] -> HW:RAM-LOW | |
# PT[100161a0000:103dba44000] -> HW:RAM-HIGH | |
# PT[103dba44000:103dd814000] -> *UNMAPPED* | |
# PT[103dd814000:103e6e5c000] -> HW:RAM-HIGH | |
# PT[103e6e5c000:103ffe5c000] -> *UNMAPPED* | |
# PT[103ffe5c000:10400000000] -> HW:RAM-HIGH | |
# [cpu0] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) | |
# [cpu0] Shadow: mrs x12, MDSCR_EL1 = 0 | |
# [cpu0] Shadow: msr MDSCR_EL1, x12 = 1000 | |
# [cpu0] Pass: mrs x13, HID5_EL1 = 2082df50f700df12 (HID5_EL1) | |
# [cpu0] Pass: msr HID5_EL1, x13 = 2082df50f700df12 (OK) (HID5_EL1) | |
# [cpu0] Pass: mrs x13, EHID10_EL1 = 3000528002788 (EHID10_EL1) | |
# [cpu0] Pass: msr EHID10_EL1, x13 = 3000528002788 (OK) (EHID10_EL1) | |
# [cpu0] Pass: mrs x13, EHID10_EL1 = 3000528002788 (EHID10_EL1) | |
# [cpu0] Pass: msr EHID10_EL1, x13 = 3000528002788 (OK) (EHID10_EL1) | |
# [cpu0] Pass: mrs x13, EHID20_EL1 = 618000 (EHID20_EL1) | |
# [cpu0] Pass: msr EHID20_EL1, x13 = 618100 (OK) (EHID20_EL1) | |
# [cpu0] Pass: mrs x13, EHID9_EL1 = 600000811 (EHID9_EL1) | |
# [cpu0] Pass: msr EHID9_EL1, x13 = 600000811 (OK) (EHID9_EL1) | |
# [cpu0] Pass: mrs x13, EHID20_EL1 = 618100 (EHID20_EL1) | |
# [cpu0] Pass: msr EHID20_EL1, x13 = 618100 (OK) (EHID20_EL1) | |
# [cpu0] Pass: mrs x13, EHID20_EL1 = 618100 (EHID20_EL1) | |
# [cpu0] Pass: msr EHID20_EL1, x13 = 618100 (OK) (EHID20_EL1) | |
# [cpu0] Pass: mrs x13, EHID20_EL1 = 618100 (EHID20_EL1) | |
# [cpu0] Pass: msr EHID20_EL1, x13 = 618100 (OK) (EHID20_EL1) | |
# [cpu0] Pass: mrs x13, EHID20_EL1 = 618100 (EHID20_EL1) | |
# [cpu0] Pass: msr EHID20_EL1, x13 = 618100 (OK) (EHID20_EL1) | |
# [cpu0] Pass: mrs x13, ACC_CFG_EL1 = d (ACC_CFG_EL1) | |
# [cpu0] Skip: msr ACC_CFG_EL1, x13 = d | |
# [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR R 28e080238+0:32 = 0xff -> 0xff | |
# [cpu0] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR R 28e580230+0:32 = 0xff -> 0xff | |
# [cpu0] PMGR R 28e580240+0:32 = 0xff -> 0xff | |
# [cpu0] PMGR R 292280088+0:32 = 0xff -> 0xff | |
# [cpu0] PMGR R 2922800d0+0:32 = 0xff -> 0xff | |
# [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write | |
# [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write | |
# [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e0801d8+0:32 = 0x1f0000ff: Dangerous write | |
# [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write | |
# [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write | |
# [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e0801f0+0:32 = 0x1f0000ff: Dangerous write | |
# [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write | |
# [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write | |
# [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e080200+0:32 = 0x1f0000ff: Dangerous write | |
# [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e080218+0:32 = 0xf0000ff: Dangerous write | |
# [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e080218+0:32 = 0xf0000ff: Dangerous write | |
# [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e080218+0:32 = 0x1f0000ff: Dangerous write | |
# [cpu0] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e580148+0:32 = 0xf0000ff: Dangerous write | |
# [cpu0] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e580148+0:32 = 0xf0000ff: Dangerous write | |
# [cpu0] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e580148+0:32 = 0x1f0000ff: Dangerous write | |
# [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e580150+0:32 = 0xf0000ff: Dangerous write | |
# [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e580150+0:32 = 0xf0000ff: Dangerous write | |
# [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e580150+0:32 = 0x1f0000ff: Dangerous write | |
# [cpu0] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e580160+0:32 = 0xf0000ff: Dangerous write | |
# [cpu0] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e580160+0:32 = 0xf0000ff: Dangerous write | |
# [cpu0] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e580160+0:32 = 0x1f0000ff: Dangerous write | |
# [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e580180+0:32 = 0xf0000ff: Dangerous write | |
# [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e580180+0:32 = 0xf0000ff: Dangerous write | |
# [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff | |
# [cpu0] PMGR W 28e580180+0:32 = 0x1f0000ff: Dangerous write | |
# [cpu0] PMGR R 28e580230+0:32 = 0xff -> 0xff | |
# [cpu0] PMGR W 28e580230+0:32 = 0xff: Dangerous write | |
# [cpu0] PMGR R 28e580230+0:32 = 0xff -> 0xff | |
# [cpu0] PMGR W 28e580230+0:32 = 0xff: Dangerous write | |
# [cpu0] PMGR R 28e580230+0:32 = 0xff -> 0xff | |
# [cpu0] PMGR W 28e580230+0:32 = 0x100000ff: Dangerous write | |
# [cpu0] PMGR R 28e580240+0:32 = 0xff -> 0xff | |
# [cpu0] PMGR W 28e580240+0:32 = 0xff: Dangerous write | |
# [cpu0] PMGR R 28e580240+0:32 = 0xff -> 0xff | |
# [cpu0] PMGR W 28e580240+0:32 = 0xff: Dangerous write | |
# [cpu0] PMGR R 28e580240+0:32 = 0xff -> 0xff | |
# [cpu0] PMGR W 28e580240+0:32 = 0x100000ff: Dangerous write | |
# [cpu0] PMGR R 28e080238+0:32 = 0xff -> 0xff | |
# [cpu0] PMGR R 2922800d0+0:32 = 0xff -> 0xff | |
# [cpu0] PMGR W 2922800d0+0:32 = 0xf0: Dangerous write | |
# [cpu0] PMGR R 2922800d0+0:32 = 0xff -> 0x0 | |
# [cpu0] PMGR W 28e080238+0:32 = 0x3f0: Dangerous write | |
# [cpu0] PMGR R 28e080238+0:32 = 0xff -> 0x0 | |
# [cpu0] PMGR R 28e080238+0:32 = 0xff -> 0x0 | |
# [cpu0] PMGR R 2922800d0+0:32 = 0xff -> 0x0 | |
# [cpu0] PMGR R 292280088+0:32 = 0xff -> 0xff | |
# [cpu0] PMGR W 292280088+0:32 = 0x3f0: Dangerous write | |
# [cpu0] PMGR R 292280088+0:32 = 0xff -> 0x0 | |
# [cpu0] CPUSTART W 28e0d4000+4:32 = 0x2 | |
# [cpu0] CPUSTART W 28e0d4000+8:32 = 0x2 | |
# [cpu0] Starting guest secondary 0:0:1 | |
# [cpu0] CPU #1: RVBAR = 0x10017b10000 | |
# [cpu1] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) | |
# [cpu0] CPUSTART W 28e0d4000+c:32 = 0x0 | |
# [cpu0] CPUSTART W 28e0d4000+10:32 = 0x0 | |
# [cpu1] Pass: mrs x13, ACC_CFG_EL1 = d (ACC_CFG_EL1) | |
# [cpu1] Skip: msr ACC_CFG_EL1, x13 = d | |
# [cpu1] Shadow: mrs x12, MDSCR_EL1 = 0 | |
# [cpu1] Shadow: msr MDSCR_EL1, x12 = 1000 | |
# [cpu1] Pass: mrs x13, HID5_EL1 = 2082df50f700df12 (HID5_EL1) | |
# [cpu1] Pass: msr HID5_EL1, x13 = 2082df50f700df12 (OK) (HID5_EL1) | |
# [cpu1] Pass: mrs x13, EHID10_EL1 = 3000528002788 (EHID10_EL1) | |
# [cpu1] Pass: msr EHID10_EL1, x13 = 3000528002788 (OK) (EHID10_EL1) | |
# [cpu1] Pass: mrs x13, EHID10_EL1 = 3000528002788 (EHID10_EL1) | |
# [cpu1] Pass: msr EHID10_EL1, x13 = 3000528002788 (OK) (EHID10_EL1) | |
# [cpu1] Pass: mrs x13, EHID20_EL1 = 618000 (EHID20_EL1) | |
# [cpu1] Pass: msr EHID20_EL1, x13 = 618100 (OK) (EHID20_EL1) | |
# [cpu1] Pass: mrs x13, EHID9_EL1 = 600000811 (EHID9_EL1) | |
# [cpu1] Pass: msr EHID9_EL1, x13 = 600000811 (OK) (EHID9_EL1) | |
# [cpu1] Pass: mrs x13, EHID20_EL1 = 618100 (EHID20_EL1) | |
# [cpu1] Pass: msr EHID20_EL1, x13 = 618100 (OK) (EHID20_EL1) | |
# [cpu1] Pass: mrs x13, EHID20_EL1 = 618100 (EHID20_EL1) | |
# [cpu1] Pass: msr EHID20_EL1, x13 = 618100 (OK) (EHID20_EL1) | |
# [cpu1] Pass: mrs x13, EHID20_EL1 = 618100 (EHID20_EL1) | |
# [cpu1] Pass: msr EHID20_EL1, x13 = 618100 (OK) (EHID20_EL1) | |
# [cpu1] Pass: mrs x13, EHID20_EL1 = 618100 (EHID20_EL1) | |
# [cpu1] Pass: msr EHID20_EL1, x13 = 618100 (OK) (EHID20_EL1) | |
# [cpu0] CPUSTART W 28e0d4000+4:32 = 0x10 | |
# [cpu0] CPUSTART W 28e0d4000+8:32 = 0x0 | |
# [cpu0] CPUSTART W 28e0d4000+c:32 = 0x1 | |
# [cpu0] Starting guest secondary 0:1:0 | |
# [cpu0] CPU #2: RVBAR = 0x10017b10000 | |
# [cpu2] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) | |
# [cpu0] CPUSTART W 28e0d4000+10:32 = 0x0 | |
# [cpu2] Pass: mrs x13, ACC_CFG_EL1 = d (ACC_CFG_EL1) | |
# [cpu2] Skip: msr ACC_CFG_EL1, x13 = d | |
# [cpu2] Pass: mrs x13, HID13_EL1 = 332200211010205 (HID13_EL1) | |
# [cpu2] Pass: msr HID13_EL1, x13 = c332200211010205 (OK) (HID13_EL1) | |
# [cpu2] Pass: mrs x13, HID14_EL1 = 200000bb8 (HID14_EL1) | |
# [cpu2] Pass: msr HID14_EL1, x13 = 300000bb8 (OK) (HID14_EL1) | |
# [cpu2] Shadow: mrs x12, MDSCR_EL1 = 0 | |
# [cpu2] Shadow: msr MDSCR_EL1, x12 = 1000 | |
# [cpu2] Pass: mrs x13, HID5_EL1 = 2082df205700ff12 (HID5_EL1) | |
# [cpu2] Pass: msr HID5_EL1, x13 = 2082df205700ff12 (OK) (HID5_EL1) | |
# [cpu2] Pass: mrs x13, HID13_EL1 = c332200211010205 (HID13_EL1) | |
# [cpu2] Pass: msr HID13_EL1, x13 = c332200211010205 (OK) (HID13_EL1) | |
# [cpu2] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu2] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu2] Pass: mrs x13, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) | |
# [cpu2] Pass: msr HID3_EL1, x13 = 4180000cf8001fe0 (OK) (HID3_EL1) | |
# [cpu2] Pass: mrs x13, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) | |
# [cpu2] Pass: msr HID3_EL1, x13 = 4180000cf8001fe0 (OK) (HID3_EL1) | |
# [cpu2] Pass: mrs x13, HID1_EL1 = 1400000002000000 (HID1_EL1) | |
# [cpu2] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu2] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu2] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu2] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu2] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu2] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu2] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu2] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu2] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu2] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu2] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu2] Pass: mrs x13, HID11_EL1 = 804000010008000 (HID11_EL1) | |
# [cpu2] Pass: msr HID11_EL1, x13 = 804000010008000 (OK) (HID11_EL1) | |
# [cpu2] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu2] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu2] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu2] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu2] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu2] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu2] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu2] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu2] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu2] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu2] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu2] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu2] Pass: mrs x13, HID11_EL1 = 804000010008000 (HID11_EL1) | |
# [cpu2] Pass: msr HID11_EL1, x13 = 804000010008000 (OK) (HID11_EL1) | |
# [cpu2] Pass: mrs x13, HID18_EL1 = 2000040004000 (HID18_EL1) | |
# [cpu2] Pass: msr HID18_EL1, x13 = 2000040004000 (OK) (HID18_EL1) | |
# [cpu2] Pass: mrs x13, HID21_EL1 = 1040000 (HID21_EL1) | |
# [cpu2] Pass: msr HID21_EL1, x13 = 1040000 (OK) (HID21_EL1) | |
# [cpu2] Pass: mrs x13, HID1_EL1 = 1440000002000000 (HID1_EL1) | |
# [cpu2] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu2] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu2] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu2] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu2] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu2] Pass: mrs x13, HID1_EL1 = 1440000002000000 (HID1_EL1) | |
# [cpu2] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu2] Pass: mrs x13, HID18_EL1 = 2000040004000 (HID18_EL1) | |
# [cpu2] Pass: msr HID18_EL1, x13 = 2000040004000 (OK) (HID18_EL1) | |
# [cpu0] CPUSTART W 28e0d4000+4:32 = 0x20 | |
# [cpu0] CPUSTART W 28e0d4000+8:32 = 0x0 | |
# [cpu0] CPUSTART W 28e0d4000+c:32 = 0x2 | |
# [cpu0] Starting guest secondary 0:1:1 | |
# [cpu0] CPU #3: RVBAR = 0x10017b10000 | |
# [cpu3] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) | |
# [cpu0] CPUSTART W 28e0d4000+10:32 = 0x0 | |
# [cpu3] Pass: mrs x13, ACC_CFG_EL1 = d (ACC_CFG_EL1) | |
# [cpu3] Skip: msr ACC_CFG_EL1, x13 = d | |
# [cpu3] Pass: mrs x13, HID13_EL1 = 332200211010205 (HID13_EL1) | |
# [cpu3] Pass: msr HID13_EL1, x13 = c332200211010205 (OK) (HID13_EL1) | |
# [cpu3] Pass: mrs x13, HID14_EL1 = 200000bb8 (HID14_EL1) | |
# [cpu3] Pass: msr HID14_EL1, x13 = 300000bb8 (OK) (HID14_EL1) | |
# [cpu3] Shadow: mrs x12, MDSCR_EL1 = 0 | |
# [cpu3] Shadow: msr MDSCR_EL1, x12 = 1000 | |
# [cpu3] Pass: mrs x13, HID5_EL1 = 2082df205700ff12 (HID5_EL1) | |
# [cpu3] Pass: msr HID5_EL1, x13 = 2082df205700ff12 (OK) (HID5_EL1) | |
# [cpu3] Pass: mrs x13, HID13_EL1 = c332200211010205 (HID13_EL1) | |
# [cpu3] Pass: msr HID13_EL1, x13 = c332200211010205 (OK) (HID13_EL1) | |
# [cpu3] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu3] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu3] Pass: mrs x13, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) | |
# [cpu3] Pass: msr HID3_EL1, x13 = 4180000cf8001fe0 (OK) (HID3_EL1) | |
# [cpu3] Pass: mrs x13, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) | |
# [cpu3] Pass: msr HID3_EL1, x13 = 4180000cf8001fe0 (OK) (HID3_EL1) | |
# [cpu3] Pass: mrs x13, HID1_EL1 = 1400000002000000 (HID1_EL1) | |
# [cpu3] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu3] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu3] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu3] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu3] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu3] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu3] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu3] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu3] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu3] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu3] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu3] Pass: mrs x13, HID11_EL1 = 804000010008000 (HID11_EL1) | |
# [cpu3] Pass: msr HID11_EL1, x13 = 804000010008000 (OK) (HID11_EL1) | |
# [cpu3] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu3] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu3] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu3] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu3] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu3] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu3] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu3] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu3] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu3] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu3] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu3] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu3] Pass: mrs x13, HID11_EL1 = 804000010008000 (HID11_EL1) | |
# [cpu3] Pass: msr HID11_EL1, x13 = 804000010008000 (OK) (HID11_EL1) | |
# [cpu3] Pass: mrs x13, HID18_EL1 = 2000040004000 (HID18_EL1) | |
# [cpu3] Pass: msr HID18_EL1, x13 = 2000040004000 (OK) (HID18_EL1) | |
# [cpu3] Pass: mrs x13, HID21_EL1 = 1040000 (HID21_EL1) | |
# [cpu3] Pass: msr HID21_EL1, x13 = 1040000 (OK) (HID21_EL1) | |
# [cpu3] Pass: mrs x13, HID1_EL1 = 1440000002000000 (HID1_EL1) | |
# [cpu3] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu3] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu3] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu3] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu3] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu3] Pass: mrs x13, HID1_EL1 = 1440000002000000 (HID1_EL1) | |
# [cpu3] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu0] CPUSTART W 28e0d4000+4:32 = 0x40 | |
# [cpu0] CPUSTART W 28e0d4000+8:32 = 0x0 | |
# [cpu0] CPUSTART W 28e0d4000+c:32 = 0x4 | |
# [cpu0] Starting guest secondary 0:1:2 | |
# [cpu0] CPU #4: RVBAR = 0x10017b10000 | |
# [cpu0] CPUSTART W 28e0d4000+10:32 = 0x0 | |
# [cpu3] Pass: mrs x13, HID18_EL1 = 2000040004000 (HID18_EL1) | |
# [cpu3] Pass: msr HID18_EL1, x13 = 2000040004000 (OK) (HID18_EL1) | |
# [cpu4] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) | |
# [cpu4] Pass: mrs x13, ACC_CFG_EL1 = d (ACC_CFG_EL1) | |
# [cpu4] Skip: msr ACC_CFG_EL1, x13 = d | |
# [cpu4] Pass: mrs x13, HID13_EL1 = 332200211010205 (HID13_EL1) | |
# [cpu4] Pass: msr HID13_EL1, x13 = c332200211010205 (OK) (HID13_EL1) | |
# [cpu4] Pass: mrs x13, HID14_EL1 = 200000bb8 (HID14_EL1) | |
# [cpu4] Pass: msr HID14_EL1, x13 = 300000bb8 (OK) (HID14_EL1) | |
# [cpu4] Shadow: mrs x12, MDSCR_EL1 = 0 | |
# [cpu4] Shadow: msr MDSCR_EL1, x12 = 1000 | |
# [cpu4] Pass: mrs x13, HID5_EL1 = 2082df205700ff12 (HID5_EL1) | |
# [cpu4] Pass: msr HID5_EL1, x13 = 2082df205700ff12 (OK) (HID5_EL1) | |
# [cpu4] Pass: mrs x13, HID13_EL1 = c332200211010205 (HID13_EL1) | |
# [cpu4] Pass: msr HID13_EL1, x13 = c332200211010205 (OK) (HID13_EL1) | |
# [cpu4] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu4] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu4] Pass: mrs x13, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) | |
# [cpu4] Pass: msr HID3_EL1, x13 = 4180000cf8001fe0 (OK) (HID3_EL1) | |
# [cpu4] Pass: mrs x13, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) | |
# [cpu4] Pass: msr HID3_EL1, x13 = 4180000cf8001fe0 (OK) (HID3_EL1) | |
# [cpu4] Pass: mrs x13, HID1_EL1 = 1400000002000000 (HID1_EL1) | |
# [cpu4] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu4] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu0] CPUSTART W 28e0d4000+4:32 = 0x80 | |
# [cpu0] CPUSTART W 28e0d4000+8:32 = 0x0 | |
# [cpu0] CPUSTART W 28e0d4000+c:32 = 0x8 | |
# [cpu0] Starting guest secondary 0:1:3 | |
# [cpu0] CPU #5: RVBAR = 0x10017b10000 | |
# [cpu5] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) | |
# [cpu0] CPUSTART W 28e0d4000+10:32 = 0x0 | |
# [cpu4] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu4] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu4] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu5] Pass: mrs x13, ACC_CFG_EL1 = d (ACC_CFG_EL1) | |
# [cpu5] Skip: msr ACC_CFG_EL1, x13 = d | |
# [cpu5] Pass: mrs x13, HID13_EL1 = 332200211010205 (HID13_EL1) | |
# [cpu5] Pass: msr HID13_EL1, x13 = c332200211010205 (OK) (HID13_EL1) | |
# [cpu5] Pass: mrs x13, HID14_EL1 = 200000bb8 (HID14_EL1) | |
# [cpu5] Pass: msr HID14_EL1, x13 = 300000bb8 (OK) (HID14_EL1) | |
# [cpu5] Shadow: mrs x12, MDSCR_EL1 = 0 | |
# [cpu4] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu4] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu5] Shadow: msr MDSCR_EL1, x12 = 1000 | |
# [cpu4] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu4] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu5] Pass: mrs x13, HID5_EL1 = 2082df205700ff12 (HID5_EL1) | |
# [cpu5] Pass: msr HID5_EL1, x13 = 2082df205700ff12 (OK) (HID5_EL1) | |
# [cpu0] CPUSTART W 28e0d4000+4:32 = 0x100 | |
# [cpu0] CPUSTART W 28e0d4000+8:32 = 0x0 | |
# [cpu0] CPUSTART W 28e0d4000+c:32 = 0x0 | |
# [cpu5] Pass: mrs x13, HID13_EL1 = c332200211010205 (HID13_EL1) | |
# [cpu0] CPUSTART W 28e0d4000+10:32 = 0x1 | |
# [cpu0] Starting guest secondary 0:2:0 | |
# [cpu0] CPU #6: RVBAR = 0x10017b10000 | |
# [cpu6] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) | |
# [cpu6] Pass: mrs x13, ACC_CFG_EL1 = d (ACC_CFG_EL1) | |
# [cpu4] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu6] Skip: msr ACC_CFG_EL1, x13 = d | |
# [cpu4] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu6] Pass: mrs x13, HID13_EL1 = 332200211010205 (HID13_EL1) | |
# [cpu6] Pass: msr HID13_EL1, x13 = c332200211010205 (OK) (HID13_EL1) | |
# [cpu5] Pass: msr HID13_EL1, x13 = c332200211010205 (OK) (HID13_EL1) | |
# [cpu6] Pass: mrs x13, HID14_EL1 = 200000bb8 (HID14_EL1) | |
# [cpu6] Pass: msr HID14_EL1, x13 = 300000bb8 (OK) (HID14_EL1) | |
# [cpu6] Shadow: mrs x12, MDSCR_EL1 = 0 | |
# [cpu6] Shadow: msr MDSCR_EL1, x12 = 1000 | |
# [cpu6] Pass: mrs x13, HID5_EL1 = 2082df205700ff12 (HID5_EL1) | |
# [cpu6] Pass: msr HID5_EL1, x13 = 2082df205700ff12 (OK) (HID5_EL1) | |
# [cpu6] Pass: mrs x13, HID13_EL1 = c332200211010205 (HID13_EL1) | |
# [cpu6] Pass: msr HID13_EL1, x13 = c332200211010205 (OK) (HID13_EL1) | |
# [cpu6] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu6] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu6] Pass: mrs x13, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) | |
# [cpu6] Pass: msr HID3_EL1, x13 = 4180000cf8001fe0 (OK) (HID3_EL1) | |
# [cpu6] Pass: mrs x13, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) | |
# [cpu5] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu6] Pass: msr HID3_EL1, x13 = 4180000cf8001fe0 (OK) (HID3_EL1) | |
# [cpu6] Pass: mrs x13, HID1_EL1 = 1400000002000000 (HID1_EL1) | |
# [cpu6] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu6] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu4] Pass: mrs x13, HID11_EL1 = 804000010008000 (HID11_EL1) | |
# [cpu6] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu5] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu5] Pass: mrs x13, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) | |
# [cpu6] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu6] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu6] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu6] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu6] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu6] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu6] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu6] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu6] Pass: mrs x13, HID11_EL1 = 804000010008000 (HID11_EL1) | |
# [cpu6] Pass: msr HID11_EL1, x13 = 804000010008000 (OK) (HID11_EL1) | |
# [cpu5] Pass: msr HID3_EL1, x13 = 4180000cf8001fe0 (OK) (HID3_EL1) | |
# [cpu6] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu4] Pass: msr HID11_EL1, x13 = 804000010008000 (OK) (HID11_EL1) | |
# [cpu6] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu6] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu6] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu6] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu6] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu6] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu6] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu6] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu6] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu6] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu6] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu6] Pass: mrs x13, HID11_EL1 = 804000010008000 (HID11_EL1) | |
# [cpu6] Pass: msr HID11_EL1, x13 = 804000010008000 (OK) (HID11_EL1) | |
# [cpu6] Pass: mrs x13, HID18_EL1 = 2000040004000 (HID18_EL1) | |
# [cpu6] Pass: msr HID18_EL1, x13 = 2000040004000 (OK) (HID18_EL1) | |
# [cpu6] Pass: mrs x13, HID21_EL1 = 1040000 (HID21_EL1) | |
# [cpu6] Pass: msr HID21_EL1, x13 = 1040000 (OK) (HID21_EL1) | |
# [cpu5] Pass: mrs x13, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) | |
# [cpu5] Pass: msr HID3_EL1, x13 = 4180000cf8001fe0 (OK) (HID3_EL1) | |
# [cpu6] Pass: mrs x13, HID1_EL1 = 1440000002000000 (HID1_EL1) | |
# [cpu6] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu6] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu6] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu6] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu6] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu5] Pass: mrs x13, HID1_EL1 = 1400000002000000 (HID1_EL1) | |
# [cpu6] Pass: mrs x13, HID1_EL1 = 1440000002000000 (HID1_EL1) | |
# [cpu6] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu6] Pass: mrs x13, HID18_EL1 = 2000040004000 (HID18_EL1) | |
# [cpu6] Pass: msr HID18_EL1, x13 = 2000040004000 (OK) (HID18_EL1) | |
# [cpu4] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu5] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu4] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu5] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu4] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu5] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu5] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu5] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu5] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu5] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu4] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu4] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu5] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu0] CPUSTART W 28e0d4000+4:32 = 0x200 | |
# [cpu4] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu5] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu0] CPUSTART W 28e0d4000+8:32 = 0x0 | |
# [cpu0] CPUSTART W 28e0d4000+c:32 = 0x0 | |
# [cpu0] CPUSTART W 28e0d4000+10:32 = 0x2 | |
# [cpu0] Starting guest secondary 0:2:1 | |
# [cpu0] CPU #7: RVBAR = 0x10017b10000 | |
# [cpu7] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) | |
# [cpu7] Pass: mrs x13, ACC_CFG_EL1 = d (ACC_CFG_EL1) | |
# [cpu7] Skip: msr ACC_CFG_EL1, x13 = d | |
# [cpu4] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu7] Pass: mrs x13, HID13_EL1 = 332200211010205 (HID13_EL1) | |
# [cpu7] Pass: msr HID13_EL1, x13 = c332200211010205 (OK) (HID13_EL1) | |
# [cpu7] Pass: mrs x13, HID14_EL1 = 200000bb8 (HID14_EL1) | |
# [cpu7] Pass: msr HID14_EL1, x13 = 300000bb8 (OK) (HID14_EL1) | |
# [cpu7] Shadow: mrs x12, MDSCR_EL1 = 0 | |
# [cpu7] Shadow: msr MDSCR_EL1, x12 = 1000 | |
# [cpu4] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu4] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu7] Pass: mrs x13, HID5_EL1 = 2082df205700ff12 (HID5_EL1) | |
# [cpu7] Pass: msr HID5_EL1, x13 = 2082df205700ff12 (OK) (HID5_EL1) | |
# [cpu7] Pass: mrs x13, HID13_EL1 = c332200211010205 (HID13_EL1) | |
# [cpu7] Pass: msr HID13_EL1, x13 = c332200211010205 (OK) (HID13_EL1) | |
# [cpu7] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu7] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu7] Pass: mrs x13, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) | |
# [cpu7] Pass: msr HID3_EL1, x13 = 4180000cf8001fe0 (OK) (HID3_EL1) | |
# [cpu7] Pass: mrs x13, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) | |
# [cpu7] Pass: msr HID3_EL1, x13 = 4180000cf8001fe0 (OK) (HID3_EL1) | |
# [cpu7] Pass: mrs x13, HID1_EL1 = 1400000002000000 (HID1_EL1) | |
# [cpu7] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu7] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu4] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu7] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu7] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu0] CPUSTART W 28e0d4000+4:32 = 0x400 | |
# [cpu7] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu0] CPUSTART W 28e0d4000+8:32 = 0x0 | |
# [cpu0] CPUSTART W 28e0d4000+c:32 = 0x0 | |
# [cpu4] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu7] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu0] CPUSTART W 28e0d4000+10:32 = 0x4 | |
# [cpu0] Starting guest secondary 0:2:2 | |
# [cpu0] CPU #8: RVBAR = 0x10017b10000 | |
# [cpu7] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu8] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) | |
# [cpu7] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu7] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu7] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu7] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu7] Pass: mrs x13, HID11_EL1 = 804000010008000 (HID11_EL1) | |
# [cpu7] Pass: msr HID11_EL1, x13 = 804000010008000 (OK) (HID11_EL1) | |
# [cpu7] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu7] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu7] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu7] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu5] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu7] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu7] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu4] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu7] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu7] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu7] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu7] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu0] CPUSTART W 28e0d4000+4:32 = 0x800 | |
# [cpu7] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu0] CPUSTART W 28e0d4000+8:32 = 0x0 | |
# [cpu7] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu0] CPUSTART W 28e0d4000+c:32 = 0x0 | |
# [cpu0] CPUSTART W 28e0d4000+10:32 = 0x8 | |
# [cpu0] Starting guest secondary 0:2:3 | |
# [cpu0] CPU #9: RVBAR = 0x10017b10000 | |
# [cpu7] Pass: mrs x13, HID11_EL1 = 804000010008000 (HID11_EL1) | |
# [cpu7] Pass: msr HID11_EL1, x13 = 804000010008000 (OK) (HID11_EL1) | |
# [cpu9] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) | |
# [cpu7] Pass: mrs x13, HID18_EL1 = 2000040004000 (HID18_EL1) | |
# [cpu7] Pass: msr HID18_EL1, x13 = 2000040004000 (OK) (HID18_EL1) | |
# [cpu5] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu4] Pass: mrs x13, HID11_EL1 = 804000010008000 (HID11_EL1) | |
# [cpu7] Pass: mrs x13, HID21_EL1 = 1040000 (HID21_EL1) | |
# [cpu7] Pass: msr HID21_EL1, x13 = 1040000 (OK) (HID21_EL1) | |
# [cpu4] Pass: msr HID11_EL1, x13 = 804000010008000 (OK) (HID11_EL1) | |
# [cpu5] Pass: mrs x13, HID11_EL1 = 804000010008000 (HID11_EL1) | |
# [cpu7] Pass: mrs x13, HID1_EL1 = 1440000002000000 (HID1_EL1) | |
# [cpu8] Pass: mrs x13, ACC_CFG_EL1 = d (ACC_CFG_EL1) | |
# [cpu7] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu4] Pass: mrs x13, HID18_EL1 = 2000040004000 (HID18_EL1) | |
# [cpu7] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu9] Pass: mrs x13, ACC_CFG_EL1 = d (ACC_CFG_EL1) | |
# [cpu7] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu5] Pass: msr HID11_EL1, x13 = 804000010008000 (OK) (HID11_EL1) | |
# [cpu7] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu4] Pass: msr HID18_EL1, x13 = 2000040004000 (OK) (HID18_EL1) | |
# [cpu7] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu8] Skip: msr ACC_CFG_EL1, x13 = d | |
# [cpu7] Pass: mrs x13, HID1_EL1 = 1440000002000000 (HID1_EL1) | |
# [cpu4] Pass: mrs x13, HID21_EL1 = 1040000 (HID21_EL1) | |
# [cpu7] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu8] Pass: mrs x13, HID13_EL1 = 332200211010205 (HID13_EL1) | |
# [cpu4] Pass: msr HID21_EL1, x13 = 1040000 (OK) (HID21_EL1) | |
# [cpu4] Pass: mrs x13, HID1_EL1 = 1440000002000000 (HID1_EL1) | |
# [cpu9] Skip: msr ACC_CFG_EL1, x13 = d | |
# [cpu5] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu5] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu9] Pass: mrs x13, HID13_EL1 = 332200211010205 (HID13_EL1) | |
# [cpu7] Pass: mrs x13, HID18_EL1 = 2000040004000 (HID18_EL1) | |
# [cpu9] Pass: msr HID13_EL1, x13 = c332200211010205 (OK) (HID13_EL1) | |
# [cpu7] Pass: msr HID18_EL1, x13 = 2000040004000 (OK) (HID18_EL1) | |
# [cpu9] Pass: mrs x13, HID14_EL1 = 200000bb8 (HID14_EL1) | |
# [cpu5] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu8] Pass: msr HID13_EL1, x13 = c332200211010205 (OK) (HID13_EL1) | |
# [cpu8] Pass: mrs x13, HID14_EL1 = 200000bb8 (HID14_EL1) | |
# [cpu9] Pass: msr HID14_EL1, x13 = 300000bb8 (OK) (HID14_EL1) | |
# [cpu5] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu9] Shadow: mrs x12, MDSCR_EL1 = 0 | |
# [cpu9] Shadow: msr MDSCR_EL1, x12 = 1000 | |
# [cpu8] Pass: msr HID14_EL1, x13 = 300000bb8 (OK) (HID14_EL1) | |
# [cpu4] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu8] Shadow: mrs x12, MDSCR_EL1 = 0 | |
# [cpu5] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu5] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu5] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu8] Shadow: msr MDSCR_EL1, x12 = 1000 | |
# [cpu4] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu5] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu8] Pass: mrs x13, HID5_EL1 = 2082df205700ff12 (HID5_EL1) | |
# [cpu9] Pass: mrs x13, HID5_EL1 = 2082df205700ff12 (HID5_EL1) | |
# [cpu4] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu4] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu9] Pass: msr HID5_EL1, x13 = 2082df205700ff12 (OK) (HID5_EL1) | |
# [cpu9] Pass: mrs x13, HID13_EL1 = c332200211010205 (HID13_EL1) | |
# [cpu4] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu8] Pass: msr HID5_EL1, x13 = 2082df205700ff12 (OK) (HID5_EL1) | |
# [cpu9] Pass: msr HID13_EL1, x13 = c332200211010205 (OK) (HID13_EL1) | |
# [cpu9] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu9] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu5] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu8] Pass: mrs x13, HID13_EL1 = c332200211010205 (HID13_EL1) | |
# [cpu8] Pass: msr HID13_EL1, x13 = c332200211010205 (OK) (HID13_EL1) | |
# [cpu8] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu5] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu4] Pass: mrs x13, HID1_EL1 = 1440000002000000 (HID1_EL1) | |
# [cpu8] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu5] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu4] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu5] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu9] Pass: mrs x13, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) | |
# [cpu5] Pass: mrs x13, HID11_EL1 = 804000010008000 (HID11_EL1) | |
# [cpu9] Pass: msr HID3_EL1, x13 = 4180000cf8001fe0 (OK) (HID3_EL1) | |
# [cpu5] Pass: msr HID11_EL1, x13 = 804000010008000 (OK) (HID11_EL1) | |
# [cpu8] Pass: mrs x13, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) | |
# [cpu4] Pass: mrs x13, HID18_EL1 = 2000040004000 (HID18_EL1) | |
# [cpu5] Pass: mrs x13, HID18_EL1 = 2000040004000 (HID18_EL1) | |
# [cpu4] Pass: msr HID18_EL1, x13 = 2000040004000 (OK) (HID18_EL1) | |
# [cpu8] Pass: msr HID3_EL1, x13 = 4180000cf8001fe0 (OK) (HID3_EL1) | |
# [cpu8] Pass: mrs x13, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) | |
# [cpu5] Pass: msr HID18_EL1, x13 = 2000040004000 (OK) (HID18_EL1) | |
# [cpu9] Pass: mrs x13, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) | |
# [cpu9] Pass: msr HID3_EL1, x13 = 4180000cf8001fe0 (OK) (HID3_EL1) | |
# [cpu8] Pass: msr HID3_EL1, x13 = 4180000cf8001fe0 (OK) (HID3_EL1) | |
# [cpu9] Pass: mrs x13, HID1_EL1 = 1400000002000000 (HID1_EL1) | |
# [cpu9] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu5] Pass: mrs x13, HID21_EL1 = 1040000 (HID21_EL1) | |
# [cpu5] Pass: msr HID21_EL1, x13 = 1040000 (OK) (HID21_EL1) | |
# [cpu9] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu5] Pass: mrs x13, HID1_EL1 = 1440000002000000 (HID1_EL1) | |
# [cpu8] Pass: mrs x13, HID1_EL1 = 1400000002000000 (HID1_EL1) | |
# [cpu8] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu5] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu9] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu8] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu9] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu8] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu9] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu5] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu5] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu9] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu9] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu8] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu9] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu8] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu9] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu9] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu9] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu8] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu8] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu9] Pass: mrs x13, HID11_EL1 = 804000010008000 (HID11_EL1) | |
# [cpu8] Pass: mrs x13, HID16_EL1 = 6900000440000000 (HID16_EL1) | |
# [cpu5] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu8] Pass: msr HID16_EL1, x13 = 6900000440000000 (OK) (HID16_EL1) | |
# [cpu5] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu9] Pass: msr HID11_EL1, x13 = 804000010008000 (OK) (HID11_EL1) | |
# [cpu9] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu9] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu8] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu9] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu8] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu9] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu5] Pass: mrs x13, HID1_EL1 = 1440000002000000 (HID1_EL1) | |
# [cpu5] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu8] Pass: mrs x13, HID11_EL1 = 804000010008000 (HID11_EL1) | |
# [cpu9] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu9] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu8] Pass: msr HID11_EL1, x13 = 804000010008000 (OK) (HID11_EL1) | |
# [cpu8] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu8] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu8] Pass: mrs x13, HID0_EL1 = 10002990120e0e00 (HID0_EL1) | |
# [cpu8] Pass: msr HID0_EL1, x13 = 10002990120e0e00 (OK) (HID0_EL1) | |
# [cpu9] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu9] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu8] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu9] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu8] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu9] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu8] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu9] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu8] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu5] Pass: mrs x13, HID18_EL1 = 2000040004000 (HID18_EL1) | |
# [cpu5] Pass: msr HID18_EL1, x13 = 2000040004000 (OK) (HID18_EL1) | |
# [cpu9] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu9] Pass: mrs x13, HID11_EL1 = 804000010008000 (HID11_EL1) | |
# [cpu8] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu9] Pass: msr HID11_EL1, x13 = 804000010008000 (OK) (HID11_EL1) | |
# [cpu8] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu8] Pass: mrs x13, HID9_EL1 = 8100086c000000 (HID9_EL1) | |
# [cpu9] Pass: mrs x13, HID18_EL1 = 2000040004000 (HID18_EL1) | |
# [cpu8] Pass: msr HID9_EL1, x13 = 8100086c000000 (OK) (HID9_EL1) | |
# [cpu9] Pass: msr HID18_EL1, x13 = 2000040004000 (OK) (HID18_EL1) | |
# [cpu8] Pass: mrs x13, HID11_EL1 = 804000010008000 (HID11_EL1) | |
# [cpu9] Pass: mrs x13, HID21_EL1 = 1040000 (HID21_EL1) | |
# [cpu8] Pass: msr HID11_EL1, x13 = 804000010008000 (OK) (HID11_EL1) | |
# [cpu8] Pass: mrs x13, HID18_EL1 = 2000040004000 (HID18_EL1) | |
# [cpu9] Pass: msr HID21_EL1, x13 = 1040000 (OK) (HID21_EL1) | |
# [cpu9] Pass: mrs x13, HID1_EL1 = 1440000002000000 (HID1_EL1) | |
# [cpu8] Pass: msr HID18_EL1, x13 = 2000040004000 (OK) (HID18_EL1) | |
# [cpu8] Pass: mrs x13, HID21_EL1 = 1040000 (HID21_EL1) | |
# [cpu9] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu9] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu8] Pass: msr HID21_EL1, x13 = 1040000 (OK) (HID21_EL1) | |
# [cpu9] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu8] Pass: mrs x13, HID1_EL1 = 1440000002000000 (HID1_EL1) | |
# [cpu9] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu8] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu8] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu9] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu9] Pass: mrs x13, HID1_EL1 = 1440000002000000 (HID1_EL1) | |
# [cpu8] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu9] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu8] Pass: mrs x13, HID7_EL1 = 3110000 (HID7_EL1) | |
# [cpu8] Pass: msr HID7_EL1, x13 = 3110000 (OK) (HID7_EL1) | |
# [cpu9] Pass: mrs x13, HID18_EL1 = 2000040004000 (HID18_EL1) | |
# [cpu9] Pass: msr HID18_EL1, x13 = 2000040004000 (OK) (HID18_EL1) | |
# [cpu8] Pass: mrs x13, HID1_EL1 = 1440000002000000 (HID1_EL1) | |
# [cpu8] Pass: msr HID1_EL1, x13 = 1440000002000000 (OK) (HID1_EL1) | |
# [cpu8] Pass: mrs x13, HID18_EL1 = 2000040004000 (HID18_EL1) | |
# [cpu8] Pass: msr HID18_EL1, x13 = 2000040004000 (OK) (HID18_EL1) | |
################### | |
# DOCK PLUGGED IN # | |
################### | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: R.4 CROSSBAR_MUX_CTRL = 0x0 (DPPHY_SELECT0=0x0(DISPEXT_0_0), DPIN1_SELECT0=0x0(DISPEXT_0_0), DPIN0_SELECT0=0x0(DISPEXT_0_0), DPPHY_SELECT1=0x0(DISPEXT_0_0), DPIN1_SELECT1=0x0(DISPEXT_0_0), DPIN0_SELECT1=0x0(DISPEXT_0_0)) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: W.4 CROSSBAR_MUX_CTRL = 0x0 (DPPHY_SELECT0=0x0(DISPEXT_0_0), DPIN1_SELECT0=0x0(DISPEXT_0_0), DPIN0_SELECT0=0x0(DISPEXT_0_0), DPPHY_SELECT1=0x0(DISPEXT_0_0), DPIN1_SELECT1=0x0(DISPEXT_0_0), DPIN0_SELECT1=0x0(DISPEXT_0_0)) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: R.4 CROSSBAR_MUX_CTRL = 0x0 (DPPHY_SELECT0=0x0(DISPEXT_0_0), DPIN1_SELECT0=0x0(DISPEXT_0_0), DPIN0_SELECT0=0x0(DISPEXT_0_0), DPPHY_SELECT1=0x0(DISPEXT_0_0), DPIN1_SELECT1=0x0(DISPEXT_0_0), DPIN0_SELECT1=0x0(DISPEXT_0_0)) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: W.4 CROSSBAR_MUX_CTRL = 0x0 (DPPHY_SELECT0=0x0(DISPEXT_0_0), DPIN1_SELECT0=0x0(DISPEXT_0_0), DPIN0_SELECT0=0x0(DISPEXT_0_0), DPPHY_SELECT1=0x0(DISPEXT_0_0), DPIN1_SELECT1=0x0(DISPEXT_0_0), DPIN0_SELECT1=0x0(DISPEXT_0_0)) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: W.4 UNK_TUNABLE = 0x5 (UNK_TUNABLE=0x5(T6000)) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: R.4 FIFO_WR_N_CLK_EN = 0x1ff (DISPEXT_0_0=1, DISPEXT_0_1=1, DISPEXT_1_0=1, DISPEXT_1_1=1, DISPEXT_2_0=1, DISPEXT_2_1=1, DISPEXT_3_0=1, DISPEXT_3_1=1, DISPEXT_4_0=1) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: W.4 FIFO_WR_N_CLK_EN = 0x1fe (DISPEXT_0_0=0, DISPEXT_0_1=1, DISPEXT_1_0=1, DISPEXT_1_1=1, DISPEXT_2_0=1, DISPEXT_2_1=1, DISPEXT_3_0=1, DISPEXT_3_1=1, DISPEXT_4_0=1) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: R.4 FIFO_RD_N_CLK_EN = 0x1ff (DISPEXT_0_0=1, DISPEXT_0_1=1, DISPEXT_1_0=1, DISPEXT_1_1=1, DISPEXT_2_0=1, DISPEXT_2_1=1, DISPEXT_3_0=1, DISPEXT_3_1=1, DISPEXT_4_0=1) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: W.4 FIFO_RD_N_CLK_EN = 0x1fe (DISPEXT_0_0=0, DISPEXT_0_1=1, DISPEXT_1_0=1, DISPEXT_1_1=1, DISPEXT_2_0=1, DISPEXT_2_1=1, DISPEXT_3_0=1, DISPEXT_3_1=1, DISPEXT_4_0=1) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: R.4 OUT_N_CLK_EN = 0x111 (DPIN0=1, DPIN1=1, DPPHY=1) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: W.4 OUT_N_CLK_EN = 0x110 (DPIN0=0, DPIN1=1, DPPHY=1) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: R.4 STAT_FIFO_WR_N_CLK_EN = 0x1fe (DISPEXT_0_0=0, DISPEXT_0_1=1, DISPEXT_1_0=1, DISPEXT_1_1=1, DISPEXT_2_0=1, DISPEXT_2_1=1, DISPEXT_3_0=1, DISPEXT_3_1=1, DISPEXT_4_0=1) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: R.4 STAT_FIFO_RD_N_CLK_EN = 0x1fe (DISPEXT_0_0=0, DISPEXT_0_1=1, DISPEXT_1_0=1, DISPEXT_1_1=1, DISPEXT_2_0=1, DISPEXT_2_1=1, DISPEXT_3_0=1, DISPEXT_3_1=1, DISPEXT_4_0=1) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: R.4 STAT_OUT_N_CLK_EN = 0x110 (DPIN0=0, DPIN1=1, DPPHY=1) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: R.4 FIFO_WR_UNK_EN = 0x0 (DISPEXT_0_0=0, DISPEXT_0_1=0, DISPEXT_1_0=0, DISPEXT_1_1=0, DISPEXT_2_0=0, DISPEXT_2_1=0, DISPEXT_3_0=0, DISPEXT_3_1=0, DISPEXT_4_0=0) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: W.4 FIFO_WR_UNK_EN = 0x1 (DISPEXT_0_0=1, DISPEXT_0_1=0, DISPEXT_1_0=0, DISPEXT_1_1=0, DISPEXT_2_0=0, DISPEXT_2_1=0, DISPEXT_3_0=0, DISPEXT_3_1=0, DISPEXT_4_0=0) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: R.4 FIFO_RD_UNK_EN = 0x0 (DISPEXT_0_0=0, DISPEXT_0_1=0, DISPEXT_1_0=0, DISPEXT_1_1=0, DISPEXT_2_0=0, DISPEXT_2_1=0, DISPEXT_3_0=0, DISPEXT_3_1=0, DISPEXT_4_0=0) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: W.4 FIFO_RD_UNK_EN = 0x1 (DISPEXT_0_0=1, DISPEXT_0_1=0, DISPEXT_1_0=0, DISPEXT_1_1=0, DISPEXT_2_0=0, DISPEXT_2_1=0, DISPEXT_3_0=0, DISPEXT_3_1=0, DISPEXT_4_0=0) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: R.4 OUT_UNK_EN = 0x0 (DPIN0=0, DPIN1=0, DPPHY=0) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: W.4 OUT_UNK_EN = 0x1 (DPIN0=1, DPIN1=0, DPPHY=0) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: R.4 FIFO_WR_DPTX_CLK_EN = 0x0 (DISPEXT_0_0=0, DISPEXT_0_1=0, DISPEXT_1_0=0, DISPEXT_1_1=0, DISPEXT_2_0=0, DISPEXT_2_1=0, DISPEXT_3_0=0, DISPEXT_3_1=0, DISPEXT_4_0=0) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: W.4 FIFO_WR_DPTX_CLK_EN = 0x1 (DISPEXT_0_0=1, DISPEXT_0_1=0, DISPEXT_1_0=0, DISPEXT_1_1=0, DISPEXT_2_0=0, DISPEXT_2_1=0, DISPEXT_3_0=0, DISPEXT_3_1=0, DISPEXT_4_0=0) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: R.4 FIFO_RD_PCLK1_EN = 0x0 (DISPEXT_0_0=0, DISPEXT_0_1=0, DISPEXT_1_0=0, DISPEXT_1_1=0, DISPEXT_2_0=0, DISPEXT_2_1=0, DISPEXT_3_0=0, DISPEXT_3_1=0, DISPEXT_4_0=0) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: W.4 FIFO_RD_PCLK1_EN = 0x1 (DISPEXT_0_0=1, DISPEXT_0_1=0, DISPEXT_1_0=0, DISPEXT_1_1=0, DISPEXT_2_0=0, DISPEXT_2_1=0, DISPEXT_3_0=0, DISPEXT_3_1=0, DISPEXT_4_0=0) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: R.4 OUT_PCLK1_EN = 0x0 (DISPEXT_0_0=0, DISPEXT_0_1=0, DISPEXT_1_0=0, DISPEXT_1_1=0, DISPEXT_2_0=0, DISPEXT_2_1=0, DISPEXT_3_0=0, DISPEXT_3_1=0, DISPEXT_4_0=0) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: W.4 OUT_PCLK1_EN = 0x1 (DISPEXT_0_0=1, DISPEXT_0_1=0, DISPEXT_1_0=0, DISPEXT_1_1=0, DISPEXT_2_0=0, DISPEXT_2_1=0, DISPEXT_3_0=0, DISPEXT_3_1=0, DISPEXT_4_0=0) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: R.4 CROSSBAR_ATC_EN = 0x0 (DPIN0=0, DPIN1=0, DPPHY=0) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: W.4 CROSSBAR_ATC_EN = 0x1 (DPIN0=1, DPIN1=0, DPPHY=0) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: R.4 CROSSBAR_DISPEXT_EN = 0x0 (DISPEXT_0_0=0, DISPEXT_0_1=0, DISPEXT_1_0=0, DISPEXT_1_1=0, DISPEXT_2_0=0, DISPEXT_2_1=0, DISPEXT_3_0=0, DISPEXT_3_1=0, DISPEXT_4_0=0) | |
# [DisplayCrossbarTracer@/arm-io/atc2-dpxbar] MMIO: W.4 CROSSBAR_DISPEXT_EN = 0x1 (DISPEXT_0_0=1, DISPEXT_0_1=0, DISPEXT_1_0=0, DISPEXT_1_1=0, DISPEXT_2_0=0, DISPEXT_2_1=0, DISPEXT_3_0=0, DISPEXT_3_1=0, DISPEXT_4_0=0) | |
########################################### | |
# TRIED TO ACCESS SYSTEM DISPLAY SETTINGS # | |
########################################### | |
# [cpu6] PMGR R 28e0801d8+0:32 = 0x1f0000ff -> 0x1f0000ff | |
# [cpu6] PMGR W 28e0801d8+0:32 = 0x1f0400ff: Dangerous write | |
# [cpu6] PMGR R 28e0801f0+0:32 = 0x1f0000ff -> 0x1f0000ff | |
# [cpu6] PMGR W 28e0801f0+0:32 = 0x1f0400ff: Dangerous write | |
# [cpu6] PMGR R 28e080200+0:32 = 0x1f0000ff -> 0x1f0000ff | |
# [cpu6] PMGR R 28e080200+0:32 = 0x1f0000ff -> 0x1f0000ff | |
# [cpu6] PMGR W 28e080200+0:32 = 0x1f0400ff: Dangerous write | |
# [cpu6] PMGR R 28e080218+0:32 = 0x1f0000ff -> 0x1f0000ff | |
# [cpu6] PMGR W 28e080218+0:32 = 0x1f0400ff: Dangerous write |
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