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chadmed/t6020-dieX.dtsi Secret

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Mac Mini (M2 Pro, 2023) prototype DTs
Raw
t6020-dieX.dtsi
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Nodes present on both dies of a hypothetical T6022 (M2 Ultra)
* and present on M2 Pro/Max.
*
* Copyright The Asahi Linux Contributors
*/
DIE_NODE(cpufreq_e): cpufreq@210e20000 {
compatible = "apple,t6020-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
reg = <0x2 0x10e20000 0 0x1000>;
#performance-domain-cells = <0>;
};
DIE_NODE(cpufreq_p0): cpufreq@211e20000 {
compatible = "apple,t6020-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
reg = <0x2 0x11e20000 0 0x1000>;
#performance-domain-cells = <0>;
};
DIE_NODE(cpufreq_p1): cpufreq@212e20000 {
compatible = "apple,t6020-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
reg = <0x2 0x12e20000 0 0x1000>;
#performance-domain-cells = <0>;
};
Raw
t6020-j474s.dts
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Mac Mini (M2 Pro, 2023)
*
* target-type: J474s
*
* Copyright The Asahi Linux Contributors
*/
/dts-v1/;
#include "t6020.dtsi"
/ {
compatible = "apple,j474s", "apple,t6020", "apple,arm-platform";
model = "Apple Mac Mini (M2 Pro, 2023)";
aliases {
serial0 = &serial0;
};
chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
stdout-path = "serial0";
framebuffer0: framebuffer@0 {
compatible = "apple,simple-framebuffer", "simple-framebuffer";
reg = <0 0 0 0>; /* to be filled by loader */
status = "disabled";
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* to be filled by loader */
};
memory@10000000000 {
device_type = "memory";
reg = <0x100 0 0x2 0>; /* to be filled by loader */
};
};
&serial0 {
status = "okay";
};
Raw
t6020.dtsi
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Apple T6020 "M2 Pro" SoC
*
* Other names: H14
*
* Copyright The Asahi Linux Contributors
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/spmi/spmi.h>
#include "multi-die-cpp.h"
#include "t602x-common.dtsi"
/ {
compatible = "apple,t6020", "apple,arm-platform";
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
uat_handoff: uat-handoff {
reg = <0 0 0 0>;
};
uat_pagetables: uat-pagetables {
reg = <0 0 0 0>;
};
uat_ttbs: uat-ttbs {
reg = <0 0 0 0>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
nonposted-mmio;
/* filled by includes below */
};
};
#define DIE
#define DIE_NO 0
&{/soc} {
#include "t602x-die0.dtsi"
#include "t602x-dieX.dtsi"
#include "t602x-nvme.dtsi"
};
// pmgr and gpio will go here
#undef DIE
#undef DIE_NO
&aic {
affinities {
e-core-pmu-affinity {
apple,fiq-index = <AIC_CPU_PMU_E>;
cpus = <&cpu_e00 &cpu_e01>;
};
p-core-pmu-affinity {
apple,fiq-index = <AIC_CPU_PMU_P>;
cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03
&cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13>;
};
};
};
Raw
t602x-common.dtsi
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Nodes common to all T602x family SoCs (M2 Pro/Max/Ultra)
*
* Copyright The Asahi Linux Contributors
*/
/ {
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu_e00>;
};
core1 {
cpu = <&cpu_e01>;
};
core2 {
cpu = <&cpu_e02>;
};
core3 {
cpu = <&cpu_e03>;
};
};
cluster1 {
core0 {
cpu = <&cpu_p00>;
};
core1 {
cpu = <&cpu_p01>;
};
core2 {
cpu = <&cpu_p02>;
};
core3 {
cpu = <&cpu_p03>;
};
};
cluster2 {
core0 {
cpu = <&cpu_p10>;
};
core1 {
cpu = <&cpu_p11>;
};
core2 {
cpu = <&cpu_p12>;
};
core3 {
cpu = <&cpu_p13>;
};
};
};
cpu_e00: cpu@0 {
compatible = "apple,blizzard";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* to be filled by loader */
next-level-cache = <&l2_cache_0>;
i-cache-size = <0x20000>;
d-cache-size = <0x10000>;
operating-points-v2 = <&blizzard_opp>;
// TODO: capacity-dmips-mhz = <>
performance_domains = <&cpufreq_e>;
};
cpu_e01: cpu@1 {
compatible = "apple,blizzard";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* to be filled by loader */
next-level-cache = <&l2_cache_0>;
i-cache-size = <0x20000>;
d-cache-size = <0x10000>;
operating-points-v2 = <&blizzard_opp>;
// TODO: capacity-dmips-mhz = <>
performance_domains = <&cpufreq_e>;
};
cpu_e02: cpu@2 {
compatible = "apple,blizzard";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* to be filled by loader */
next-level-cache = <&l2_cache_0>;
i-cache-size = <0x20000>;
d-cache-size = <0x10000>;
operating-points-v2 = <&blizzard_opp>;
// TODO: capacity-dmips-mhz = <>
performance_domains = <&cpufreq_e>;
};
cpu_e03: cpu@3 {
compatible = "apple,blizzard";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* to be filled by loader */
next-level-cache = <&l2_cache_0>;
i-cache-size = <0x20000>;
d-cache-size = <0x10000>;
operating-points-v2 = <&blizzard_opp>;
// TODO: capacity-dmips-mhz = <>
performance_domains = <&cpufreq_e>;
};
cpu_p00: cpu@10100 {
compatible = "apple,avalanche";
device_type = "cpu";
reg = <0x0 0x10100>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
next-level-cache = <&l2_cache_1>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
operating-points-v2 = <&avalanche_opp>;
// TODO: capacity-dmips-mhz = <>;
performance-domains = <&cpufreq_p0>;
};
cpu_p01: cpu@10101 {
compatible = "apple,avalanche";
device_type = "cpu";
reg = <0x0 0x10101>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
next-level-cache = <&l2_cache_1>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
operating-points-v2 = <&avalanche_opp>;
// TODO: capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p0>;
};
cpu_p02: cpu@10102 {
compatible = "apple,avalanche";
device_type = "cpu";
reg = <0x0 0x10102>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
next-level-cache = <&l2_cache_1>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
operating-points-v2 = <&avalanche_opp>;
// TODO: capacity-dmips-mhz = <>;
performance-domains = <&cpufreq_p0>;
};
cpu_p03: cpu@10103 {
compatible = "apple,avalanche";
device_type = "cpu";
reg = <0x0 0x10103>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
next-level-cache = <&l2_cache_1>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
operating-points-v2 = <&avalanche_opp>;
// TODO: capacity-dmips-mhz = <>;
performance-domains = <&cpufreq_p0>;
};
cpu_p10: cpu@10200 {
compatible = "apple,avalanche";
device_type = "cpu";
reg = <0x0 0x10200>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
next-level-cache = <&l2_cache_2>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
operating-points-v2 = <&avalanche_opp>;
// TODO: capacity-dmips-mhz = <>;
performance-domains = <&cpufreq_p1>;
};
cpu_p11: cpu@10201 {
compatible = "apple,avalanche";
device_type = "cpu";
reg = <0x0 0x10201>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
next-level-cache = <&l2_cache_2>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
operating-points-v2 = <&avalanche_opp>;
// TODO: capacity-dmips-mhz = <>;
performance-domains = <&cpufreq_p1>;
};
cpu_p12: cpu@10202 {
compatible = "apple,avalanche";
device_type = "cpu";
reg = <0x0 0x10202>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
next-level-cache = <&l2_cache_2>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
operating-points-v2 = <&avalanche_opp>;
// TODO: capacity-dmips-mhz = <>;
performance-domains = <&cpufreq_p1>;
};
cpu_p13: cpu@10203 {
compatible = "apple,avalanche";
device_type = "cpu";
reg = <0x0 0x10203>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
next-level-cache = <&l2_cache_2>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
operating-points-v2 = <&avalanche_opp>;
// TODO: capacity-dmips-mhz = <>;
performance-domains = <&cpufreq_p1>;
};
l2_cache_0: l2-cache-0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x400000>;
};
l2_cache_1: l2-cache-1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x1000000>;
};
l2_cache_2: l2-cache-2 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x1000000>;
};
};
blizzard_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp01 {
opp-hz = /bits/ 64 <600000000>;
opp-level = <1>;
clock-latency-ns = <7792>;
};
opp02 {
opp-hz = /bits/ 64 <912000000>;
opp-level = <2>;
clock-latency-ns = <7667>;
};
opp03 {
opp-hz = /bits/ 64 <1284000000>;
opp-level = <3>;
clock-latency-ns = <23865>;
};
opp04 {
opp-hz = /bits/ 64 <1752000000>;
opp-level = <4>;
clock-latency-ns = <31292>;
};
opp05 {
opp-hz = /bits/ 64 <2004000000>;
opp-level = <5>;
clock-latency-ns = <37500>;
};
opp06 {
opp-hz = /bits/ 64 <2256000000>;
opp-level = <6>;
clock-latency-ns = <42833>;
};
opp07 {
opp-hz = /bits/ 64 <2424000000>;
opp-level = <7>;
clock-latency-ns = <46708>;
};
};
avalanche_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
opp01 {
opp-hz = /bits/ 64 <702000000>;
opp-level = <1>;
clock-latency-ns = <6625>;
};
opp02 {
opp-hz = /bits/ 64 <948000000>;
opp-level = <2>;
clock-latency-ns = <6875>;
};
opp03 {
opp-hz = /bits/ 64 <1188000000>;
opp-level = <3>;
clock-latency-ns = <20708>;
};
opp04 {
opp-hz = /bits/ 64 <1452000000>;
opp-level = <4>;
clock-latency-ns = <23083>;
};
opp05 {
opp-hz = /bits/ 64 <1704000000>;
opp-level = <5>;
clock-latency-ns = <27458>;
};
opp06 {
opp-hz = /bits/ 64 <1968000000>;
opp-level = <6>;
clock-latency-ns = <30458>;
};
opp07 {
opp-hz = /bits/ 64 <2208000000>;
opp-level = <7>;
clock-latency-ns = <42833>;
};
opp08 {
opp-hz = /bits/ 64 <2400000000>;
opp-level = <8>;
clock-latency-ns = <44542>;
};
opp09 {
opp-hz = /bits/ 64 <2568000000>;
opp-level = <9>;
clock-latency-ns = <46042>;
};
opp10 {
opp-hz = /bits/ 64 <2724000000>;
opp-level = <10>;
clock-latency-ns = <49208>;
};
opp11 {
opp-hz = /bits/ 64 <2868000000>;
opp-level = <11>;
clock-latency-ns = <51708>;
};
opp12 {
opp-hz = /bits/ 64 <3000000000>;
opp-level = <12>;
clock-latency-ns = <56292>;
};
opp13 {
opp-hz = /bits/ 64 <3132000000>;
opp-level = <13>;
clock-latency-ns = <58917>;
};
opp14 {
opp-hz = /bits/ 64 <3264000000>;
opp-level = <14>;
clock-latency-ns = <63125>;
};
/* Not available until CPU deep sleep is implemented */
#if 0
opp15 {
opp-hz = /bits/ 64 <3360000000>;
opp-level = <15>;
clock-latency-ns = <63292>;
turbo-mode;
};
opp16 {
opp-hz = /bits/ 64 <3408000000>;
opp-level = <16>;
clock-latency-ns = <63375>;
turbo-mode;
};
opp17 {
opp-hz = /bits/ 64 <3504000000>;
opp-level = <17>;
clock-latency-ns = <63375>;
turbo-mode;
};
#endif
};
pmu-e {
compatible = "apple,blizard-pmu";
interrupt-parent = <&aic>;
interrupts = <AIC_FIQ 0 AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
};
pmu-p {
compatible = "apple,avalanche-pmu";
interrupt-parent = <&aic>;
interrupts = <AIC_FIQ 0 AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&aic>;
interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
interrupts = <AIC_FIQ 0 AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
<AIC_FIQ 0 AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
<AIC_FIQ 0 AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
<AIC_FIQ 0 AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
};
clkref: clock-ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "clkref";
};
clk_200m: clock-200m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
clock-output-names = "clk_200m";
};
/*
* This is a fabulated representation of the input clock
* to NCO since we don't know the true clock tree.
*/
nco_clkref: clock-ref-nco {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "nco_ref";
};
};
Raw
t602x-die0.dtsi
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* In anticipation of an M2 Ultra. Inspired by T600x.
*
* Obviously needs filling out, just the bare bones required
* to boot to a console in the HV.
*
* Copyright The Asahi Linux Contributors
*/
nco: clock-controller@28e03c000 {
compatible = "apple,t6020-nco", "apple,nco";
reg = <0x2 0x8e03c000 0x0 0x14000>;
clocks = <&nco_clkref>;
#clock-cells = <1>;
};
aic: interrupt-controller@28e100000 {
compatible = "apple,t6020-aic", "apple,aic2";
#interrupt-cells = <4>;
interrupt-controller;
reg = <0x2 0x8e100000 0x0 0xc000>,
<0x2 0x8e148000 0x0 0x1000>;
reg-names = "core", "event";
//power-domains = <&ps_aic>;
};
wdt: watchdog@29e2c4000 {
compatible = "apple,t6020-wdt", "apple,wdt";
reg = <0x2 0x9e2c4000 0x0 0x4000>;
clocks = <&clkref>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 0 719 IRQ_TYPE_LEVEL_HIGH>;
};
serial0: serial@39b200000 {
compatible = "apple,s5l-uart";
reg = <0x3 0x9b200000 0x0 0x4000>;
reg-io-width = <4>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 0 1198 IRQ_TYPE_LEVEL_HIGH>;
/*
* TODO: figure out the clocking properly, there may
* be a third selectable clock.
*/
clocks = <&clkref>, <&clkref>;
clock-names = "uart", "clk_uart_baud0";
//power-domains = <&ps_uart0>;
status = "disabled";
};
Raw
t602x-nvme.dtsi
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* NVMe related devices for Apple T602x SoCs.
*
* Preliminary info based on J474s ADT. Could be wrong, not sure
* with this one.
*
* Copyright The Asahi Linux Contributors
*/
DIE_NODE(ans_mbox): mbox@347050000 {
compatible = "apple,t6020-asc-mailbox", "apple,asc-mailbox-v4";
reg = <0x3 0x47050000 0x0 0x4000>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ DIE_NO 1169 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ DIE_NO 1170 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ DIE_NO 1171 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ DIE_NO 1172 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "send-empty", "send-not-empty",
"recv-empty", "recv-not-empty";
//power-domains = <&DIE_NODE(ps_ans2)>;
#mbox-cells = <0>;
};
DIE_NODE(sart): sart@34bc50000 {
compatible = "apple,t6020-sart", "apple,t6000-sart", "apple,sart";
reg = <0x3 0x4bc50000 0x0 0x10000>;
//power-domains = <&DIE_NODE(ps_ans2)>;
};
DIE_NODE(nvme): nvme@34bd47c00 {
compatible = "apple,t6020-nvme-ans2", "apple,nvme-ans2";
reg = <0x3 0x4bd47c00 0x0 0x40000>, <0x3 0x8f400000 0x0 0x4000>;
reg-names = "nvme", "ans";
interrupt-parent = <&aic>;
/* The NVME interrupt is always routed to die */
interrupts = <AIC_IRQ 0 1832 IRQ_TYPE_LEVEL_HIGH>;
mboxes = <&DIE_NODE(ans_mbox)>;
apple,sart = <&DIE_NODE(sart)>;
//power-domains = <&DIE_NODE(ps_ans2)>,
// <&DIE_NODE(ps_apcie_st_sys)>,
// <&DIE_NODE(ps_apcie_st1_sys)>;
//power-domain-names = "ans", "apcie0", "apcie1";
//resets = <&DIE_NODE(ps_ans2)>;
};
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