Created
September 27, 2021 06:10
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Intel(R) Xeon(R) Gold 6126 CPU @ 2.60GHz
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Processor [Intel(R) Xeon(R) Gold 6126 CPU @ 2.60GHz] | |
|- PPIN# [243ee2da688a964b] | |
|- Architecture [Skylake/X] | |
|- Vendor ID [GenuineIntel] | |
|- Microcode [0x02006b06] | |
|- Signature [ 06_55] | |
|- Stepping [ 4] | |
|- Online CPU [ 48/ 48] | |
|- Base Clock [ 99.766] | |
|- Frequency (MHz) Ratio | |
Min 997.66 < 10 > | |
Max 2593.90 < 26 > | |
|- Factory [100.000] | |
2600 [ 26 ] | |
|- Performance | |
|- P-State | |
TGT 3691.33 < 37 > | |
|- Turbo Boost [ UNLOCK] | |
1C 3691.33 < 37 > | |
2C 3491.79 < 35 > | |
3C 3392.03 < 34 > | |
4C 3292.26 < 33 > | |
5C 3292.26 < 33 > | |
6C 3292.26 < 33 > | |
7C 3292.26 < 33 > | |
8C 3292.26 < 33 > | |
9C 199.53 < 2 > | |
10C 399.06 < 4 > | |
11C 798.12 < 8 > | |
12C 1197.19 < 12 > | |
13C 1596.25 < 16 > | |
14C 1995.31 < 20 > | |
15C 2394.37 < 24 > | |
16C 2793.44 < 28 > | |
|- Uncore [ UNLOCK] | |
Min 2394.37 < 24 > | |
Max 2394.37 < 24 > | |
|- TDP Level [ 0:2 ] | |
|- Programmable [ UNLOCK] | |
|- Configuration [ LOCK] | |
|- Turbo Activation [ UNLOCK] | |
Nominal 2593.90 [ 26 ] | |
Level1 1696.01 [ 17 ] | |
Level2 1696.01 [ 17 ] | |
Turbo AUTO < 255 > | |
Instruction Set Extensions | |
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y] | |
|- AVX512-F [Y] AVX512-DQ [Y] AVX512-IFMA [N] AVX512-PF [N] | |
|- AVX512-ER [N] AVX512-CD [Y] AVX512-BW [Y] AVX512-VL [Y] | |
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNMI [N] AVX512-ALG [N] | |
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N] | |
|- AVX512-BF16 [N] BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH/O [Y/Y] | |
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y] | |
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y] | |
|- MMX/Ext [Y/N] MON/MWAITX [Y/N] MOVBE [Y] PCLMULQDQ [Y] | |
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y] | |
|- SEP [Y] SHA [N] SSE [Y] SSE2 [Y] | |
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y] | |
|- SERIALIZE [N] SYSCALL [Y] SGX [N] RDPID [N] | |
Features | |
|- 1 GB Pages Support 1GB-PAGES [Capable] | |
|- Advanced Configuration & Power Interface ACPI [Capable] | |
|- Advanced Programmable Interrupt Controller APIC [Capable] | |
|- Core Multi-Processing CMP Legacy [Missing] | |
|- L1 Data Cache Context ID CNXT-ID [Missing] | |
|- Direct Cache Access DCA [Capable] | |
|- Debugging Extension DE [Capable] | |
|- Debug Store & Precise Event Based Sampling DS, PEBS [Capable] | |
|- CPL Qualified Debug Store DS-CPL [Capable] | |
|- 64-Bit Debug Store DTES64 [Capable] | |
|- Fast-String Operation Fast-Strings [Capable] | |
|- Fused Multiply Add FMA | FMA4 [Capable] | |
|- Hardware Lock Elision HLE [Capable] | |
|- Instruction Based Sampling IBS [Missing] | |
|- Long Mode 64 bits IA64 | LM [Capable] | |
|- LightWeight Profiling LWP [Missing] | |
|- Machine-Check Architecture MCA [Capable] | |
|- Memory Protection Extensions MPX [Capable] | |
|- Model Specific Registers MSR [Capable] | |
|- Memory Type Range Registers MTRR [Capable] | |
|- OS-Enabled Ext. State Management OSXSAVE [Capable] | |
|- Physical Address Extension PAE [Capable] | |
|- Page Attribute Table PAT [Capable] | |
|- Pending Break Enable PBE [Capable] | |
|- Process Context Identifiers PCID [Capable] | |
|- Perfmon and Debug Capability PDCM [Capable] | |
|- Page Global Enable PGE [Capable] | |
|- Page Size Extension PSE [Capable] | |
|- 36-bit Page Size Extension PSE36 [Capable] | |
|- Processor Serial Number PSN [Missing] | |
|- Resource Director Technology/PQE RDT-A [Capable] | |
|- Resource Director Technology/PQM RDT-M [Capable] | |
|- Restricted Transactional Memory RTM [Capable] | |
|- Safer Mode Extensions SMX [Capable] | |
|- Self-Snoop SS [Capable] | |
|- Supervisor-Mode Access Prevention SMAP [Capable] | |
|- Supervisor-Mode Execution Prevention SMEP [Capable] | |
|- Time Stamp Counter TSC [Invariant] | |
|- Time Stamp Counter Deadline TSC-DEADLINE [Capable] | |
|- TSX Force Abort MSR Register TSX-ABORT [Capable] | |
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing] | |
|- User-Mode Instruction Prevention UMIP [Missing] | |
|- Virtual Mode Extension VME [Capable] | |
|- Virtual Machine Extensions VMX [Capable] | |
|- Extended xAPIC Support x2APIC [ x2APIC] | |
|- Execution Disable Bit Support XD-Bit [Capable] | |
|- XSAVE/XSTOR States XSAVE [Capable] | |
|- xTPR Update Control xTPR [Capable] | |
Mitigation mechanisms | |
|- Indirect Branch Restricted Speculation IBRS [Capable] | |
|- Indirect Branch Prediction Barrier IBPB [Capable] | |
|- Single Thread Indirect Branch Predictor STIBP [Capable] | |
|- Speculative Store Bypass Disable SSBD [Capable] | |
|- Writeback & invalidate the L1 data cache L1D-FLUSH [Capable] | |
|- Hypervisor - No flush L1D on VM entry L1DFL_VMENTRY_NO [Missing] | |
|- Architectural - Buffer Overwriting MD-CLEAR [Capable] | |
|- Architectural - Rogue Data Cache Load RDCL_NO [Missing] | |
|- Architectural - Enhanced IBRS IBRS_ALL [Missing] | |
|- Architectural - Return Stack Buffer Alternate RSBA [Missing] | |
|- Architectural - Speculative Store Bypass SSB_NO [Missing] | |
|- Architectural - Microarchitectural Data Sampling MDS_NO [Missing] | |
|- Architectural - TSX Asynchronous Abort TAA_NO [Missing] | |
|- Architectural - Page Size Change MCE PSCHANGE_MC_NO [Missing] | |
|- Architectural - STLB QoS STLB [Missing] | |
|- Architectural - Functional Safety Island FuSa [Missing] | |
|- Architectural - RSM in CPL0 only RSM [Missing] | |
|- Architectural - Split Locked Access Exception SPLA [Missing] | |
|- Architectural - Snoop Filter QoS Mask SNOOP_FILTER [Missing] | |
Technologies | |
|- Data Cache Unit | |
|- L1 Prefetcher L1 HW < ON> | |
|- L1 IP Prefetcher L1 HW IP < ON> | |
|- L2 Prefetcher L2 HW < ON> | |
|- L2 Line Prefetcher L2 HW CL < ON> | |
|- System Management Mode SMM-Dual [ ON] | |
|- Hyper-Threading HTT [ ON] | |
|- SpeedStep EIST < ON> | |
|- Dynamic Acceleration IDA [ ON] | |
|- Turbo Boost TURBO < ON> | |
|- Energy Efficiency Optimization EEO <OFF> | |
|- Race To Halt Optimization R2H <OFF> | |
|- Watchdog Timer TCO < ON> | |
|- Virtualization VMX [ ON] | |
|- I/O MMU VT-d [OFF] | |
|- Version [ N/A] | |
|- Hypervisor [OFF] | |
|- Vendor ID [ N/A] | |
Performance Monitoring | |
|- Version PM [ 4] | |
|- Counters: General Fixed | |
| 4 x 48 bits 3 x 48 bits | |
|- Enhanced Halt State C1E <OFF> | |
|- C1 Auto Demotion C1A <OFF> | |
|- C3 Auto Demotion C3A <OFF> | |
|- C1 UnDemotion C1U <OFF> | |
|- C3 UnDemotion C3U <OFF> | |
|- C6 Core Demotion CC6 <OFF> | |
|- C6 Module Demotion MC6 <OFF> | |
|- Legacy Frequency ID control FID [OFF] | |
|- Legacy Voltage ID control VID [OFF] | |
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON] | |
|- Hardware-Controlled Performance States HWP [OFF] | |
|- Hardware Duty Cycling HDC [OFF] | |
|- Package C-States | |
|- Configuration Control CONFIG [ LOCK] | |
|- Lowest C-State LIMIT < C0> | |
|- I/O MWAIT Redirection IOMWAIT < Enable> | |
|- Max C-State Inclusion RANGE < C0> | |
|- Core C-States | |
|- C-States Base Address BAR [ 0x514 ] | |
|- MONITOR/MWAIT | |
|- State index: #0 #1 #2 #3 #4 #5 #6 #7 | |
|- Sub C-State: 0 2 0 2 0 0 0 0 | |
|- Core Cycles [Capable] | |
|- Instructions Retired [Capable] | |
|- Reference Cycles [Capable] | |
|- Last Level Cache References [Capable] | |
|- Last Level Cache Misses [Capable] | |
|- Branch Instructions Retired [Capable] | |
|- Branch Mispredicts Retired [Capable] | |
|- Top-down slots Counter [Capable] | |
Power, Current & Thermal | |
|- Clock Modulation ODCM <Disable> | |
|- DutyCycle [ 0.00%] | |
|- Power Management PWR MGMT [ LOCK] | |
|- Energy Policy Bias Hint < 6> | |
|- Energy Policy HWP EPP [ 0] | |
|- Junction Temperature TjMax [ 0:100C] | |
|- Digital Thermal Sensor DTS [Capable] | |
|- Power Limit Notification PLN [Capable] | |
|- Package Thermal Management PTM [Capable] | |
|- Thermal Monitor 1 TM1 [ Enable] | |
|- Thermal Monitor 2 TM2 [Capable] | |
|- Thermal Design Power TDP [ 125 W] | |
|- Minimum Power Min [ 65 W] | |
|- Maximum Power Max [ 264 W] | |
|- Thermal Design Power Package < Enable> | |
|- Power Limit (1 sec) PL1 < 125 W> | |
|- Power Limit (1 sec) PL2 < 150 W> | |
|- Thermal Design Power Core <Disable> | |
|- Power Limit PL1 [Missing] | |
|- Thermal Design Power Uncore <Disable> | |
|- Power Limit PL1 [Missing] | |
|- Thermal Design Power DRAM <Disable> | |
|- Power Limit PL1 [Missing] | |
|- Thermal Design Power Platform <Disable> | |
|- Power Limit PL1 [Missing] | |
|- Power Limit PL2 [Missing] | |
|- Electrical Design Current EDC [Missing] | |
|- Thermal Design Current TDC [Missing] | |
|- Units | |
|- Power watt [ 0.125000000] | |
|- Energy joule [ 0.000061035] | |
|- Window second [ 0.000976562] |
Author
chenkaigithub
commented
Sep 27, 2021
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