Created
April 21, 2020 16:47
-
-
Save chipmuenk/ca8d3aa40c40d2b09bd51b989815bfac to your computer and use it in GitHub Desktop.
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
from nmigen import * | |
from nmigen.cli import main | |
class Blinky(Elaboratable): | |
def __init__(self): | |
self.led = Signal() | |
def elaborate(self, platform): | |
m = Module() | |
counter = Signal(3) | |
m.d.sync += counter.eq(counter + 1) | |
m.d.comb += self.led.eq(counter[0]) | |
return m | |
if __name__ == "__main__": | |
top = Blinky() | |
main(top, ports=(top.led)) |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
This piece of code should generate verilog code when called with
python blinky.py generate
(with our N00b background) but it generates the error message
TypeError: Only signals may be added as ports, not (slice (sig led) 0:1)
I guess we're doing something wrong on a very basic level ... but I have no idea what.