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@chipmuenk
Created April 21, 2020 16:47
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from nmigen import *
from nmigen.cli import main
class Blinky(Elaboratable):
def __init__(self):
self.led = Signal()
def elaborate(self, platform):
m = Module()
counter = Signal(3)
m.d.sync += counter.eq(counter + 1)
m.d.comb += self.led.eq(counter[0])
return m
if __name__ == "__main__":
top = Blinky()
main(top, ports=(top.led))
@chipmuenk
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This piece of code should generate verilog code when called with

python blinky.py generate

(with our N00b background) but it generates the error message

TypeError: Only signals may be added as ports, not (slice (sig led) 0:1)

I guess we're doing something wrong on a very basic level ... but I have no idea what.

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