Skip to content

Instantly share code, notes, and snippets.

@christiaanb
Created April 12, 2017 21:20
Show Gist options
  • Save christiaanb/464ed5e3f6cd9b89a0ec5760293d078e to your computer and use it in GitHub Desktop.
Save christiaanb/464ed5e3f6cd9b89a0ec5760293d078e to your computer and use it in GitHub Desktop.
module UART where
import CLaSH.Prelude
import qualified Data.List as L
type Byte = Unsigned 8
data TxState
= TxIdle
| TxStart (Unsigned 8)
| TxSending (Unsigned 8) (Index 8)
| TxDone
deriving (Eq, Show, Ord)
uartTxT TxIdle Nothing = (TxIdle , (high , False))
uartTxT TxIdle (Just b) = (TxStart b , (low , False))
uartTxT (TxStart b) _ = (TxSending b 0, (lsb b, False))
uartTxT (TxSending b off) _
| off == 7 = (TxDone , (high , False))
| otherwise = (TxSending b' off', (lsb b', False))
where b' = b `shiftR` 1
off' = off + 1
uartTxT TxDone _ = (TxIdle, (high, True))
mealyEn f iS en = \i -> let s = regEn iS en s'
(s',o) = unbundle (f <$> s <*> i)
in o
uartTx :: Signal Bool -> Signal (Maybe Byte) -> Signal (Bit, Bool)
uartTx en x = bundle (register high out,finished .&&. en)
where (out,finished) = unbundle (mealyEn uartTxT TxIdle en x)
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment