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christian-lanius / random_delay_write.sv
Created September 20, 2023 10:50
This gist shows an example for why an "accept" as an optional feature would be nice to have in the airhdl generated register files. It would connect to a register file which implements a memory field. Read is just included for completeness. A testbench for how I would imagine the output of the register file to look is also included.
module tb;
logic clk_axi;
initial begin
clk_axi = 1'd0;
forever begin
clk_axi <= !clk_axi;
#(800ps/2.0);
end
end
# ==================================================================
# module list
# ------------------------------------------------------------------
# python 3.5 (apt)
# tensorflow latest (pip)
# opencv latest (git)
# caffe latest (git)
# openpose latest (git)
# pyopenpose latest (git)
# custom_dependencies latest (apt)