"Trammell Mode" RGB blink pattern for UPDuino v2.0

blink.v

/******************************************************************************
*                                                                             *
* Copyright 2016 myStorm Copyright and related                                *
* rights are licensed under the Solderpad Hardware License, Version 0.51      *
* (the “License”); you may not use this file except in compliance with        *
* the License. You may obtain a copy of the License at                        *
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable       *
* law or agreed to in writing, software, hardware and materials               *
* distributed under this License is distributed on an “AS IS” BASIS,          *
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or             *
* implied. See the License for the specific language governing                *
* permissions and limitations under the License.                              *
*                                                                             *
******************************************************************************/

module blink(
    input clk,
    input rst,
    output led_r,
    output led_g,
    output led_b
);
        reg [1:0] state;

        reg [26:0] count;

        reg [2:0] leds;

        reg pwm_state;

        wire [7:0] correction;

        assign led_r = !leds[0];
        assign led_g = !leds[1];
        assign led_b = !leds[2];

        correction_lut corrector (
            .value(count[25:18]),
            .corrected(correction)
        );

        always @(posedge clk)
            if(rst) begin
                count = 0;
                state = 0;
            end
            else begin
                pwm_state = 0;
                leds = 0;

                count = count + 1;

                if(count[26] == 0) begin
                    //if(count[25:18] > count[7:0])
                    if(correction > count[7:0])
                        pwm_state = 1;
                end
                else begin
                    if(correction < count[7:0])
                        pwm_state = 1;
                end

                if(count == 0)
                    state = state + 1;

                case(state)
                0:
                    leds[0] <= pwm_state;
                1:
                    leds[1] <= pwm_state;
                2:
                    leds[2] <= pwm_state;
                3:
                    begin
                        leds[0] <= pwm_state;
                        leds[1] <= pwm_state;
                        leds[2] <= pwm_state;
                    end

                endcase
            end

endmodule

chip.v

module chip (
        output  LED_R,
        output  LED_G,
        output  LED_B
        );

        wire clk, led_r, led_g, led_b;

        SB_HFOSC u_hfosc (
                .CLKHFPU(1'b1),
                .CLKHFEN(1'b1),
                .CLKHF(clk)
        );

        blink my_blink (
                .clk(clk),
                .rst(0),
                .led_r(led_r),
                .led_g(led_g),
                .led_b(led_b)
        );

        assign LED_R = led_r;
        assign LED_G = led_b;
        assign LED_B = led_g;

endmodule
~                     

lut_gen.py

'''
module lut(count_out, angle); 

input [2:0] count_out; 
output [11:0] angle; 
reg [11:0] angle; 

always @(count_out) 

case (count_out) 

3'b000: angle=12'b001000000000; //0 45 45 
3'b001: angle=12'b000100101110; //1 26.54 26.57 
3'b010: angle=12'b000010100000; //2 14.06 14.036 
3'b011: angle=12'b000001010001; //3 7.12 7.13 
3'b100: angle=12'b000000101001; //4 3.604 3.576 
3'b101: angle=12'b000000010100; //5 1.76 1.79 
3'b110: angle=12'b000000001010; //6 0.88 0.9 
3'b111: angle=12'b000000000101; //7 0.44 0.45 
default: angle=12'b001000000000; //default 0 

endcase 

endmodule
'''

header = '''
module correction_lut(value, corrected); 

input [7:0] value; 
output [7:0] corrected; 
reg [7:0] corrected; 

always @(value) 

case (value) 
'''

footer = '''

endcase 

endmodule

'''


out = open('correction_lut.v','w')

out.write(header)

for val in range(0,256):
    out.write("%i: corrected=%i;\n" % (val,int(255*pow(val/255.0,1.8))))

out.write(footer)

Makefile

chip.bin: chip.v blink.v upduino_v2.pcf
        yosys -q -p "synth_ice40 -blif chip.blif" chip.v blink.v correction_lut.v
        arachne-pnr -d 5k -P sg48 -p upduino_v2.pcf chip.blif -o chip.txt
        icepack chip.txt chip.bin

.PHONY: flash
flash:
        iceprog chip.bin

.PHONY: clean
clean:
        $(RM) -f chip.blif chip.txt chip.ex chip.bin

upduino_v2.pcf

t_io LED_R    41
set_io LED_G    40
set_io LED_B    39