cirosantilli2/README.md

## README.md

      
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    ./run -aA -eg -N1 --linux-exec /home/ciro/bak/git/linux-kernel-module-cheat/out/gem5/test_binaries/binaries/vmlinux.arm64 --cpus 8 --trace FmtFlag,CacheAll,DRAM,ExecAll,Event,XBar --G=--debug-start=7306449500 -- --cpu-type DerivO3CPU --caches --l2cache 

gem5 3ca404da175a66e0b958165ad75eb5f54cb5e772 full CLI:
+ M5_OVERRIDE_PY_SOURCE=true \
  rr record /home/ciro/bak/git/linux-kernel-module-cheat/out/gem5/1/build/ARM/gem5.debug \
  --debug-file trace.txt \
  --listener-mode on \
  --outdir /home/ciro/bak/git/linux-kernel-module-cheat/out/run/gem5/aarch64/0/m5out \
  --debug-flags FmtFlag,ExecAll,Cache,DRAM,Event \
  /home/ciro/bak/git/linux-kernel-module-cheat/data/gem5/1/configs/example/fs.py \
  --kernel /home/ciro/bak/git/linux-kernel-module-cheat/out/gem5/test_binaries/binaries/vmlinux.arm64 \
  --num-cpus 8 \
  --script /home/ciro/bak/git/linux-kernel-module-cheat/out/run/gem5/aarch64/0/readfile \
  --disk-image /home/ciro/bak/git/linux-kernel-module-cheat/out/buildroot/build/default/aarch64/images/rootfs.ext2 \
  --machine-type VExpress_GEM5_V1 \
  --command-line 'earlyprintk=pl011,0x1c090000 lpj=19988480 rw loglevel=8 mem=256MB root=/dev/sda console_msg_format=syslog nokaslr norandmaps panic=-1 printk.devkmsg=on printk.time=y rw console=ttyAMA0 - lkmc_home=/lkmc' \
  --param 'system.workload.panic_on_panic = True' \
  --bootloader /home/ciro/bak/git/linux-kernel-module-cheat/out/gem5/1/system/binaries/boot.arm64 \
  --mem-size 256MB \
  --cpu-type DerivO3CPU --caches --l2cache \
;

Reproduces error:
panic: panic condition (pkt->needsWritable() != pkt->isInvalidate()) && !pkt->req->isCacheMaintenance() occurred: global got snoop WriteReq [80a70800:80a70803] UC D=110e0000 where needsWritable, does not match isInvalidate

Panic comes from:
bool
MSHR::handleSnoop(PacketPtr pkt, Counter _order)
{
    DPRINTF(Cache, "%s for %s\n", __func__, pkt->print());

    // when we snoop packets the needsWritable and isInvalidate flags
    // should always be the same, however, this assumes that we never
    // snoop writes as they are currently not marked as invalidations
    panic_if((pkt->needsWritable() != pkt->isInvalidate()) &&
             !pkt->req->isCacheMaintenance(),

GDB values:
>>> p pkt->needsWritable()
$1 = true
>>> p pkt->isInvalidate()
$2 = false

Backtrace to it:
MSHR::handleSnoop(Packet*, long)+0xaa0)[0x5568a52a6920]
Cache::recvTimingSnoopReq(Packet*)+0x293)[0x5568a529a7e3]
CoherentXBar::forwardTiming(Packet*, short, std::vector<QueuedSlavePort*, std::allocator<QueuedSlavePort*> > const&)+0xbc)[0x5568a69e6efc]
CoherentXBar::recvTimingReq(Packet*, short)+0xde9)[0x5568a69eab79]
BaseCache::sendWriteQueuePacket(WriteQueueEntry*)+0x24e)[0x5568a529325e]
BaseCache::CacheReqPacketQueue::sendDeferredPacket()+0xd9)[0x5568a5286709]
EventQueue::serviceOne()+0xb9)[0x5568a6d04e09]
doSimLoop(EventQueue*)+0xf8)[0x5568a6d25d18]
simulate(unsigned long)+0xaed)[0x5568a6d26b0d]

Code snippets from backtrace:
void
Cache::recvTimingSnoopReq(PacketPtr pkt)
{
    DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print());
    ...
    if (mshr && mshr->handleSnoop(pkt, order++)) {

void
CoherentXBar::forwardTiming(PacketPtr pkt, PortID exclude_slave_port_id,
                           const std::vector<QueuedSlavePort*>& dests)
{
    DPRINTF(CoherentXBar, "%s for %s\n", __func__, pkt->print());

    // snoops should only happen if the system isn't bypassing caches
    assert(!system->bypassCaches());

    unsigned fanout = 0;

    for (const auto& p: dests) {
        // we could have gotten this request from a snooping master
        // (corresponding to our own slave port that is also in
        // snoopPorts) and should not send it back to where it came
        // from
        if (exclude_slave_port_id == InvalidPortID ||
            p->getId() != exclude_slave_port_id) {
            // cache is not allowed to refuse snoop
            p->sendTimingSnoopReq(pkt);
            fanout++;
        }
    }

    // Stats for fanout of this forward operation
    snoopFanout.sample(fanout);
}

CoherentXBar::recvTimingReq(PacketPtr pkt, PortID slave_port_id)
{

    ....

    const bool is_destination = isDestination(pkt);

    const bool snoop_caches = !system->bypassCaches() &&
        pkt->cmd != MemCmd::WriteClean;
    if (snoop_caches) {
        assert(pkt->snoopDelay == 0);

        if (pkt->isClean() && !is_destination) {
            // before snooping we need to make sure that the memory
            // below is not busy and the cache clean request can be
            // forwarded to it
            if (!masterPorts[master_port_id]->tryTiming(pkt)) {
                DPRINTF(CoherentXBar, "%s: src %s packet %s RETRY\n", __func__,
                        src_port->name(), pkt->print());

                // update the layer state and schedule an idle event
                reqLayers[master_port_id]->failedTiming(src_port,
                                                        clockEdge(Cycles(1)));
                return false;
            }
        }


        // the packet is a memory-mapped request and should be
        // broadcasted to our snoopers but the source
        if (snoopFilter) {
            // check with the snoop filter where to forward this packet
            auto sf_res = snoopFilter->lookupRequest(pkt, *src_port);
            // the time required by a packet to be delivered through
            // the xbar has to be charged also with to lookup latency
            // of the snoop filter
            pkt->headerDelay += sf_res.second * clockPeriod();
            DPRINTF(CoherentXBar, "%s: src %s packet %s SF size: %i lat: %i\n",
                    __func__, src_port->name(), pkt->print(),
                    sf_res.first.size(), sf_res.second);

            if (pkt->isEviction()) {
                // for block-evicting packets, i.e. writebacks and
                // clean evictions, there is no need to snoop up, as
                // all we do is determine if the block is cached or
                // not, instead just set it here based on the snoop
                // filter result
                if (!sf_res.first.empty())
                    pkt->setBlockCached();
            } else {
                forwardTiming(pkt, slave_port_id, sf_res.first);
            }
        } else {
            forwardTiming(pkt, slave_port_id);
        }

bool
BaseCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry)
{
    assert(wq_entry);

    // always a single target for write queue entries
    PacketPtr tgt_pkt = wq_entry->getTarget()->pkt;

    DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print());

    // forward as is, both for evictions and uncacheable writes
    if (!memSidePort.sendTimingReq(tgt_pkt)) {
        // note that we have now masked any requestBus and
        // schedSendEvent (we will wait for a retry before
        // doing anything), and this is so even if we do not
        // care about this packet and might override it before
        // it gets retried
        return true;
    } else {
        markInService(wq_entry);
        return false;
    }
}

Last tick:
7306611500: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)

Last cpu0 instruction:
7306519500: system.cpu0: A0 T0 : @__flush_dcache_area+52    :   ret                      : IntAlu :   FetchSeq=13255201  CPSeq=11776693  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)

grep 80a70800 trace.txt
      0: CacheVerbose: system.iocache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.l2: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu0.icache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu0.dcache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu1.icache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu1.dcache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu2.icache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu2.dcache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu3.icache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu3.dcache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu4.icache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu4.dcache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu5.icache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu5.dcache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu6.icache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu6.dcache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu7.icache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu7.dcache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
2116500: ExecEnable: system.cpu0: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=218  CPSeq=74  flags=(IsInteger)
2199500: ExecEnable: system.cpu0: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=226  CPSeq=77  flags=(IsInteger|IsMemRef|IsStore)
2204000: Cache: system.cpu0.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000
2205000: Cache: system.cpu0.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
2205000: Cache: system.l2: access for WriteReq [80a70800:80a70803] UC D=110e0000
2215500: Cache: system.l2: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
2215500: DRAM: system.mem_ctrls: recvTimingReq: request WriteReq addr 0x80a70800 size 4
2215500: DRAM: system.mem_ctrls: Responding to Address 0x80a70800.. 2215500: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 8 scheduled @ 2235000
2215500: DRAM: system.mem_ctrls: Done: WriteResp [80a70800:80a70803] UC D=110e0000
2237000: Cache: system.l2: recvTimingResp: Handling response WriteResp [80a70800:80a70803] UC D=110e0000
2247500: Cache: system.cpu0.dcache: recvTimingResp: Handling response WriteResp [80a70800:80a70803] UC D=110e0000
2199500: ExecEnable: system.cpu0: A0 T0 : @_kernel_size_le_lo32+2144375192    :   dc ivac   , x1           : MemWrite :  A=0x80a70800  FetchSeq=228  CPSeq=79  flags=(IsInteger|IsMemRef|IsStore)
2252500: Cache: system.cpu0.dcache: access for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 miss
2253500: Cache: system.cpu0.dcache: sendMSHRQueuePacket: MSHR InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
2253500: Cache: system.l2: access for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 miss
2264000: Cache: system.l2: sendMSHRQueuePacket: MSHR InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
2272000: Cache: system.l2: recvTimingResp: Handling response InvalidateResp [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
2272000: CacheVerbose: system.l2: recvTimingResp: Leaving with InvalidateResp [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
2282500: Cache: system.cpu0.dcache: recvTimingResp: Handling response InvalidateResp [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
2282500: CacheVerbose: system.cpu0.dcache: recvTimingResp: Leaving with InvalidateResp [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
18843500: ExecEnable: system.cpu0: A0 T0 : @_kernel_size_le_lo32+2144375372    :   dc ivac   , x1           : MemWrite :  A=0x80a70800  FetchSeq=9292  CPSeq=8760  flags=(IsInteger|IsMemRef|IsStore)
18896500: Cache: system.cpu0.dcache: access for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 miss
18897500: Cache: system.cpu0.dcache: sendMSHRQueuePacket: MSHR InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
18897500: Cache: system.l2: access for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 miss
18908000: Cache: system.l2: sendMSHRQueuePacket: MSHR InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
18916000: Cache: system.l2: recvTimingResp: Handling response InvalidateResp [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
18916000: CacheVerbose: system.l2: recvTimingResp: Leaving with InvalidateResp [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
18926500: Cache: system.cpu0.dcache: recvTimingResp: Handling response InvalidateResp [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
18926500: CacheVerbose: system.cpu0.dcache: recvTimingResp: Leaving with InvalidateResp [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6666523500: Cache: system.cpu0.dcache: access for ReadReq [80a70800:80a70803] D=6090b49e miss
6666524500: Cache: system.cpu0.dcache: sendMSHRQueuePacket: MSHR ReadReq [80a70800:80a70803] D=6090b49e
6666524500: Cache: system.cpu0.dcache: createMissPacket: created ReadSharedReq [80a70800:80a7083f] D=00e2ffa0655500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e74000a000000000000000000000000000000 from ReadReq [80a70800:80a70803] D=6090b49e
6666524500: Cache: system.l2: access for ReadSharedReq [80a70800:80a7083f] D=00e2ffa0655500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e74000a000000000000000000000000000000 miss
6666535000: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadSharedReq [80a70800:80a7083f] D=00e2ffa0655500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e74000a000000000000000000000000000000
6666535000: Cache: system.l2: createMissPacket: created ReadSharedReq [80a70800:80a7083f] D=00aca9986555000070100f9d65550000e0100f9d6555000050110f9d65550000c0110f9d6555000030120f9d65550000a0120f9d6555000010130f9d65550000 from ReadSharedReq [80a70800:80a7083f] D=00e2ffa0655500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e74000a000000000000000000000000000000
6666535000: DRAM: system.mem_ctrls: recvTimingReq: request ReadSharedReq addr 0x80a70800 size 64
6666567500: DRAM: system.mem_ctrls: Responding to Address 0x80a70800.. 6666567500: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 8 scheduled @ 6666595500
6666567500: DRAM: system.mem_ctrls: Done: ReadResp [80a70800:80a7083f] D=110e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6666598000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80a70800:80a7083f] D=110e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6666598000: Cache: system.l2: Block for addr 0x80a70800 being updated in Cache
6666598000: Cache: system.l2: Block addr 0x80a70800 (ns) moving from state 0 to state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x2029 set: 0xc20 way: 0x2
6666598000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80a70800:80a7083f] D=110e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6666608500: Cache: system.cpu0.dcache: recvTimingResp: Handling response ReadResp [80a70800:80a7083f] D=110e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6666608500: Cache: system.cpu0.dcache: Block for addr 0x80a70800 being updated in Cache
6666608500: Cache: system.cpu0.dcache: Block addr 0x80a70800 (ns) moving from state 0 to state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x1014e set: 0x20 way: 0x1
6666608500: CacheVerbose: system.cpu0.dcache: recvTimingResp: Leaving with ReadResp [80a70800:80a7083f] D=110e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6684591500: Cache: system.cpu0.dcache: Create CleanEvict CleanEvict [80a70800:80a7083f] D=
6684592500: Cache: system.cpu0.dcache: sendWriteQueuePacket: write CleanEvict [80a70800:80a7083f] D=
6684592500: Cache: system.l2: access for CleanEvict [80a70800:80a7083f] D= hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x2029 set: 0xc20 way: 0x2
6684592500: Cache: system.l2: handleTimingReqHit satisfied CleanEvict [80a70800:80a7083f] D=, no response needed
6825844000: Cache: system.cpu0.dcache: access for ReadReq [80a70800:80a70803] D=608eb49e miss
6825845000: Cache: system.cpu0.dcache: sendMSHRQueuePacket: MSHR ReadReq [80a70800:80a70803] D=608eb49e
6825845000: Cache: system.cpu0.dcache: createMissPacket: created ReadSharedReq [80a70800:80a7083f] D=00e1ffa0655500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e74000a00d79865550000746976650a005fd6 from ReadReq [80a70800:80a70803] D=608eb49e
6825845000: Cache: system.l2: access for ReadSharedReq [80a70800:80a7083f] D=00e1ffa0655500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e74000a00d79865550000746976650a005fd6 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x2029 set: 0xc20 way: 0x2
6825856000: Cache: system.cpu0.dcache: recvTimingResp: Handling response ReadResp [80a70800:80a7083f] D=110e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6825856000: Cache: system.cpu0.dcache: Block for addr 0x80a70800 being updated in Cache
6825856000: Cache: system.cpu0.dcache: Block addr 0x80a70800 (ns) moving from state 0 to state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x1014e set: 0x20 way: 0
6825856000: CacheVerbose: system.cpu0.dcache: recvTimingResp: Leaving with ReadResp [80a70800:80a7083f] D=110e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6836065000: Cache: system.cpu0.dcache: Create CleanEvict CleanEvict [80a70800:80a7083f] D=
6836066000: Cache: system.cpu0.dcache: sendWriteQueuePacket: write CleanEvict [80a70800:80a7083f] D=
6836066000: Cache: system.l2: access for CleanEvict [80a70800:80a7083f] D= hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x2029 set: 0xc20 way: 0x2
6836066000: Cache: system.l2: handleTimingReqHit satisfied CleanEvict [80a70800:80a7083f] D=, no response needed
6894097000: Cache: system.cpu0.dcache: access for ReadReq [80a70800:80a70803] D=388eb49e miss
6894098000: Cache: system.cpu0.dcache: sendMSHRQueuePacket: MSHR ReadReq [80a70800:80a70803] D=388eb49e
6894098000: Cache: system.cpu0.dcache: createMissPacket: created ReadSharedReq [80a70800:80a7083f] D=c09002a1655500006374696f6e5772617070656420343530207363686564756c6564204020363839343037303030300a00e03891ac63dd97a0c245b900030036 from ReadReq [80a70800:80a70803] D=388eb49e
6894098000: Cache: system.l2: access for ReadSharedReq [80a70800:80a7083f] D=c09002a1655500006374696f6e5772617070656420343530207363686564756c6564204020363839343037303030300a00e03891ac63dd97a0c245b900030036 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x2029 set: 0xc20 way: 0x2
6894109000: Cache: system.cpu0.dcache: recvTimingResp: Handling response ReadResp [80a70800:80a7083f] D=110e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6894109000: Cache: system.cpu0.dcache: Block for addr 0x80a70800 being updated in Cache
6894109000: Cache: system.cpu0.dcache: Block addr 0x80a70800 (ns) moving from state 0 to state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x1014e set: 0x20 way: 0x1
6894109000: CacheVerbose: system.cpu0.dcache: recvTimingResp: Leaving with ReadResp [80a70800:80a7083f] D=110e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6943904000: Cache: system.cpu0.dcache: Create CleanEvict CleanEvict [80a70800:80a7083f] D=
6943905000: Cache: system.cpu0.dcache: sendWriteQueuePacket: write CleanEvict [80a70800:80a7083f] D=
6943905000: Cache: system.l2: access for CleanEvict [80a70800:80a7083f] D= hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x2029 set: 0xc20 way: 0x2
6943905000: Cache: system.l2: handleTimingReqHit satisfied CleanEvict [80a70800:80a7083f] D=, no response needed
7306449500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306493500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306498500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306503500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306511500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306546500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306562000: Cache: system.cpu1.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000
7306563000: Cache: system.cpu1.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
7306563000: Cache: system.l2: access for WriteReq [80a70800:80a70803] UC D=110e0000
7306563000: Cache: system.l2: Create CleanEvict CleanEvict [80a70800:80a7083f] D=
7306563000: Cache: system.l2: Potential to merge writeback WriteReq [80a70800:80a70803] UC D=110e00007306563000: CachePort: system.l2.mem_side: Scheduling send event at 7306573500
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306573500: Cache: system.l2: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
7306573500: DRAM: system.mem_ctrls: recvTimingReq: request WriteReq addr 0x80a70800 size 4
7306573500: DRAM: system.mem_ctrls: Responding to Address 0x80a70800.. 7306573500: DRAM: system.mem_ctrls: Done: WriteResp [80a70800:80a70803] UC D=110e0000
7306583000: Cache: system.l2: sendWriteQueuePacket: write CleanEvict [80a70800:80a7083f] D=
7306581500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306586000: Cache: system.cpu2.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000
7306587000: Cache: system.cpu2.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
7306587000: Cache: system.l2: access for WriteReq [80a70800:80a70803] UC D=110e0000
7306591500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306596000: Cache: system.cpu3.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000
7306597000: Cache: system.cpu3.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
7306597000: Cache: system.l2: access for WriteReq [80a70800:80a70803] UC D=110e0000
7306597500: Cache: system.l2: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
7306597500: DRAM: system.mem_ctrls: recvTimingReq: request WriteReq addr 0x80a70800 size 4
7306597500: DRAM: system.mem_ctrls: Responding to Address 0x80a70800.. 7306597500: DRAM: system.mem_ctrls: Done: WriteResp [80a70800:80a70803] UC D=110e0000
7306600000: Cache: system.l2: recvTimingResp: Handling response WriteResp [80a70800:80a70803] UC D=110e0000
7306601500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306606000: Cache: system.cpu4.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000
7306607000: Cache: system.cpu4.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
7306607000: Cache: system.l2: access for WriteReq [80a70800:80a70803] UC D=110e0000
7306607500: Cache: system.l2: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
7306607500: DRAM: system.mem_ctrls: recvTimingReq: request WriteReq addr 0x80a70800 size 4
7306607500: DRAM: system.mem_ctrls: Responding to Address 0x80a70800.. 7306607500: DRAM: system.mem_ctrls: Done: WriteResp [80a70800:80a70803] UC D=110e0000
7306610500: Cache: system.cpu1.dcache: recvTimingResp: Handling response WriteResp [80a70800:80a70803] UC D=110e0000
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375192    :   dc ivac   , x1           : MemWrite :  A=0x80a70800  FetchSeq=185  CPSeq=40  flags=(IsInteger|IsMemRef|IsStore)
7306611500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306615500: Cache: system.cpu1.dcache: access for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 miss
7306616000: Cache: system.cpu5.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000
7306616500: Cache: system.cpu1.dcache: sendMSHRQueuePacket: MSHR InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306616500: Cache: system.l2: access for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 miss
7306617000: Cache: system.cpu5.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
7306617000: CacheVerbose: system.cpu1.dcache: recvTimingSnoopReq: for WriteReq [80a70800:80a70803] UC D=110e0000
7306617000: Cache: global: handleSnoop for WriteReq [80a70800:80a70803] UC D=110e0000

The last line is actually the very last log line.
WriteReq already necessarily implies pkt->needsWritable() != pkt->isInvalidate() (needsWritable true, isInvalidate false).
One question is why CPU1 holds that cacheline at all. All requests to system.cpu1.dcache have been UC, except for one:
7306615500: Cache: system.cpu1.dcache: access for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 miss

which presumably comes from the DC IVAC!
g ExecEnable trace.txt  | gv cpu0 shows that there are very very few instructions executed on non cpu0 cpus, the crash happens very soon after they start running.
 108500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+6    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=1  CPSeq=1  flags=(IsInteger|IsSerializeBefore)
 108500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+10    :   subs   x0, #12           : IntAlu :  D=0x0000000000000000  FetchSeq=2  CPSeq=2  flags=(IsInteger)
 108500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+14    :   b.ne   <_kernel_flags_le_lo32+142> : IntAlu :   FetchSeq=3  CPSeq=3  flags=(IsControl|IsDirectControl|IsCondControl)
 118500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+6    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=1  CPSeq=1  flags=(IsInteger|IsSerializeBefore)
 118500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+10    :   subs   x0, #12           : IntAlu :  D=0x0000000000000000  FetchSeq=2  CPSeq=2  flags=(IsInteger)
 118500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+14    :   b.ne   <_kernel_flags_le_lo32+142> : IntAlu :   FetchSeq=3  CPSeq=3  flags=(IsControl|IsDirectControl|IsCondControl)
 123500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+6    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=1  CPSeq=1  flags=(IsInteger|IsSerializeBefore)
 123500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+10    :   subs   x0, #12           : IntAlu :  D=0x0000000000000000  FetchSeq=2  CPSeq=2  flags=(IsInteger)
 123500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+14    :   b.ne   <_kernel_flags_le_lo32+142> : IntAlu :   FetchSeq=3  CPSeq=3  flags=(IsControl|IsDirectControl|IsCondControl)
 128500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+6    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=1  CPSeq=1  flags=(IsInteger|IsSerializeBefore)
 128500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+10    :   subs   x0, #12           : IntAlu :  D=0x0000000000000000  FetchSeq=2  CPSeq=2  flags=(IsInteger)
 128500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+14    :   b.ne   <_kernel_flags_le_lo32+142> : IntAlu :   FetchSeq=3  CPSeq=3  flags=(IsControl|IsDirectControl|IsCondControl)
 133500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+6    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=1  CPSeq=1  flags=(IsInteger|IsSerializeBefore)
 133500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+10    :   subs   x0, #12           : IntAlu :  D=0x0000000000000000  FetchSeq=2  CPSeq=2  flags=(IsInteger)
 133500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+14    :   b.ne   <_kernel_flags_le_lo32+142> : IntAlu :   FetchSeq=3  CPSeq=3  flags=(IsControl|IsDirectControl|IsCondControl)
 138500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+6    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=1  CPSeq=1  flags=(IsInteger|IsSerializeBefore)
 138500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+10    :   subs   x0, #12           : IntAlu :  D=0x0000000000000000  FetchSeq=2  CPSeq=2  flags=(IsInteger)
 138500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+14    :   b.ne   <_kernel_flags_le_lo32+142> : IntAlu :   FetchSeq=3  CPSeq=3  flags=(IsControl|IsDirectControl|IsCondControl)
 143500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+6    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=1  CPSeq=1  flags=(IsInteger|IsSerializeBefore)
 143500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+10    :   subs   x0, #12           : IntAlu :  D=0x0000000000000000  FetchSeq=2  CPSeq=2  flags=(IsInteger)
 143500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+14    :   b.ne   <_kernel_flags_le_lo32+142> : IntAlu :   FetchSeq=3  CPSeq=3  flags=(IsControl|IsDirectControl|IsCondControl)
 187500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+142    :   orr   x0, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=13  CPSeq=4  flags=(IsInteger)
 187500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+146    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=14  CPSeq=5  flags=(IsInteger)
 187500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+150    :   orr   x2, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=15  CPSeq=6  flags=(IsInteger)
 187500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+154    :   orr   x3, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=16  CPSeq=7  flags=(IsInteger)
 187500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+158    :   mrs   x4, mpidr_el1      : IntAlu :  D=0x0000000080000001  FetchSeq=17  CPSeq=8  flags=(IsInteger|IsSerializeBefore)
 207500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+142    :   orr   x0, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=13  CPSeq=4  flags=(IsInteger)
 207500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+146    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=14  CPSeq=5  flags=(IsInteger)
 207500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+150    :   orr   x2, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=15  CPSeq=6  flags=(IsInteger)
 207500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+154    :   orr   x3, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=16  CPSeq=7  flags=(IsInteger)
 207500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+158    :   mrs   x4, mpidr_el1      : IntAlu :  D=0x0000000080000002  FetchSeq=17  CPSeq=8  flags=(IsInteger|IsSerializeBefore)
 217500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+142    :   orr   x0, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=13  CPSeq=4  flags=(IsInteger)
 217500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+146    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=14  CPSeq=5  flags=(IsInteger)
 217500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+150    :   orr   x2, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=15  CPSeq=6  flags=(IsInteger)
 217500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+154    :   orr   x3, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=16  CPSeq=7  flags=(IsInteger)
 217500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+158    :   mrs   x4, mpidr_el1      : IntAlu :  D=0x0000000080000003  FetchSeq=17  CPSeq=8  flags=(IsInteger|IsSerializeBefore)
 227500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+142    :   orr   x0, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=13  CPSeq=4  flags=(IsInteger)
 227500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+146    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=14  CPSeq=5  flags=(IsInteger)
 227500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+150    :   orr   x2, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=15  CPSeq=6  flags=(IsInteger)
 227500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+154    :   orr   x3, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=16  CPSeq=7  flags=(IsInteger)
 227500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+158    :   mrs   x4, mpidr_el1      : IntAlu :  D=0x0000000080000004  FetchSeq=17  CPSeq=8  flags=(IsInteger|IsSerializeBefore)
 237500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+142    :   orr   x0, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=13  CPSeq=4  flags=(IsInteger)
 237500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+146    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=14  CPSeq=5  flags=(IsInteger)
 237500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+150    :   orr   x2, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=15  CPSeq=6  flags=(IsInteger)
 237500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+154    :   orr   x3, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=16  CPSeq=7  flags=(IsInteger)
 237500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+158    :   mrs   x4, mpidr_el1      : IntAlu :  D=0x0000000080000005  FetchSeq=17  CPSeq=8  flags=(IsInteger|IsSerializeBefore)
 247500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+142    :   orr   x0, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=13  CPSeq=4  flags=(IsInteger)
 247500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+146    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=14  CPSeq=5  flags=(IsInteger)
 247500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+150    :   orr   x2, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=15  CPSeq=6  flags=(IsInteger)
 247500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+154    :   orr   x3, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=16  CPSeq=7  flags=(IsInteger)
 247500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+158    :   mrs   x4, mpidr_el1      : IntAlu :  D=0x0000000080000006  FetchSeq=17  CPSeq=8  flags=(IsInteger|IsSerializeBefore)
 252500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+142    :   orr   x0, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=13  CPSeq=4  flags=(IsInteger)
 252500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+146    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=14  CPSeq=5  flags=(IsInteger)
 252500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+150    :   orr   x2, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=15  CPSeq=6  flags=(IsInteger)
 252500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+154    :   orr   x3, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=16  CPSeq=7  flags=(IsInteger)
 252500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+158    :   mrs   x4, mpidr_el1      : IntAlu :  D=0x0000000080000007  FetchSeq=17  CPSeq=8  flags=(IsInteger|IsSerializeBefore)
 187500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+162    :   ldr   w1, #264           : MemRead :  D=0x000000ff00ffffff A=0x108  FetchSeq=18  CPSeq=9  flags=(IsInteger|IsMemRef|IsLoad)
 187500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+166    :   ands   x4, x1            : IntAlu :  D=0x0000000000000000  FetchSeq=19  CPSeq=10  flags=(IsInteger)
 187500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+170    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=20  CPSeq=11  flags=(IsInteger)
 188000: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+174    :   b.eq   <_kernel_flags_le_lo32+198> : IntAlu :   FetchSeq=21  CPSeq=12  flags=(IsControl|IsDirectControl|IsCondControl)
 188000: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=22  CPSeq=13  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 207500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+162    :   ldr   w1, #264           : MemRead :  D=0x000000ff00ffffff A=0x108  FetchSeq=18  CPSeq=9  flags=(IsInteger|IsMemRef|IsLoad)
 207500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+166    :   ands   x4, x1            : IntAlu :  D=0x0000000000000000  FetchSeq=19  CPSeq=10  flags=(IsInteger)
 207500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+170    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=20  CPSeq=11  flags=(IsInteger)
 208000: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+174    :   b.eq   <_kernel_flags_le_lo32+198> : IntAlu :   FetchSeq=21  CPSeq=12  flags=(IsControl|IsDirectControl|IsCondControl)
 208000: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=22  CPSeq=13  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 217500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+162    :   ldr   w1, #264           : MemRead :  D=0x000000ff00ffffff A=0x108  FetchSeq=18  CPSeq=9  flags=(IsInteger|IsMemRef|IsLoad)
 217500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+166    :   ands   x4, x1            : IntAlu :  D=0x0000000000000000  FetchSeq=19  CPSeq=10  flags=(IsInteger)
 217500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+170    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=20  CPSeq=11  flags=(IsInteger)
 218000: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+174    :   b.eq   <_kernel_flags_le_lo32+198> : IntAlu :   FetchSeq=21  CPSeq=12  flags=(IsControl|IsDirectControl|IsCondControl)
 218000: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=22  CPSeq=13  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 227500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+162    :   ldr   w1, #264           : MemRead :  D=0x000000ff00ffffff A=0x108  FetchSeq=18  CPSeq=9  flags=(IsInteger|IsMemRef|IsLoad)
 227500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+166    :   ands   x4, x1            : IntAlu :  D=0x0000000000000000  FetchSeq=19  CPSeq=10  flags=(IsInteger)
 227500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+170    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=20  CPSeq=11  flags=(IsInteger)
 228000: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+174    :   b.eq   <_kernel_flags_le_lo32+198> : IntAlu :   FetchSeq=21  CPSeq=12  flags=(IsControl|IsDirectControl|IsCondControl)
 228000: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=22  CPSeq=13  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 237500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+162    :   ldr   w1, #264           : MemRead :  D=0x000000ff00ffffff A=0x108  FetchSeq=18  CPSeq=9  flags=(IsInteger|IsMemRef|IsLoad)
 237500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+166    :   ands   x4, x1            : IntAlu :  D=0x0000000000000000  FetchSeq=19  CPSeq=10  flags=(IsInteger)
 237500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+170    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=20  CPSeq=11  flags=(IsInteger)
 238000: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+174    :   b.eq   <_kernel_flags_le_lo32+198> : IntAlu :   FetchSeq=21  CPSeq=12  flags=(IsControl|IsDirectControl|IsCondControl)
 238000: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=22  CPSeq=13  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 247500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+162    :   ldr   w1, #264           : MemRead :  D=0x000000ff00ffffff A=0x108  FetchSeq=18  CPSeq=9  flags=(IsInteger|IsMemRef|IsLoad)
 247500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+166    :   ands   x4, x1            : IntAlu :  D=0x0000000000000000  FetchSeq=19  CPSeq=10  flags=(IsInteger)
 247500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+170    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=20  CPSeq=11  flags=(IsInteger)
 248000: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+174    :   b.eq   <_kernel_flags_le_lo32+198> : IntAlu :   FetchSeq=21  CPSeq=12  flags=(IsControl|IsDirectControl|IsCondControl)
 248000: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=22  CPSeq=13  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 252500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+162    :   ldr   w1, #264           : MemRead :  D=0x000000ff00ffffff A=0x108  FetchSeq=18  CPSeq=9  flags=(IsInteger|IsMemRef|IsLoad)
 252500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+166    :   ands   x4, x1            : IntAlu :  D=0x0000000000000000  FetchSeq=19  CPSeq=10  flags=(IsInteger)
 252500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+170    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=20  CPSeq=11  flags=(IsInteger)
 253000: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+174    :   b.eq   <_kernel_flags_le_lo32+198> : IntAlu :   FetchSeq=21  CPSeq=12  flags=(IsControl|IsDirectControl|IsCondControl)
 253000: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=22  CPSeq=13  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 334500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=23  CPSeq=14  flags=(IsInteger|IsMemRef|IsLoad)
 354500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=23  CPSeq=14  flags=(IsInteger|IsMemRef|IsLoad)
 364500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=23  CPSeq=14  flags=(IsInteger|IsMemRef|IsLoad)
 374500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=23  CPSeq=14  flags=(IsInteger|IsMemRef|IsLoad)
 384500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=23  CPSeq=14  flags=(IsInteger|IsMemRef|IsLoad)
 394500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=23  CPSeq=14  flags=(IsInteger|IsMemRef|IsLoad)
 399500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=23  CPSeq=14  flags=(IsInteger|IsMemRef|IsLoad)
 334500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x0000000000000000 A=0x8000fff8  FetchSeq=24  CPSeq=15  flags=(IsInteger|IsMemRef|IsLoad)
 334500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=25  CPSeq=16  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
 354500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x0000000000000000 A=0x8000fff8  FetchSeq=24  CPSeq=15  flags=(IsInteger|IsMemRef|IsLoad)
 354500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=25  CPSeq=16  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
 364500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x0000000000000000 A=0x8000fff8  FetchSeq=24  CPSeq=15  flags=(IsInteger|IsMemRef|IsLoad)
 364500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=25  CPSeq=16  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
 374500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x0000000000000000 A=0x8000fff8  FetchSeq=24  CPSeq=15  flags=(IsInteger|IsMemRef|IsLoad)
 374500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=25  CPSeq=16  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
 384500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x0000000000000000 A=0x8000fff8  FetchSeq=24  CPSeq=15  flags=(IsInteger|IsMemRef|IsLoad)
 384500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=25  CPSeq=16  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
 394500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x0000000000000000 A=0x8000fff8  FetchSeq=24  CPSeq=15  flags=(IsInteger|IsMemRef|IsLoad)
 394500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=25  CPSeq=16  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
 399500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x0000000000000000 A=0x8000fff8  FetchSeq=24  CPSeq=15  flags=(IsInteger|IsMemRef|IsLoad)
 399500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=25  CPSeq=16  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
 567500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=74  CPSeq=17  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 577500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=74  CPSeq=17  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 587500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=74  CPSeq=17  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 597500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=74  CPSeq=17  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 607500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=74  CPSeq=17  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 617500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=74  CPSeq=17  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 627500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=74  CPSeq=17  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
7305644500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=75  CPSeq=18  flags=(IsInteger|IsMemRef|IsLoad)
7305649500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=75  CPSeq=18  flags=(IsInteger|IsMemRef|IsLoad)
7305654500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=75  CPSeq=18  flags=(IsInteger|IsMemRef|IsLoad)
7305659500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=75  CPSeq=18  flags=(IsInteger|IsMemRef|IsLoad)
7305664500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=75  CPSeq=18  flags=(IsInteger|IsMemRef|IsLoad)
7305669500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=75  CPSeq=18  flags=(IsInteger|IsMemRef|IsLoad)
7305674500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=75  CPSeq=18  flags=(IsInteger|IsMemRef|IsLoad)
7305644500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x00000000807371a0 A=0x8000fff8  FetchSeq=76  CPSeq=19  flags=(IsInteger|IsMemRef|IsLoad)
7305644500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=77  CPSeq=20  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7305644500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+194    :   br   x4                  : IntAlu :   FetchSeq=78  CPSeq=21  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl)
7305649500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x00000000807371a0 A=0x8000fff8  FetchSeq=76  CPSeq=19  flags=(IsInteger|IsMemRef|IsLoad)
7305649500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=77  CPSeq=20  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7305649500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+194    :   br   x4                  : IntAlu :   FetchSeq=78  CPSeq=21  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl)
7305654500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x00000000807371a0 A=0x8000fff8  FetchSeq=76  CPSeq=19  flags=(IsInteger|IsMemRef|IsLoad)
7305654500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=77  CPSeq=20  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7305654500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+194    :   br   x4                  : IntAlu :   FetchSeq=78  CPSeq=21  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl)
7305659500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x00000000807371a0 A=0x8000fff8  FetchSeq=76  CPSeq=19  flags=(IsInteger|IsMemRef|IsLoad)
7305659500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=77  CPSeq=20  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7305659500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+194    :   br   x4                  : IntAlu :   FetchSeq=78  CPSeq=21  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl)
7305664500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x00000000807371a0 A=0x8000fff8  FetchSeq=76  CPSeq=19  flags=(IsInteger|IsMemRef|IsLoad)
7305664500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=77  CPSeq=20  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7305664500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+194    :   br   x4                  : IntAlu :   FetchSeq=78  CPSeq=21  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl)
7305669500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x00000000807371a0 A=0x8000fff8  FetchSeq=76  CPSeq=19  flags=(IsInteger|IsMemRef|IsLoad)
7305669500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=77  CPSeq=20  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7305669500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+194    :   br   x4                  : IntAlu :   FetchSeq=78  CPSeq=21  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl)
7305674500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x00000000807371a0 A=0x8000fff8  FetchSeq=76  CPSeq=19  flags=(IsInteger|IsMemRef|IsLoad)
7305674500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=77  CPSeq=20  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7305674500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+194    :   br   x4                  : IntAlu :   FetchSeq=78  CPSeq=21  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl)
7305955500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375200    :   bl   <arch_find_n_match_cpu_physical_id> : IntAlu :  D=0x00000000807371a4  FetchSeq=142  CPSeq=22  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7305960500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375200    :   bl   <arch_find_n_match_cpu_physical_id> : IntAlu :  D=0x00000000807371a4  FetchSeq=142  CPSeq=22  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7305970500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375200    :   bl   <arch_find_n_match_cpu_physical_id> : IntAlu :  D=0x00000000807371a4  FetchSeq=142  CPSeq=22  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7305980500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375200    :   bl   <arch_find_n_match_cpu_physical_id> : IntAlu :  D=0x00000000807371a4  FetchSeq=142  CPSeq=22  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7305985500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375200    :   bl   <arch_find_n_match_cpu_physical_id> : IntAlu :  D=0x00000000807371a4  FetchSeq=142  CPSeq=22  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7305990500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375200    :   bl   <arch_find_n_match_cpu_physical_id> : IntAlu :  D=0x00000000807371a4  FetchSeq=142  CPSeq=22  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7305995500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375200    :   bl   <arch_find_n_match_cpu_physical_id> : IntAlu :  D=0x00000000807371a4  FetchSeq=142  CPSeq=22  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306038500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374792    :   msr   spsel, #0x1        : IntAlu :  D=0x0000000000000001  FetchSeq=150  CPSeq=23  flags=(IsSerializeAfter|IsNonSpeculative)
7306038500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374796    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=151  CPSeq=24  flags=(IsInteger|IsSerializeBefore)
7306038500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374800    :   subs   x0, #8            : IntAlu :  D=0x0000000000000000  FetchSeq=152  CPSeq=25  flags=(IsInteger)
7306038500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374804    :   b.eq   <_kernel_size_le_lo32+2144374832> : IntAlu :   FetchSeq=153  CPSeq=26  flags=(IsControl|IsDirectControl|IsCondControl)
7306038500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374808    :   movz   x0, #12368, #16   : IntAlu :  D=0x0000000030500000  FetchSeq=154  CPSeq=27  flags=(IsInteger)
7306038500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374812    :   movk   x0, #2048, #0     : IntAlu :  D=0x0000000030500800  FetchSeq=155  CPSeq=28  flags=(IsInteger)
7306038500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374816    :   msr   sctlr_el1, x0      : IntAlu :  D=0x0000000030500800  FetchSeq=156  CPSeq=29  flags=(IsInteger|IsSerializeAfter|IsNonSpeculative)
7306048500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374792    :   msr   spsel, #0x1        : IntAlu :  D=0x0000000000000001  FetchSeq=150  CPSeq=23  flags=(IsSerializeAfter|IsNonSpeculative)
7306038500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374820    :   movz   w0, #3601, #0     : IntAlu :  D=0x0000000000000e11  FetchSeq=157  CPSeq=30  flags=(IsInteger)
7306039000: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374824    :   isb                      : IntAlu :   FetchSeq=158  CPSeq=31  flags=(IsSquashAfter)
7306048500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374796    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=151  CPSeq=24  flags=(IsInteger|IsSerializeBefore)
7306048500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374800    :   subs   x0, #8            : IntAlu :  D=0x0000000000000000  FetchSeq=152  CPSeq=25  flags=(IsInteger)
7306048500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374804    :   b.eq   <_kernel_size_le_lo32+2144374832> : IntAlu :   FetchSeq=153  CPSeq=26  flags=(IsControl|IsDirectControl|IsCondControl)
7306048500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374808    :   movz   x0, #12368, #16   : IntAlu :  D=0x0000000030500000  FetchSeq=154  CPSeq=27  flags=(IsInteger)
7306048500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374812    :   movk   x0, #2048, #0     : IntAlu :  D=0x0000000030500800  FetchSeq=155  CPSeq=28  flags=(IsInteger)
7306048500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374816    :   msr   sctlr_el1, x0      : IntAlu :  D=0x0000000030500800  FetchSeq=156  CPSeq=29  flags=(IsInteger|IsSerializeAfter|IsNonSpeculative)
7306058500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374792    :   msr   spsel, #0x1        : IntAlu :  D=0x0000000000000001  FetchSeq=150  CPSeq=23  flags=(IsSerializeAfter|IsNonSpeculative)
7306048500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374820    :   movz   w0, #3601, #0     : IntAlu :  D=0x0000000000000e11  FetchSeq=157  CPSeq=30  flags=(IsInteger)
7306049000: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374824    :   isb                      : IntAlu :   FetchSeq=158  CPSeq=31  flags=(IsSquashAfter)
7306058500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374796    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=151  CPSeq=24  flags=(IsInteger|IsSerializeBefore)
7306058500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374800    :   subs   x0, #8            : IntAlu :  D=0x0000000000000000  FetchSeq=152  CPSeq=25  flags=(IsInteger)
7306058500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374804    :   b.eq   <_kernel_size_le_lo32+2144374832> : IntAlu :   FetchSeq=153  CPSeq=26  flags=(IsControl|IsDirectControl|IsCondControl)
7306058500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374808    :   movz   x0, #12368, #16   : IntAlu :  D=0x0000000030500000  FetchSeq=154  CPSeq=27  flags=(IsInteger)
7306058500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374812    :   movk   x0, #2048, #0     : IntAlu :  D=0x0000000030500800  FetchSeq=155  CPSeq=28  flags=(IsInteger)
7306058500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374816    :   msr   sctlr_el1, x0      : IntAlu :  D=0x0000000030500800  FetchSeq=156  CPSeq=29  flags=(IsInteger|IsSerializeAfter|IsNonSpeculative)
7306068500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374792    :   msr   spsel, #0x1        : IntAlu :  D=0x0000000000000001  FetchSeq=150  CPSeq=23  flags=(IsSerializeAfter|IsNonSpeculative)
7306058500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374820    :   movz   w0, #3601, #0     : IntAlu :  D=0x0000000000000e11  FetchSeq=157  CPSeq=30  flags=(IsInteger)
7306059000: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374824    :   isb                      : IntAlu :   FetchSeq=158  CPSeq=31  flags=(IsSquashAfter)
7306068500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374796    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=151  CPSeq=24  flags=(IsInteger|IsSerializeBefore)
7306068500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374800    :   subs   x0, #8            : IntAlu :  D=0x0000000000000000  FetchSeq=152  CPSeq=25  flags=(IsInteger)
7306068500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374804    :   b.eq   <_kernel_size_le_lo32+2144374832> : IntAlu :   FetchSeq=153  CPSeq=26  flags=(IsControl|IsDirectControl|IsCondControl)
7306068500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374808    :   movz   x0, #12368, #16   : IntAlu :  D=0x0000000030500000  FetchSeq=154  CPSeq=27  flags=(IsInteger)
7306068500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374812    :   movk   x0, #2048, #0     : IntAlu :  D=0x0000000030500800  FetchSeq=155  CPSeq=28  flags=(IsInteger)
7306068500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374816    :   msr   sctlr_el1, x0      : IntAlu :  D=0x0000000030500800  FetchSeq=156  CPSeq=29  flags=(IsInteger|IsSerializeAfter|IsNonSpeculative)
7306068500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374820    :   movz   w0, #3601, #0     : IntAlu :  D=0x0000000000000e11  FetchSeq=157  CPSeq=30  flags=(IsInteger)
7306069000: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374824    :   isb                      : IntAlu :   FetchSeq=158  CPSeq=31  flags=(IsSquashAfter)
7306108500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374792    :   msr   spsel, #0x1        : IntAlu :  D=0x0000000000000001  FetchSeq=150  CPSeq=23  flags=(IsSerializeAfter|IsNonSpeculative)
7306108500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374796    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=151  CPSeq=24  flags=(IsInteger|IsSerializeBefore)
7306108500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374800    :   subs   x0, #8            : IntAlu :  D=0x0000000000000000  FetchSeq=152  CPSeq=25  flags=(IsInteger)
7306108500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374804    :   b.eq   <_kernel_size_le_lo32+2144374832> : IntAlu :   FetchSeq=153  CPSeq=26  flags=(IsControl|IsDirectControl|IsCondControl)
7306108500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374808    :   movz   x0, #12368, #16   : IntAlu :  D=0x0000000030500000  FetchSeq=154  CPSeq=27  flags=(IsInteger)
7306108500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374812    :   movk   x0, #2048, #0     : IntAlu :  D=0x0000000030500800  FetchSeq=155  CPSeq=28  flags=(IsInteger)
7306108500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374816    :   msr   sctlr_el1, x0      : IntAlu :  D=0x0000000030500800  FetchSeq=156  CPSeq=29  flags=(IsInteger|IsSerializeAfter|IsNonSpeculative)
7306118500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374792    :   msr   spsel, #0x1        : IntAlu :  D=0x0000000000000001  FetchSeq=150  CPSeq=23  flags=(IsSerializeAfter|IsNonSpeculative)
7306108500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374820    :   movz   w0, #3601, #0     : IntAlu :  D=0x0000000000000e11  FetchSeq=157  CPSeq=30  flags=(IsInteger)
7306109000: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374824    :   isb                      : IntAlu :   FetchSeq=158  CPSeq=31  flags=(IsSquashAfter)
7306118500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374796    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=151  CPSeq=24  flags=(IsInteger|IsSerializeBefore)
7306118500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374800    :   subs   x0, #8            : IntAlu :  D=0x0000000000000000  FetchSeq=152  CPSeq=25  flags=(IsInteger)
7306118500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374804    :   b.eq   <_kernel_size_le_lo32+2144374832> : IntAlu :   FetchSeq=153  CPSeq=26  flags=(IsControl|IsDirectControl|IsCondControl)
7306118500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374808    :   movz   x0, #12368, #16   : IntAlu :  D=0x0000000030500000  FetchSeq=154  CPSeq=27  flags=(IsInteger)
7306118500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374812    :   movk   x0, #2048, #0     : IntAlu :  D=0x0000000030500800  FetchSeq=155  CPSeq=28  flags=(IsInteger)
7306118500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374816    :   msr   sctlr_el1, x0      : IntAlu :  D=0x0000000030500800  FetchSeq=156  CPSeq=29  flags=(IsInteger|IsSerializeAfter|IsNonSpeculative)
7306128500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374792    :   msr   spsel, #0x1        : IntAlu :  D=0x0000000000000001  FetchSeq=150  CPSeq=23  flags=(IsSerializeAfter|IsNonSpeculative)
7306118500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374820    :   movz   w0, #3601, #0     : IntAlu :  D=0x0000000000000e11  FetchSeq=157  CPSeq=30  flags=(IsInteger)
7306119000: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374824    :   isb                      : IntAlu :   FetchSeq=158  CPSeq=31  flags=(IsSquashAfter)
7306128500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374796    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=151  CPSeq=24  flags=(IsInteger|IsSerializeBefore)
7306128500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374800    :   subs   x0, #8            : IntAlu :  D=0x0000000000000000  FetchSeq=152  CPSeq=25  flags=(IsInteger)
7306128500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374804    :   b.eq   <_kernel_size_le_lo32+2144374832> : IntAlu :   FetchSeq=153  CPSeq=26  flags=(IsControl|IsDirectControl|IsCondControl)
7306128500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374808    :   movz   x0, #12368, #16   : IntAlu :  D=0x0000000030500000  FetchSeq=154  CPSeq=27  flags=(IsInteger)
7306128500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374812    :   movk   x0, #2048, #0     : IntAlu :  D=0x0000000030500800  FetchSeq=155  CPSeq=28  flags=(IsInteger)
7306128500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374816    :   msr   sctlr_el1, x0      : IntAlu :  D=0x0000000030500800  FetchSeq=156  CPSeq=29  flags=(IsInteger|IsSerializeAfter|IsNonSpeculative)
7306128500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374820    :   movz   w0, #3601, #0     : IntAlu :  D=0x0000000000000e11  FetchSeq=157  CPSeq=30  flags=(IsInteger)
7306129000: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374824    :   isb                      : IntAlu :   FetchSeq=158  CPSeq=31  flags=(IsSquashAfter)
7306143500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374828    :   ret                      : IntAlu :   FetchSeq=160  CPSeq=32  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306153500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374828    :   ret                      : IntAlu :   FetchSeq=160  CPSeq=32  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306163500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374828    :   ret                      : IntAlu :   FetchSeq=160  CPSeq=32  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306168500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374828    :   ret                      : IntAlu :   FetchSeq=160  CPSeq=32  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306261500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374828    :   ret                      : IntAlu :   FetchSeq=160  CPSeq=32  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306271500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374828    :   ret                      : IntAlu :   FetchSeq=160  CPSeq=32  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306276500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375204    :   bl   <__memblock_alloc_base> : IntAlu :  D=0x00000000807371a8  FetchSeq=161  CPSeq=33  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306281500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374828    :   ret                      : IntAlu :   FetchSeq=160  CPSeq=32  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306286500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375204    :   bl   <__memblock_alloc_base> : IntAlu :  D=0x00000000807371a8  FetchSeq=161  CPSeq=33  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306291500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375204    :   bl   <__memblock_alloc_base> : IntAlu :  D=0x00000000807371a8  FetchSeq=161  CPSeq=33  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306296500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375204    :   bl   <__memblock_alloc_base> : IntAlu :  D=0x00000000807371a8  FetchSeq=161  CPSeq=33  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306338500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375204    :   bl   <__memblock_alloc_base> : IntAlu :  D=0x00000000807371a8  FetchSeq=161  CPSeq=33  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306348500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375204    :   bl   <__memblock_alloc_base> : IntAlu :  D=0x00000000807371a8  FetchSeq=161  CPSeq=33  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306359500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375164    :   adrp   x1, #3379200      : IntAlu :  D=0x0000000080a70000  FetchSeq=168  CPSeq=34  flags=(IsInteger)
7306364500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375204    :   bl   <__memblock_alloc_base> : IntAlu :  D=0x00000000807371a8  FetchSeq=161  CPSeq=33  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306404500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375164    :   adrp   x1, #3379200      : IntAlu :  D=0x0000000080a70000  FetchSeq=168  CPSeq=34  flags=(IsInteger)
7306414500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375164    :   adrp   x1, #3379200      : IntAlu :  D=0x0000000080a70000  FetchSeq=168  CPSeq=34  flags=(IsInteger)
7306424500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375164    :   adrp   x1, #3379200      : IntAlu :  D=0x0000000080a70000  FetchSeq=168  CPSeq=34  flags=(IsInteger)
7306434500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375164    :   adrp   x1, #3379200      : IntAlu :  D=0x0000000080a70000  FetchSeq=168  CPSeq=34  flags=(IsInteger)
7306444500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375164    :   adrp   x1, #3379200      : IntAlu :  D=0x0000000080a70000  FetchSeq=168  CPSeq=34  flags=(IsInteger)
7306449500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306449500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306449500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306459500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375164    :   adrp   x1, #3379200      : IntAlu :  D=0x0000000080a70000  FetchSeq=168  CPSeq=34  flags=(IsInteger)
7306493500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306493500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306493500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306498500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306498500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306498500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306503500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306503500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306503500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306511500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306511500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306511500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306546500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306546500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306546500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306581500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306591500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306601500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375188    :   dmb                      : IntAlu :   FetchSeq=184  CPSeq=39  flags=(IsMemBarrier)
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375192    :   dc ivac   , x1           : MemWrite :  A=0x80a70800  FetchSeq=185  CPSeq=40  flags=(IsInteger|IsMemRef|IsStore)
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375196    :   ret                      : IntAlu :   FetchSeq=186  CPSeq=41  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306611500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)

The ones near @_kernel_flags_le_lo32 are form the gem5 bootloader, the others must be kernel. I don't know why their symbol is lost, but by grepping the kernel source, the entry seems to be secondary_holding_pen, and the last function where the crash happens is https://github.com/torvalds/linux/blob/v4.18/arch/arm64/kernel/head.S#L646:
/*
 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
 * in w0. See arch/arm64/include/asm/virt.h for more info.
 */
set_cpu_boot_mode_flag:
	adr_l	x1, __boot_cpu_mode
	cmp	w0, #BOOT_CPU_MODE_EL2
	b.ne	1f
	add	x1, x1, #4
1:	str	w0, [x1]			// This CPU has booted in EL1
	dmb	sy
	dc	ivac, x1			// Invalidate potentially stale cache line
	ret
ENDPROC(set_cpu_boot_mode_flag)

Near the crash at the end, we see that several CPUs are doing a store to a single memory address:
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306581500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306591500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306601500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375188    :   dmb                      : IntAlu :   FetchSeq=184  CPSeq=39  flags=(IsMemBarrier)
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375192    :   dc ivac   , x1           : MemWrite :  A=0x80a70800  FetchSeq=185  CPSeq=40  flags=(IsInteger|IsMemRef|IsStore)
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375196    :   ret                      : IntAlu :   FetchSeq=186  CPSeq=41  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306611500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)

CPU1 finishes first, and then proceeds to do some memory operations: dmb and dc ivac.
cpu5 is then the first CPU to do its str after those memory operations, so presumably they are the cause of the crash.

  
## config.dot.svg
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN"
 "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
<!-- Generated by graphviz version 2.43.0 (0)
 -->
<!-- Title: G Pages: 1 -->
<svg width="5278pt" height="776pt"
 viewBox="0.00 0.00 5278.00 776.00" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g id="graph0" class="graph" transform="scale(1 1) rotate(0) translate(4 772)">
<title>G</title>
<polygon fill="white" stroke="transparent" points="-4,4 -4,-772 5274,-772 5274,4 -4,4"/>
<g id="clust1" class="cluster">
<title>cluster_root</title>
<g id="a_clust1"><a xlink:title="eventq_index=0&#10;full_system=true&#10;sim_quantum=0&#10;time_sync_enable=false&#10;time_sync_period=100000000000&#10;time_sync_spin_threshold=100000000">
<path fill="#bab6ae" stroke="#000000" d="M20,-8C20,-8 5250,-8 5250,-8 5256,-8 5262,-14 5262,-20 5262,-20 5262,-748 5262,-748 5262,-754 5256,-760 5250,-760 5250,-760 20,-760 20,-760 14,-760 8,-754 8,-748 8,-748 8,-20 8,-20 8,-14 14,-8 20,-8"/>
<text text-anchor="middle" x="2635" y="-744.8" font-family="Arial" font-size="14.00" fill="#000000">root </text>
<text text-anchor="middle" x="2635" y="-729.8" font-family="Arial" font-size="14.00" fill="#000000">: Root</text>
</a>
</g>
</g>
<g id="clust2" class="cluster">
<title>cluster_system</title>
<g id="a_clust2"><a xlink:title="auto_reset_addr=true&#10;cache_line_size=64&#10;eventq_index=0&#10;exit_on_work_items=false&#10;flags_addr=469827632&#10;gic_cpu_addr=738205696&#10;have_crypto=false&#10;have_large_asid_64=false&#10;have_lpae=true&#10;have_lse=true&#10;have_pan=true&#10;have_security=false&#10;have_sve=true&#10;have_virtualization=false&#10;highest_el_is_64=false&#10;init_param=0&#10;m5ops_base=268500992&#10;mem_mode=timing&#10;mem_ranges=2147483648:2415919104&#10;memories=system.mem_ctrls system.realview.bootmem system.realview.flash0 system.realview.flash1 system.realview.trusted_sram&#10;mmap_using_noreserve=false&#10;multi_proc=true&#10;multi_thread=false&#10;&#10;um_work_ids=16&#10;phys_addr_range_64=40&#10;&#13;eadfile=/home/ciro/bak/git/linux&#45;kernel&#45;module&#45;cheat/out/run/gem5/aarch64/0/readfile&#10;&#13;edirect_paths=&#10;&#13;eset_addr=0&#10;semihosting=Null&#10;sve_vl=1&#10;symbolfile=&#10;thermal_components=&#10;thermal_model=Null&#10;work_begin_ckpt_count=0&#10;work_begin_cpu_id_exit=&#45;1&#10;work_begin_exit_count=0&#10;work_cpus_ckpt_count=0&#10;work_end_ckpt_count=0&#10;work_end_exit_count=0&#10;work_item_id=&#45;1&#10;workload=system.workload">
<path fill="#e4e7eb" stroke="#000000" d="M28,-16C28,-16 5242,-16 5242,-16 5248,-16 5254,-22 5254,-28 5254,-28 5254,-702 5254,-702 5254,-708 5248,-714 5242,-714 5242,-714 28,-714 28,-714 22,-714 16,-708 16,-702 16,-702 16,-28 16,-28 16,-22 22,-16 28,-16"/>
<text text-anchor="middle" x="2635" y="-698.8" font-family="Arial" font-size="14.00" fill="#000000">system </text>
<text text-anchor="middle" x="2635" y="-683.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmSystem</text>
</a>
</g>
</g>
<g id="clust3" class="cluster">
<title>cluster_system_tol2bus</title>
<g id="a_clust3"><a xlink:title="clk_domain=system.cpu_clk_domain&#10;eventq_index=0&#10;forward_latency=0&#10;frontend_latency=1&#10;header_latency=1&#10;max_outstanding_snoops=512&#10;max_routing_table_size=512&#10;point_of_coherency=false&#10;point_of_unification=true&#10;power_model=&#10;power_state=system.tol2bus.power_state&#10;&#13;esponse_latency=1&#10;snoop_filter=system.tol2bus.snoop_filter&#10;snoop_response_latency=1&#10;system=system&#10;use_default_range=false&#10;width=32">
<path fill="#6f798c" stroke="#000000" d="M2984,-354C2984,-354 3108,-354 3108,-354 3114,-354 3120,-360 3120,-366 3120,-366 3120,-433 3120,-433 3120,-439 3114,-445 3108,-445 3108,-445 2984,-445 2984,-445 2978,-445 2972,-439 2972,-433 2972,-433 2972,-366 2972,-366 2972,-360 2978,-354 2984,-354"/>
<text text-anchor="middle" x="3046" y="-429.8" font-family="Arial" font-size="14.00" fill="#000000">tol2bus </text>
<text text-anchor="middle" x="3046" y="-414.8" font-family="Arial" font-size="14.00" fill="#000000">: L2XBar</text>
</a>
</g>
</g>
<g id="clust6" class="cluster">
<title>cluster_system_bridge</title>
<g id="a_clust6"><a xlink:title="clk_domain=system.clk_domain&#10;delay=50000&#10;eventq_index=0&#10;power_model=&#10;power_state=system.bridge.power_state&#10;&#13;anges=201326592:536870912 788529152:2147483648&#10;&#13;eq_size=16&#10;&#13;esp_size=16">
<path fill="#bab6ae" stroke="#000000" d="M404,-163C404,-163 528,-163 528,-163 534,-163 540,-169 540,-175 540,-175 540,-242 540,-242 540,-248 534,-254 528,-254 528,-254 404,-254 404,-254 398,-254 392,-248 392,-242 392,-242 392,-175 392,-175 392,-169 398,-163 404,-163"/>
<text text-anchor="middle" x="466" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">bridge </text>
<text text-anchor="middle" x="466" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: Bridge</text>
</a>
</g>
</g>
<g id="clust10" class="cluster">
<title>cluster_system_membus</title>
<g id="a_clust10"><a xlink:title="clk_domain=system.clk_domain&#10;eventq_index=0&#10;forward_latency=4&#10;frontend_latency=3&#10;header_latency=1&#10;max_outstanding_snoops=512&#10;max_routing_table_size=512&#10;point_of_coherency=true&#10;point_of_unification=true&#10;power_model=&#10;power_state=system.membus.power_state&#10;&#13;esponse_latency=2&#10;snoop_filter=system.membus.snoop_filter&#10;snoop_response_latency=4&#10;system=system&#10;use_default_range=false&#10;width=16">
<path fill="#6f798c" stroke="#000000" d="M36,-155C36,-155 236,-155 236,-155 242,-155 248,-161 248,-167 248,-167 248,-433 248,-433 248,-439 242,-445 236,-445 236,-445 36,-445 36,-445 30,-445 24,-439 24,-433 24,-433 24,-167 24,-167 24,-161 30,-155 36,-155"/>
<text text-anchor="middle" x="136" y="-429.8" font-family="Arial" font-size="14.00" fill="#000000">membus </text>
<text text-anchor="middle" x="136" y="-414.8" font-family="Arial" font-size="14.00" fill="#000000">: MemBus</text>
</a>
</g>
</g>
<g id="clust13" class="cluster">
<title>cluster_system_membus_badaddr_responder</title>
<g id="a_clust13"><a xlink:title="clk_domain=system.clk_domain&#10;eventq_index=0&#10;fake_mem=false&#10;pio_addr=0&#10;pio_latency=100000&#10;pio_size=8&#10;power_model=&#10;power_state=system.membus.badaddr_responder.power_state&#10;&#13;et_bad_addr=true&#10;&#13;et_data16=65535&#10;&#13;et_data32=4294967295&#10;&#13;et_data64=18446744073709551615&#10;&#13;et_data8=255&#10;system=system&#10;update_data=false&#10;warn_access=warn">
<path fill="#c7a793" stroke="#000000" d="M44,-163C44,-163 158,-163 158,-163 164,-163 170,-169 170,-175 170,-175 170,-242 170,-242 170,-248 164,-254 158,-254 158,-254 44,-254 44,-254 38,-254 32,-248 32,-242 32,-242 32,-175 32,-175 32,-169 38,-163 44,-163"/>
<text text-anchor="middle" x="101" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">badaddr_responder </text>
<text text-anchor="middle" x="101" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: BadAddr</text>
</a>
</g>
</g>
<g id="clust17" class="cluster">
<title>cluster_system_realview</title>
<g id="a_clust17"><a xlink:title="eventq_index=0&#10;intrctrl=system.intrctrl&#10;system=system">
<path fill="#bab6ae" stroke="#000000" d="M136,-469C136,-469 2988,-469 2988,-469 2994,-469 3000,-475 3000,-481 3000,-481 3000,-656 3000,-656 3000,-662 2994,-668 2988,-668 2988,-668 136,-668 136,-668 130,-668 124,-662 124,-656 124,-656 124,-481 124,-481 124,-475 130,-469 136,-469"/>
<text text-anchor="middle" x="1562" y="-652.8" font-family="Arial" font-size="14.00" fill="#000000">realview </text>
<text text-anchor="middle" x="1562" y="-637.8" font-family="Arial" font-size="14.00" fill="#000000">: VExpress_GEM5_V1</text>
</a>
</g>
</g>
<g id="clust18" class="cluster">
<title>cluster_system_realview_hdlcd</title>
<g id="a_clust18"><a xlink:title="amba_id=1314816&#10;clk_domain=system.clk_domain&#10;enable_capture=true&#10;encoder=system.realview.hdlcd.encoder&#10;eventq_index=0&#10;frame_format=Auto&#10;gic=system.realview.gic&#10;int_num=95&#10;pio_addr=721420288&#10;pio_latency=10000&#10;pixel_buffer_size=2048&#10;pixel_chunk=32&#10;power_model=&#10;power_state=system.realview.hdlcd.power_state&#10;pxl_clk=system.realview.dcc.osc_pxl&#10;sid=0&#10;ssid=0&#10;system=system&#10;virt_refresh_rate=50000000000&#10;vnc=system.vncserver&#10;workaround_dma_line_count=true&#10;workaround_swap_rb=false">
<path fill="#c7a793" stroke="#000000" d="M144,-485C144,-485 262,-485 262,-485 268,-485 274,-491 274,-497 274,-497 274,-564 274,-564 274,-570 268,-576 262,-576 262,-576 144,-576 144,-576 138,-576 132,-570 132,-564 132,-564 132,-497 132,-497 132,-491 138,-485 144,-485"/>
<text text-anchor="middle" x="203" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">hdlcd </text>
<text text-anchor="middle" x="203" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: HDLcd</text>
</a>
</g>
</g>
<g id="clust21" class="cluster">
<title>cluster_system_realview_rtc</title>
<g id="a_clust21"><a xlink:title="amba_id=266289&#10;clk_domain=system.clk_domain&#10;eventq_index=0&#10;gic=system.realview.gic&#10;int_delay=100000&#10;int_num=36&#10;pio_addr=471269376&#10;pio_latency=100000&#10;power_model=&#10;power_state=system.realview.rtc.power_state&#10;system=system&#10;time=Thu Jan &#160;1 00:00:00 2009">
<path fill="#c7a793" stroke="#000000" d="M2934,-485C2934,-485 2980,-485 2980,-485 2986,-485 2992,-491 2992,-497 2992,-497 2992,-564 2992,-564 2992,-570 2986,-576 2980,-576 2980,-576 2934,-576 2934,-576 2928,-576 2922,-570 2922,-564 2922,-564 2922,-497 2922,-497 2922,-491 2928,-485 2934,-485"/>
<text text-anchor="middle" x="2957" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">rtc </text>
<text text-anchor="middle" x="2957" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: PL031</text>
</a>
</g>
</g>
<g id="clust23" class="cluster">
<title>cluster_system_realview_trusted_watchdog</title>
<g id="a_clust23"><a xlink:title="amba_id=1316869&#10;clk_domain=system.clk_domain&#10;eventq_index=0&#10;gic=system.realview.gic&#10;int_delay=100000&#10;int_num=56&#10;pio_addr=709427200&#10;pio_latency=100000&#10;power_model=&#10;power_state=system.realview.trusted_watchdog.power_state&#10;system=system">
<path fill="#c7a793" stroke="#000000" d="M418,-485C418,-485 521,-485 521,-485 527,-485 533,-491 533,-497 533,-497 533,-564 533,-564 533,-570 527,-576 521,-576 521,-576 418,-576 418,-576 412,-576 406,-570 406,-564 406,-564 406,-497 406,-497 406,-491 412,-485 418,-485"/>
<text text-anchor="middle" x="469.5" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">trusted_watchdog </text>
<text text-anchor="middle" x="469.5" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: Sp805</text>
</a>
</g>
</g>
<g id="clust27" class="cluster">
<title>cluster_system_realview_pwr_ctrl</title>
<g id="a_clust27"><a xlink:title="clk_domain=system.clk_domain&#10;eventq_index=0&#10;pio_addr=470810624&#10;pio_latency=100000&#10;power_model=&#10;power_state=system.realview.pwr_ctrl.power_state&#10;system=system">
<path fill="#c7a793" stroke="#000000" d="M2801,-485C2801,-485 2902,-485 2902,-485 2908,-485 2914,-491 2914,-497 2914,-497 2914,-564 2914,-564 2914,-570 2908,-576 2902,-576 2902,-576 2801,-576 2801,-576 2795,-576 2789,-570 2789,-564 2789,-564 2789,-497 2789,-497 2789,-491 2795,-485 2801,-485"/>
<text text-anchor="middle" x="2851.5" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">pwr_ctrl </text>
<text text-anchor="middle" x="2851.5" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: FVPBasePwrCtrl</text>
</a>
</g>
</g>
<g id="clust29" class="cluster">
<title>cluster_system_realview_system_watchdog</title>
<g id="a_clust29"><a xlink:title="amba_id=1316869&#10;clk_domain=system.realview.dcc.osc_sys&#10;eventq_index=0&#10;gic=system.realview.gic&#10;int_delay=100000&#10;int_num=130&#10;pio_addr=721813504&#10;pio_latency=100000&#10;power_model=&#10;power_state=system.realview.system_watchdog.power_state&#10;system=system">
<path fill="#c7a793" stroke="#000000" d="M1424,-485C1424,-485 1529,-485 1529,-485 1535,-485 1541,-491 1541,-497 1541,-497 1541,-564 1541,-564 1541,-570 1535,-576 1529,-576 1529,-576 1424,-576 1424,-576 1418,-576 1412,-570 1412,-564 1412,-564 1412,-497 1412,-497 1412,-491 1418,-485 1424,-485"/>
<text text-anchor="middle" x="1476.5" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">system_watchdog </text>
<text text-anchor="middle" x="1476.5" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: Sp805</text>
</a>
</g>
</g>
<g id="clust31" class="cluster">
<title>cluster_system_realview_watchdog</title>
<g id="a_clust31"><a xlink:title="amba_id=1316869&#10;clk_domain=system.realview.clock32KHz&#10;eventq_index=0&#10;gic=system.realview.gic&#10;int_delay=100000&#10;int_num=32&#10;pio_addr=470745088&#10;pio_latency=100000&#10;power_model=&#10;power_state=system.realview.watchdog.power_state&#10;system=system">
<path fill="#c7a793" stroke="#000000" d="M2715,-485C2715,-485 2769,-485 2769,-485 2775,-485 2781,-491 2781,-497 2781,-497 2781,-564 2781,-564 2781,-570 2775,-576 2769,-576 2769,-576 2715,-576 2715,-576 2709,-576 2703,-570 2703,-564 2703,-564 2703,-497 2703,-497 2703,-491 2709,-485 2715,-485"/>
<text text-anchor="middle" x="2742" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">watchdog </text>
<text text-anchor="middle" x="2742" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: Sp805</text>
</a>
</g>
</g>
<g id="clust33" class="cluster">
<title>cluster_system_realview_realview_io</title>
<g id="a_clust33"><a xlink:title="clk_domain=system.clk_domain&#10;eventq_index=0&#10;idreg=806359296&#10;pio_addr=469827584&#10;pio_latency=100000&#10;power_model=&#10;power_state=system.realview.realview_io.power_state&#10;proc_id0=335544320&#10;proc_id1=335544320&#10;system=system">
<path fill="#c7a793" stroke="#000000" d="M2605,-485C2605,-485 2683,-485 2683,-485 2689,-485 2695,-491 2695,-497 2695,-497 2695,-564 2695,-564 2695,-570 2689,-576 2683,-576 2683,-576 2605,-576 2605,-576 2599,-576 2593,-570 2593,-564 2593,-564 2593,-497 2593,-497 2593,-491 2599,-485 2605,-485"/>
<text text-anchor="middle" x="2644" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">realview_io </text>
<text text-anchor="middle" x="2644" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: RealViewCtrl</text>
</a>
</g>
</g>
<g id="clust35" class="cluster">
<title>cluster_system_realview_bootmem</title>
<g id="a_clust35"><a xlink:title="bandwidth=73.000000&#10;clk_domain=system.clk_domain&#10;conf_table_reported=false&#10;eventq_index=0&#10;image_file=&#10;in_addr_map=true&#10;kvm_map=true&#10;&#10;atency=30000&#10;&#10;atency_var=0&#10;&#10;ull=false&#10;power_model=&#10;power_state=system.realview.bootmem.power_state&#10;&#13;ange=0:67108864">
<path fill="#5e5958" stroke="#000000" d="M1098,-485C1098,-485 1190,-485 1190,-485 1196,-485 1202,-491 1202,-497 1202,-497 1202,-564 1202,-564 1202,-570 1196,-576 1190,-576 1190,-576 1098,-576 1098,-576 1092,-576 1086,-570 1086,-564 1086,-564 1086,-497 1086,-497 1086,-491 1092,-485 1098,-485"/>
<text text-anchor="middle" x="1144" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">bootmem </text>
<text text-anchor="middle" x="1144" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: SimpleMemory</text>
</a>
</g>
</g>
<g id="clust43" class="cluster">
<title>cluster_system_realview_generic_timer_mem</title>
<g id="a_clust43"><a xlink:title="clk_domain=system.clk_domain&#10;cnt_control_base=709033984&#10;cnt_ctl_base=713097216&#10;cnt_read_base=713031680&#10;counter=system.realview.sys_counter&#10;eventq_index=0&#10;frames=system.realview.generic_timer_mem.frames0 system.realview.generic_timer_mem.frames1&#10;power_model=&#10;power_state=system.realview.generic_timer_mem.power_state&#10;system=system">
<path fill="#c7a793" stroke="#000000" d="M710,-477C710,-477 1066,-477 1066,-477 1072,-477 1078,-483 1078,-489 1078,-489 1078,-610 1078,-610 1078,-616 1072,-622 1066,-622 1066,-622 710,-622 710,-622 704,-622 698,-616 698,-610 698,-610 698,-489 698,-489 698,-483 704,-477 710,-477"/>
<text text-anchor="middle" x="888" y="-606.8" font-family="Arial" font-size="14.00" fill="#000000">generic_timer_mem </text>
<text text-anchor="middle" x="888" y="-591.8" font-family="Arial" font-size="14.00" fill="#000000">: GenericTimerMem</text>
</a>
</g>
</g>
<g id="clust44" class="cluster">
<title>cluster_system_realview_generic_timer_mem_frames0</title>
<g id="a_clust44"><a xlink:title="clk_domain=system.clk_domain&#10;cnt_base=713162752&#10;cnt_el0_base=18446744073709551615&#10;counter=system.realview.sys_counter&#10;eventq_index=0&#10;int_phys=system.realview.generic_timer_mem.frames0.int_phys&#10;int_virt=system.realview.generic_timer_mem.frames0.int_virt&#10;power_model=&#10;power_state=system.realview.generic_timer_mem.frames0.power_state&#10;system=system">
<path fill="#aa8f7e" stroke="#000000" d="M935,-485C935,-485 1058,-485 1058,-485 1064,-485 1070,-491 1070,-497 1070,-497 1070,-564 1070,-564 1070,-570 1064,-576 1058,-576 1058,-576 935,-576 935,-576 929,-576 923,-570 923,-564 923,-564 923,-497 923,-497 923,-491 929,-485 935,-485"/>
<text text-anchor="middle" x="996.5" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">frames0 </text>
<text text-anchor="middle" x="996.5" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: GenericTimerFrame</text>
</a>
</g>
</g>
<g id="clust48" class="cluster">
<title>cluster_system_realview_generic_timer_mem_frames1</title>
<g id="a_clust48"><a xlink:title="clk_domain=system.clk_domain&#10;cnt_base=713228288&#10;cnt_el0_base=18446744073709551615&#10;counter=system.realview.sys_counter&#10;eventq_index=0&#10;int_phys=system.realview.generic_timer_mem.frames1.int_phys&#10;int_virt=system.realview.generic_timer_mem.frames1.int_virt&#10;power_model=&#10;power_state=system.realview.generic_timer_mem.frames1.power_state&#10;system=system">
<path fill="#aa8f7e" stroke="#000000" d="M780,-485C780,-485 903,-485 903,-485 909,-485 915,-491 915,-497 915,-497 915,-564 915,-564 915,-570 909,-576 903,-576 903,-576 780,-576 780,-576 774,-576 768,-570 768,-564 768,-564 768,-497 768,-497 768,-491 774,-485 780,-485"/>
<text text-anchor="middle" x="841.5" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">frames1 </text>
<text text-anchor="middle" x="841.5" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: GenericTimerFrame</text>
</a>
</g>
</g>
<g id="clust53" class="cluster">
<title>cluster_system_realview_gic</title>
<g id="a_clust53"><a xlink:title="clk_domain=system.clk_domain&#10;cpu_addr=738205696&#10;cpu_pio_delay=10000&#10;cpu_size=8192&#10;dist_addr=738201600&#10;dist_pio_delay=10000&#10;eventq_index=0&#10;gem5_extensions=false&#10;gicc_iidr=33690683&#10;gicd_iidr=33559611&#10;gicd_pidr=2864272&#10;gicv_iidr=33690683&#10;int_latency=10000&#10;it_lines=512&#10;platform=system.realview&#10;power_model=&#10;power_state=system.realview.gic.power_state&#10;system=system">
<path fill="#c7a793" stroke="#000000" d="M632,-485C632,-485 678,-485 678,-485 684,-485 690,-491 690,-497 690,-497 690,-564 690,-564 690,-570 684,-576 678,-576 678,-576 632,-576 632,-576 626,-576 620,-570 620,-564 620,-564 620,-497 620,-497 620,-491 626,-485 632,-485"/>
<text text-anchor="middle" x="655" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">gic </text>
<text text-anchor="middle" x="655" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: Gic400</text>
</a>
</g>
</g>
<g id="clust55" class="cluster">
<title>cluster_system_realview_energy_ctrl</title>
<g id="a_clust55"><a xlink:title="clk_domain=system.clk_domain&#10;dvfs_handler=system.dvfs_handler&#10;eventq_index=0&#10;pio_addr=268435456&#10;pio_latency=100000&#10;power_model=&#10;power_state=system.realview.energy_ctrl.power_state&#10;system=system">
<path fill="#c7a793" stroke="#000000" d="M2509,-485C2509,-485 2573,-485 2573,-485 2579,-485 2585,-491 2585,-497 2585,-497 2585,-564 2585,-564 2585,-570 2579,-576 2573,-576 2573,-576 2509,-576 2509,-576 2503,-576 2497,-570 2497,-564 2497,-564 2497,-497 2497,-497 2497,-491 2503,-485 2509,-485"/>
<text text-anchor="middle" x="2541" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">energy_ctrl </text>
<text text-anchor="middle" x="2541" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: EnergyCtrl</text>
</a>
</g>
</g>
<g id="clust57" class="cluster">
<title>cluster_system_realview_flash0</title>
<g id="a_clust57"><a xlink:title="bandwidth=73.000000&#10;clk_domain=system.clk_domain&#10;conf_table_reported=false&#10;eventq_index=0&#10;image_file=&#10;in_addr_map=true&#10;kvm_map=true&#10;&#10;atency=30000&#10;&#10;atency_var=0&#10;&#10;ull=false&#10;power_model=&#10;power_state=system.realview.flash0.power_state&#10;&#13;ange=134217728:201326592">
<path fill="#5e5958" stroke="#000000" d="M294,-485C294,-485 386,-485 386,-485 392,-485 398,-491 398,-497 398,-497 398,-564 398,-564 398,-570 392,-576 386,-576 386,-576 294,-576 294,-576 288,-576 282,-570 282,-564 282,-564 282,-497 282,-497 282,-491 288,-485 294,-485"/>
<text text-anchor="middle" x="340" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">flash0 </text>
<text text-anchor="middle" x="340" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: SimpleMemory</text>
</a>
</g>
</g>
<g id="clust59" class="cluster">
<title>cluster_system_realview_flash1</title>
<g id="a_clust59"><a xlink:title="bandwidth=73.000000&#10;clk_domain=system.clk_domain&#10;conf_table_reported=false&#10;eventq_index=0&#10;image_file=&#10;in_addr_map=true&#10;kvm_map=true&#10;&#10;atency=30000&#10;&#10;atency_var=0&#10;&#10;ull=false&#10;power_model=&#10;power_state=system.realview.flash1.power_state&#10;&#13;ange=201326592:268435456">
<path fill="#5e5958" stroke="#000000" d="M2385,-485C2385,-485 2477,-485 2477,-485 2483,-485 2489,-491 2489,-497 2489,-497 2489,-564 2489,-564 2489,-570 2483,-576 2477,-576 2477,-576 2385,-576 2385,-576 2379,-576 2373,-570 2373,-564 2373,-564 2373,-497 2373,-497 2373,-491 2379,-485 2385,-485"/>
<text text-anchor="middle" x="2431" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">flash1 </text>
<text text-anchor="middle" x="2431" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: SimpleMemory</text>
</a>
</g>
</g>
<g id="clust61" class="cluster">
<title>cluster_system_realview_pci_host</title>
<g id="a_clust61"><a xlink:title="clk_domain=system.clk_domain&#10;conf_base=805306368&#10;conf_device_bits=12&#10;conf_size=268435456&#10;eventq_index=0&#10;int_base=100&#10;int_count=4&#10;int_policy=ARM_PCI_INT_DEV&#10;pci_dma_base=0&#10;pci_mem_base=1073741824&#10;pci_pio_base=788529152&#10;platform=system.realview&#10;power_model=&#10;power_state=system.realview.pci_host.power_state&#10;system=system">
<path fill="#c7a793" stroke="#000000" d="M2233,-485C2233,-485 2353,-485 2353,-485 2359,-485 2365,-491 2365,-497 2365,-497 2365,-564 2365,-564 2365,-570 2359,-576 2353,-576 2353,-576 2233,-576 2233,-576 2227,-576 2221,-570 2221,-564 2221,-564 2221,-497 2221,-497 2221,-491 2227,-485 2233,-485"/>
<text text-anchor="middle" x="2293" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">pci_host </text>
<text text-anchor="middle" x="2293" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: GenericArmPciHost</text>
</a>
</g>
</g>
<g id="clust63" class="cluster">
<title>cluster_system_realview_gicv2m</title>
<g id="a_clust63"><a xlink:title="clk_domain=system.clk_domain&#10;eventq_index=0&#10;frames=system.realview.gicv2m.frames&#10;gic=system.realview.gic&#10;pio_delay=10000&#10;power_model=&#10;power_state=system.realview.gicv2m.power_state&#10;system=system">
<path fill="#c7a793" stroke="#000000" d="M553,-485C553,-485 600,-485 600,-485 606,-485 612,-491 612,-497 612,-497 612,-564 612,-564 612,-570 606,-576 600,-576 600,-576 553,-576 553,-576 547,-576 541,-570 541,-564 541,-564 541,-497 541,-497 541,-491 547,-485 553,-485"/>
<text text-anchor="middle" x="576.5" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">gicv2m </text>
<text text-anchor="middle" x="576.5" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: Gicv2m</text>
</a>
</g>
</g>
<g id="clust79" class="cluster">
<title>cluster_system_realview_vio0</title>
<g id="a_clust79"><a xlink:title="clk_domain=system.clk_domain&#10;eventq_index=0&#10;interrupt=system.realview.vio0.interrupt&#10;pio_addr=471007232&#10;pio_latency=100000&#10;pio_size=4096&#10;power_model=&#10;power_state=system.realview.vio0.power_state&#10;system=system&#10;vio=system.realview.vio0.vio">
<path fill="#c7a793" stroke="#000000" d="M2131,-485C2131,-485 2201,-485 2201,-485 2207,-485 2213,-491 2213,-497 2213,-497 2213,-564 2213,-564 2213,-570 2207,-576 2201,-576 2201,-576 2131,-576 2131,-576 2125,-576 2119,-570 2119,-564 2119,-564 2119,-497 2119,-497 2119,-491 2125,-485 2131,-485"/>
<text text-anchor="middle" x="2166" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">vio0 </text>
<text text-anchor="middle" x="2166" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: MmioVirtIO</text>
</a>
</g>
</g>
<g id="clust83" class="cluster">
<title>cluster_system_realview_vio1</title>
<g id="a_clust83"><a xlink:title="clk_domain=system.clk_domain&#10;eventq_index=0&#10;interrupt=system.realview.vio1.interrupt&#10;pio_addr=471072768&#10;pio_latency=100000&#10;pio_size=4096&#10;power_model=&#10;power_state=system.realview.vio1.power_state&#10;system=system&#10;vio=system.realview.vio1.vio">
<path fill="#c7a793" stroke="#000000" d="M2029,-485C2029,-485 2099,-485 2099,-485 2105,-485 2111,-491 2111,-497 2111,-497 2111,-564 2111,-564 2111,-570 2105,-576 2099,-576 2099,-576 2029,-576 2029,-576 2023,-576 2017,-570 2017,-564 2017,-564 2017,-497 2017,-497 2017,-491 2023,-485 2029,-485"/>
<text text-anchor="middle" x="2064" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">vio1 </text>
<text text-anchor="middle" x="2064" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: MmioVirtIO</text>
</a>
</g>
</g>
<g id="clust88" class="cluster">
<title>cluster_system_realview_trusted_sram</title>
<g id="a_clust88"><a xlink:title="bandwidth=73.000000&#10;clk_domain=system.clk_domain&#10;conf_table_reported=false&#10;eventq_index=0&#10;image_file=&#10;in_addr_map=true&#10;kvm_map=true&#10;&#10;atency=30000&#10;&#10;atency_var=0&#10;&#10;ull=false&#10;power_model=&#10;power_state=system.realview.trusted_sram.power_state&#10;&#13;ange=67108864:67371008">
<path fill="#5e5958" stroke="#000000" d="M1300,-485C1300,-485 1392,-485 1392,-485 1398,-485 1404,-491 1404,-497 1404,-497 1404,-564 1404,-564 1404,-570 1398,-576 1392,-576 1392,-576 1300,-576 1300,-576 1294,-576 1288,-570 1288,-564 1288,-564 1288,-497 1288,-497 1288,-491 1294,-485 1300,-485"/>
<text text-anchor="middle" x="1346" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">trusted_sram </text>
<text text-anchor="middle" x="1346" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: SimpleMemory</text>
</a>
</g>
</g>
<g id="clust90" class="cluster">
<title>cluster_system_realview_uart0</title>
<g id="a_clust90"><a xlink:title="clk_domain=system.clk_domain&#10;device=system.terminal&#10;end_on_eot=false&#10;eventq_index=0&#10;gic=system.realview.gic&#10;int_delay=100000&#10;int_num=37&#10;pio_addr=470351872&#10;pio_latency=100000&#10;platform=system.realview&#10;power_model=&#10;power_state=system.realview.uart0.power_state&#10;system=system">
<path fill="#c7a793" stroke="#000000" d="M1951,-485C1951,-485 1997,-485 1997,-485 2003,-485 2009,-491 2009,-497 2009,-497 2009,-564 2009,-564 2009,-570 2003,-576 1997,-576 1997,-576 1951,-576 1951,-576 1945,-576 1939,-570 1939,-564 1939,-564 1939,-497 1939,-497 1939,-491 1945,-485 1951,-485"/>
<text text-anchor="middle" x="1974" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">uart0 </text>
<text text-anchor="middle" x="1974" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: Pl011</text>
</a>
</g>
</g>
<g id="clust92" class="cluster">
<title>cluster_system_realview_uart1</title>
<g id="a_clust92"><a xlink:title="clk_domain=system.clk_domain&#10;device=system.realview.uart1.device&#10;end_on_eot=false&#10;eventq_index=0&#10;gic=system.realview.gic&#10;int_delay=100000&#10;int_num=38&#10;pio_addr=470417408&#10;pio_latency=100000&#10;platform=system.realview&#10;power_model=&#10;power_state=system.realview.uart1.power_state&#10;system=system">
<path fill="#c7a793" stroke="#000000" d="M1873,-485C1873,-485 1919,-485 1919,-485 1925,-485 1931,-491 1931,-497 1931,-497 1931,-564 1931,-564 1931,-570 1925,-576 1919,-576 1919,-576 1873,-576 1873,-576 1867,-576 1861,-570 1861,-564 1861,-564 1861,-497 1861,-497 1861,-491 1867,-485 1873,-485"/>
<text text-anchor="middle" x="1896" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">uart1 </text>
<text text-anchor="middle" x="1896" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: Pl011</text>
</a>
</g>
</g>
<g id="clust95" class="cluster">
<title>cluster_system_realview_uart2</title>
<g id="a_clust95"><a xlink:title="clk_domain=system.clk_domain&#10;device=system.realview.uart2.device&#10;end_on_eot=false&#10;eventq_index=0&#10;gic=system.realview.gic&#10;int_delay=100000&#10;int_num=39&#10;pio_addr=470482944&#10;pio_latency=100000&#10;platform=system.realview&#10;power_model=&#10;power_state=system.realview.uart2.power_state&#10;system=system">
<path fill="#c7a793" stroke="#000000" d="M1795,-485C1795,-485 1841,-485 1841,-485 1847,-485 1853,-491 1853,-497 1853,-497 1853,-564 1853,-564 1853,-570 1847,-576 1841,-576 1841,-576 1795,-576 1795,-576 1789,-576 1783,-570 1783,-564 1783,-564 1783,-497 1783,-497 1783,-491 1789,-485 1795,-485"/>
<text text-anchor="middle" x="1818" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">uart2 </text>
<text text-anchor="middle" x="1818" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: Pl011</text>
</a>
</g>
</g>
<g id="clust98" class="cluster">
<title>cluster_system_realview_uart3</title>
<g id="a_clust98"><a xlink:title="clk_domain=system.clk_domain&#10;device=system.realview.uart3.device&#10;end_on_eot=false&#10;eventq_index=0&#10;gic=system.realview.gic&#10;int_delay=100000&#10;int_num=40&#10;pio_addr=470548480&#10;pio_latency=100000&#10;platform=system.realview&#10;power_model=&#10;power_state=system.realview.uart3.power_state&#10;system=system">
<path fill="#c7a793" stroke="#000000" d="M1717,-485C1717,-485 1763,-485 1763,-485 1769,-485 1775,-491 1775,-497 1775,-497 1775,-564 1775,-564 1775,-570 1769,-576 1763,-576 1763,-576 1717,-576 1717,-576 1711,-576 1705,-570 1705,-564 1705,-564 1705,-497 1705,-497 1705,-491 1711,-485 1717,-485"/>
<text text-anchor="middle" x="1740" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">uart3 </text>
<text text-anchor="middle" x="1740" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: Pl011</text>
</a>
</g>
</g>
<g id="clust101" class="cluster">
<title>cluster_system_realview_kmi1</title>
<g id="a_clust101"><a xlink:title="amba_id=1314896&#10;clk_domain=system.clk_domain&#10;eventq_index=0&#10;gic=system.realview.gic&#10;int_delay=100000&#10;int_num=45&#10;pio_addr=470220800&#10;pio_latency=100000&#10;power_model=&#10;power_state=system.realview.kmi1.power_state&#10;ps2=system.realview.kmi1.ps2&#10;system=system">
<path fill="#c7a793" stroke="#000000" d="M1639,-485C1639,-485 1685,-485 1685,-485 1691,-485 1697,-491 1697,-497 1697,-497 1697,-564 1697,-564 1697,-570 1691,-576 1685,-576 1685,-576 1639,-576 1639,-576 1633,-576 1627,-570 1627,-564 1627,-564 1627,-497 1627,-497 1627,-491 1633,-485 1639,-485"/>
<text text-anchor="middle" x="1662" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">kmi1 </text>
<text text-anchor="middle" x="1662" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: Pl050</text>
</a>
</g>
</g>
<g id="clust104" class="cluster">
<title>cluster_system_realview_kmi0</title>
<g id="a_clust104"><a xlink:title="amba_id=1314896&#10;clk_domain=system.clk_domain&#10;eventq_index=0&#10;gic=system.realview.gic&#10;int_delay=100000&#10;int_num=44&#10;pio_addr=470155264&#10;pio_latency=100000&#10;power_model=&#10;power_state=system.realview.kmi0.power_state&#10;ps2=system.realview.kmi0.ps2&#10;system=system">
<path fill="#c7a793" stroke="#000000" d="M1561,-485C1561,-485 1607,-485 1607,-485 1613,-485 1619,-491 1619,-497 1619,-497 1619,-564 1619,-564 1619,-570 1613,-576 1607,-576 1607,-576 1561,-576 1561,-576 1555,-576 1549,-570 1549,-564 1549,-564 1549,-497 1549,-497 1549,-491 1555,-485 1561,-485"/>
<text text-anchor="middle" x="1584" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">kmi0 </text>
<text text-anchor="middle" x="1584" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: Pl050</text>
</a>
</g>
</g>
<g id="clust107" class="cluster">
<title>cluster_system_realview_vgic</title>
<g id="a_clust107"><a xlink:title="clk_domain=system.clk_domain&#10;eventq_index=0&#10;gic=system.realview.gic&#10;gicv_iidr=33690683&#10;hv_addr=738213888&#10;maint_int=25&#10;pio_delay=10000&#10;platform=system.realview&#10;power_model=&#10;power_state=system.realview.vgic.power_state&#10;system=system&#10;vcpu_addr=738222080">
<path fill="#c7a793" stroke="#000000" d="M1222,-485C1222,-485 1268,-485 1268,-485 1274,-485 1280,-491 1280,-497 1280,-497 1280,-564 1280,-564 1280,-570 1274,-576 1268,-576 1268,-576 1222,-576 1222,-576 1216,-576 1210,-570 1210,-564 1210,-564 1210,-497 1210,-497 1210,-491 1216,-485 1222,-485"/>
<text text-anchor="middle" x="1245" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">vgic </text>
<text text-anchor="middle" x="1245" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: VGic</text>
</a>
</g>
</g>
<g id="clust110" class="cluster">
<title>cluster_system_cpu0</title>
<g id="a_clust110"><a xlink:title="LFSTSize=1024&#10;LQEntries=32&#10;LSQCheckLoads=true&#10;LSQDepCheckShift=4&#10;SQEntries=32&#10;SSITSize=1024&#10;activity=0&#10;backComSize=5&#10;branchPred=system.cpu0.branchPred&#10;cacheLoadPorts=200&#10;cacheStorePorts=200&#10;checker=Null&#10;clk_domain=system.cpu_clk_domain&#10;commitToDecodeDelay=1&#10;commitToFetchDelay=1&#10;commitToIEWDelay=1&#10;commitToRenameDelay=1&#10;commitWidth=8&#10;cpu_id=0&#10;decodeToFetchDelay=1&#10;decodeToRenameDelay=1&#10;decodeWidth=8&#10;dispatchWidth=8&#10;do_checkpoint_insts=true&#10;do_statistics_insts=true&#10;dtb=system.cpu0.dtb&#10;eventq_index=0&#10;fetchBufferSize=64&#10;fetchQueueSize=32&#10;fetchToDecodeDelay=1&#10;fetchTrapLatency=1&#10;fetchWidth=8&#10;forwardComSize=5&#10;fuPool=system.cpu0.fuPool&#10;function_trace=false&#10;function_trace_start=0&#10;iewToCommitDelay=1&#10;iewToDecodeDelay=1&#10;iewToFetchDelay=1&#10;iewToRenameDelay=1&#10;interrupts=system.cpu0.interrupts&#10;isa=system.cpu0.isa&#10;issueToExecuteDelay=1&#10;issueWidth=8&#10;itb=system.cpu0.itb&#10;max_insts_all_threads=0&#10;max_insts_any_thread=0&#10;&#10;eedsTSO=false&#10;&#10;umIQEntries=64&#10;&#10;umPhysCCRegs=1280&#10;&#10;umPhysFloatRegs=256&#10;&#10;umPhysIntRegs=256&#10;&#10;umPhysVecPredRegs=32&#10;&#10;umPhysVecRegs=256&#10;&#10;umROBEntries=192&#10;&#10;umRobs=1&#10;&#10;umThreads=1&#10;power_gating_on_idle=false&#10;power_model=&#10;power_state=system.cpu0.power_state&#10;profile=0&#10;progress_interval=0&#10;pwr_gating_latency=300&#10;&#13;enameToDecodeDelay=1&#10;&#13;enameToFetchDelay=1&#10;&#13;enameToIEWDelay=2&#10;&#13;enameToROBDelay=1&#10;&#13;enameWidth=8&#10;simpoint_start_insts=&#10;smtCommitPolicy=RoundRobin&#10;smtFetchPolicy=SingleThread&#10;smtIQPolicy=Partitioned&#10;smtIQThreshold=100&#10;smtLSQPolicy=Partitioned&#10;smtLSQThreshold=100&#10;smtNumFetchingThreads=1&#10;smtROBPolicy=Partitioned&#10;smtROBThreshold=100&#10;socket_id=0&#10;squashWidth=8&#10;store_set_clear_period=250000&#10;switched_out=false&#10;syscallRetryLatency=10000&#10;system=system&#10;tracer=system.cpu0.tracer&#10;trapLatency=13&#10;wait_for_remote_gdb=false&#10;wbWidth=8&#10;workload=">
<path fill="#bbc6d9" stroke="#000000" d="M2028,-24C2028,-24 2512,-24 2512,-24 2518,-24 2524,-30 2524,-36 2524,-36 2524,-334 2524,-334 2524,-340 2518,-346 2512,-346 2512,-346 2028,-346 2028,-346 2022,-346 2016,-340 2016,-334 2016,-334 2016,-36 2016,-36 2016,-30 2022,-24 2028,-24"/>
<text text-anchor="middle" x="2270" y="-330.8" font-family="Arial" font-size="14.00" fill="#000000">cpu0 </text>
<text text-anchor="middle" x="2270" y="-315.8" font-family="Arial" font-size="14.00" fill="#000000">: DerivO3CPU</text>
</a>
</g>
</g>
<g id="clust111" class="cluster">
<title>cluster_system_cpu0_icache</title>
<g id="a_clust111"><a xlink:title="addr_ranges=0:18446744073709551615&#10;assoc=2&#10;clk_domain=system.cpu_clk_domain&#10;clusivity=mostly_incl&#10;compressor=Null&#10;data_latency=2&#10;demand_mshr_reserve=1&#10;eventq_index=0&#10;is_read_only=true&#10;max_miss_count=0&#10;mshrs=4&#10;power_model=&#10;power_state=system.cpu0.icache.power_state&#10;prefetch_on_access=false&#10;prefetcher=Null&#10;&#13;eplacement_policy=system.cpu0.icache.replacement_policy&#10;&#13;esponse_latency=2&#10;sequential_access=false&#10;size=32768&#10;system=system&#10;tag_latency=2&#10;tags=system.cpu0.icache.tags&#10;tgts_per_mshr=20&#10;warmup_percentage=0&#10;write_allocator=Null&#10;write_buffers=8&#10;writeback_clean=true">
<path fill="#bab6ae" stroke="#000000" d="M2314,-32C2314,-32 2476,-32 2476,-32 2482,-32 2488,-38 2488,-44 2488,-44 2488,-111 2488,-111 2488,-117 2482,-123 2476,-123 2476,-123 2314,-123 2314,-123 2308,-123 2302,-117 2302,-111 2302,-111 2302,-44 2302,-44 2302,-38 2308,-32 2314,-32"/>
<text text-anchor="middle" x="2395" y="-107.8" font-family="Arial" font-size="14.00" fill="#000000">icache </text>
<text text-anchor="middle" x="2395" y="-92.8" font-family="Arial" font-size="14.00" fill="#000000">: L1_ICache</text>
</a>
</g>
</g>
<g id="clust175" class="cluster">
<title>cluster_system_cpu0_dtb</title>
<g id="a_clust175"><a xlink:title="eventq_index=0&#10;is_stage2=false&#10;size=64&#10;sys=system&#10;walker=system.cpu0.dtb.walker">
<path fill="#bab6ae" stroke="#000000" d="M2388,-155C2388,-155 2504,-155 2504,-155 2510,-155 2516,-161 2516,-167 2516,-167 2516,-288 2516,-288 2516,-294 2510,-300 2504,-300 2504,-300 2388,-300 2388,-300 2382,-300 2376,-294 2376,-288 2376,-288 2376,-167 2376,-167 2376,-161 2382,-155 2388,-155"/>
<text text-anchor="middle" x="2446" y="-284.8" font-family="Arial" font-size="14.00" fill="#000000">dtb </text>
<text text-anchor="middle" x="2446" y="-269.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmDTB</text>
</a>
</g>
</g>
<g id="clust176" class="cluster">
<title>cluster_system_cpu0_dtb_walker</title>
<g id="a_clust176"><a xlink:title="clk_domain=system.cpu_clk_domain&#10;eventq_index=0&#10;is_stage2=false&#10;&#10;um_squash_per_cycle=2&#10;power_model=&#10;power_state=system.cpu0.dtb.walker.power_state&#10;sys=system">
<path fill="#9f9c95" stroke="#000000" d="M2396,-163C2396,-163 2496,-163 2496,-163 2502,-163 2508,-169 2508,-175 2508,-175 2508,-242 2508,-242 2508,-248 2502,-254 2496,-254 2496,-254 2396,-254 2396,-254 2390,-254 2384,-248 2384,-242 2384,-242 2384,-175 2384,-175 2384,-169 2390,-163 2396,-163"/>
<text text-anchor="middle" x="2446" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
<text text-anchor="middle" x="2446" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
</a>
</g>
</g>
<g id="clust183" class="cluster">
<title>cluster_system_cpu0_itb</title>
<g id="a_clust183"><a xlink:title="eventq_index=0&#10;is_stage2=false&#10;size=64&#10;sys=system&#10;walker=system.cpu0.itb.walker">
<path fill="#bab6ae" stroke="#000000" d="M2240,-155C2240,-155 2356,-155 2356,-155 2362,-155 2368,-161 2368,-167 2368,-167 2368,-288 2368,-288 2368,-294 2362,-300 2356,-300 2356,-300 2240,-300 2240,-300 2234,-300 2228,-294 2228,-288 2228,-288 2228,-167 2228,-167 2228,-161 2234,-155 2240,-155"/>
<text text-anchor="middle" x="2298" y="-284.8" font-family="Arial" font-size="14.00" fill="#000000">itb </text>
<text text-anchor="middle" x="2298" y="-269.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmITB</text>
</a>
</g>
</g>
<g id="clust184" class="cluster">
<title>cluster_system_cpu0_itb_walker</title>
<g id="a_clust184"><a xlink:title="clk_domain=system.cpu_clk_domain&#10;eventq_index=0&#10;is_stage2=false&#10;&#10;um_squash_per_cycle=2&#10;power_model=&#10;power_state=system.cpu0.itb.walker.power_state&#10;sys=system">
<path fill="#9f9c95" stroke="#000000" d="M2248,-163C2248,-163 2348,-163 2348,-163 2354,-163 2360,-169 2360,-175 2360,-175 2360,-242 2360,-242 2360,-248 2354,-254 2348,-254 2348,-254 2248,-254 2248,-254 2242,-254 2236,-248 2236,-242 2236,-242 2236,-175 2236,-175 2236,-169 2242,-163 2248,-163"/>
<text text-anchor="middle" x="2298" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
<text text-anchor="middle" x="2298" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
</a>
</g>
</g>
<g id="clust190" class="cluster">
<title>cluster_system_cpu0_dcache</title>
<g id="a_clust190"><a xlink:title="addr_ranges=0:18446744073709551615&#10;assoc=2&#10;clk_domain=system.cpu_clk_domain&#10;clusivity=mostly_incl&#10;compressor=Null&#10;data_latency=2&#10;demand_mshr_reserve=1&#10;eventq_index=0&#10;is_read_only=false&#10;max_miss_count=0&#10;mshrs=4&#10;power_model=&#10;power_state=system.cpu0.dcache.power_state&#10;prefetch_on_access=false&#10;prefetcher=Null&#10;&#13;eplacement_policy=system.cpu0.dcache.replacement_policy&#10;&#13;esponse_latency=2&#10;sequential_access=false&#10;size=65536&#10;system=system&#10;tag_latency=2&#10;tags=system.cpu0.dcache.tags&#10;tgts_per_mshr=20&#10;warmup_percentage=0&#10;write_allocator=Null&#10;write_buffers=8&#10;writeback_clean=false">
<path fill="#bab6ae" stroke="#000000" d="M2065,-32C2065,-32 2227,-32 2227,-32 2233,-32 2239,-38 2239,-44 2239,-44 2239,-111 2239,-111 2239,-117 2233,-123 2227,-123 2227,-123 2065,-123 2065,-123 2059,-123 2053,-117 2053,-111 2053,-111 2053,-44 2053,-44 2053,-38 2059,-32 2065,-32"/>
<text text-anchor="middle" x="2146" y="-107.8" font-family="Arial" font-size="14.00" fill="#000000">dcache </text>
<text text-anchor="middle" x="2146" y="-92.8" font-family="Arial" font-size="14.00" fill="#000000">: L1_DCache</text>
</a>
</g>
</g>
<g id="clust201" class="cluster">
<title>cluster_system_cpu1</title>
<g id="a_clust201"><a xlink:title="LFSTSize=1024&#10;LQEntries=32&#10;LSQCheckLoads=true&#10;LSQDepCheckShift=4&#10;SQEntries=32&#10;SSITSize=1024&#10;activity=0&#10;backComSize=5&#10;branchPred=system.cpu1.branchPred&#10;cacheLoadPorts=200&#10;cacheStorePorts=200&#10;checker=Null&#10;clk_domain=system.cpu_clk_domain&#10;commitToDecodeDelay=1&#10;commitToFetchDelay=1&#10;commitToIEWDelay=1&#10;commitToRenameDelay=1&#10;commitWidth=8&#10;cpu_id=1&#10;decodeToFetchDelay=1&#10;decodeToRenameDelay=1&#10;decodeWidth=8&#10;dispatchWidth=8&#10;do_checkpoint_insts=true&#10;do_statistics_insts=true&#10;dtb=system.cpu1.dtb&#10;eventq_index=0&#10;fetchBufferSize=64&#10;fetchQueueSize=32&#10;fetchToDecodeDelay=1&#10;fetchTrapLatency=1&#10;fetchWidth=8&#10;forwardComSize=5&#10;fuPool=system.cpu1.fuPool&#10;function_trace=false&#10;function_trace_start=0&#10;iewToCommitDelay=1&#10;iewToDecodeDelay=1&#10;iewToFetchDelay=1&#10;iewToRenameDelay=1&#10;interrupts=system.cpu1.interrupts&#10;isa=system.cpu1.isa&#10;issueToExecuteDelay=1&#10;issueWidth=8&#10;itb=system.cpu1.itb&#10;max_insts_all_threads=0&#10;max_insts_any_thread=0&#10;&#10;eedsTSO=false&#10;&#10;umIQEntries=64&#10;&#10;umPhysCCRegs=1280&#10;&#10;umPhysFloatRegs=256&#10;&#10;umPhysIntRegs=256&#10;&#10;umPhysVecPredRegs=32&#10;&#10;umPhysVecRegs=256&#10;&#10;umROBEntries=192&#10;&#10;umRobs=1&#10;&#10;umThreads=1&#10;power_gating_on_idle=false&#10;power_model=&#10;power_state=system.cpu1.power_state&#10;profile=0&#10;progress_interval=0&#10;pwr_gating_latency=300&#10;&#13;enameToDecodeDelay=1&#10;&#13;enameToFetchDelay=1&#10;&#13;enameToIEWDelay=2&#10;&#13;enameToROBDelay=1&#10;&#13;enameWidth=8&#10;simpoint_start_insts=&#10;smtCommitPolicy=RoundRobin&#10;smtFetchPolicy=SingleThread&#10;smtIQPolicy=Partitioned&#10;smtIQThreshold=100&#10;smtLSQPolicy=Partitioned&#10;smtLSQThreshold=100&#10;smtNumFetchingThreads=1&#10;smtROBPolicy=Partitioned&#10;smtROBThreshold=100&#10;socket_id=0&#10;squashWidth=8&#10;store_set_clear_period=250000&#10;switched_out=false&#10;syscallRetryLatency=10000&#10;system=system&#10;tracer=system.cpu1.tracer&#10;trapLatency=13&#10;wait_for_remote_gdb=false&#10;wbWidth=8&#10;workload=">
<path fill="#bbc6d9" stroke="#000000" d="M2588,-24C2588,-24 3072,-24 3072,-24 3078,-24 3084,-30 3084,-36 3084,-36 3084,-334 3084,-334 3084,-340 3078,-346 3072,-346 3072,-346 2588,-346 2588,-346 2582,-346 2576,-340 2576,-334 2576,-334 2576,-36 2576,-36 2576,-30 2582,-24 2588,-24"/>
<text text-anchor="middle" x="2830" y="-330.8" font-family="Arial" font-size="14.00" fill="#000000">cpu1 </text>
<text text-anchor="middle" x="2830" y="-315.8" font-family="Arial" font-size="14.00" fill="#000000">: DerivO3CPU</text>
</a>
</g>
</g>
<g id="clust202" class="cluster">
<title>cluster_system_cpu1_icache</title>
<g id="a_clust202"><a xlink:title="addr_ranges=0:18446744073709551615&#10;assoc=2&#10;clk_domain=system.cpu_clk_domain&#10;clusivity=mostly_incl&#10;compressor=Null&#10;data_latency=2&#10;demand_mshr_reserve=1&#10;eventq_index=0&#10;is_read_only=true&#10;max_miss_count=0&#10;mshrs=4&#10;power_model=&#10;power_state=system.cpu1.icache.power_state&#10;prefetch_on_access=false&#10;prefetcher=Null&#10;&#13;eplacement_policy=system.cpu1.icache.replacement_policy&#10;&#13;esponse_latency=2&#10;sequential_access=false&#10;size=32768&#10;system=system&#10;tag_latency=2&#10;tags=system.cpu1.icache.tags&#10;tgts_per_mshr=20&#10;warmup_percentage=0&#10;write_allocator=Null&#10;write_buffers=8&#10;writeback_clean=true">
<path fill="#bab6ae" stroke="#000000" d="M2596,-32C2596,-32 2758,-32 2758,-32 2764,-32 2770,-38 2770,-44 2770,-44 2770,-111 2770,-111 2770,-117 2764,-123 2758,-123 2758,-123 2596,-123 2596,-123 2590,-123 2584,-117 2584,-111 2584,-111 2584,-44 2584,-44 2584,-38 2590,-32 2596,-32"/>
<text text-anchor="middle" x="2677" y="-107.8" font-family="Arial" font-size="14.00" fill="#000000">icache </text>
<text text-anchor="middle" x="2677" y="-92.8" font-family="Arial" font-size="14.00" fill="#000000">: L1_ICache</text>
</a>
</g>
</g>
<g id="clust266" class="cluster">
<title>cluster_system_cpu1_dtb</title>
<g id="a_clust266"><a xlink:title="eventq_index=0&#10;is_stage2=false&#10;size=64&#10;sys=system&#10;walker=system.cpu1.dtb.walker">
<path fill="#bab6ae" stroke="#000000" d="M2948,-155C2948,-155 3064,-155 3064,-155 3070,-155 3076,-161 3076,-167 3076,-167 3076,-288 3076,-288 3076,-294 3070,-300 3064,-300 3064,-300 2948,-300 2948,-300 2942,-300 2936,-294 2936,-288 2936,-288 2936,-167 2936,-167 2936,-161 2942,-155 2948,-155"/>
<text text-anchor="middle" x="3006" y="-284.8" font-family="Arial" font-size="14.00" fill="#000000">dtb </text>
<text text-anchor="middle" x="3006" y="-269.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmDTB</text>
</a>
</g>
</g>
<g id="clust267" class="cluster">
<title>cluster_system_cpu1_dtb_walker</title>
<g id="a_clust267"><a xlink:title="clk_domain=system.cpu_clk_domain&#10;eventq_index=0&#10;is_stage2=false&#10;&#10;um_squash_per_cycle=2&#10;power_model=&#10;power_state=system.cpu1.dtb.walker.power_state&#10;sys=system">
<path fill="#9f9c95" stroke="#000000" d="M2956,-163C2956,-163 3056,-163 3056,-163 3062,-163 3068,-169 3068,-175 3068,-175 3068,-242 3068,-242 3068,-248 3062,-254 3056,-254 3056,-254 2956,-254 2956,-254 2950,-254 2944,-248 2944,-242 2944,-242 2944,-175 2944,-175 2944,-169 2950,-163 2956,-163"/>
<text text-anchor="middle" x="3006" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
<text text-anchor="middle" x="3006" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
</a>
</g>
</g>
<g id="clust274" class="cluster">
<title>cluster_system_cpu1_itb</title>
<g id="a_clust274"><a xlink:title="eventq_index=0&#10;is_stage2=false&#10;size=64&#10;sys=system&#10;walker=system.cpu1.itb.walker">
<path fill="#bab6ae" stroke="#000000" d="M2800,-155C2800,-155 2916,-155 2916,-155 2922,-155 2928,-161 2928,-167 2928,-167 2928,-288 2928,-288 2928,-294 2922,-300 2916,-300 2916,-300 2800,-300 2800,-300 2794,-300 2788,-294 2788,-288 2788,-288 2788,-167 2788,-167 2788,-161 2794,-155 2800,-155"/>
<text text-anchor="middle" x="2858" y="-284.8" font-family="Arial" font-size="14.00" fill="#000000">itb </text>
<text text-anchor="middle" x="2858" y="-269.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmITB</text>
</a>
</g>
</g>
<g id="clust275" class="cluster">
<title>cluster_system_cpu1_itb_walker</title>
<g id="a_clust275"><a xlink:title="clk_domain=system.cpu_clk_domain&#10;eventq_index=0&#10;is_stage2=false&#10;&#10;um_squash_per_cycle=2&#10;power_model=&#10;power_state=system.cpu1.itb.walker.power_state&#10;sys=system">
<path fill="#9f9c95" stroke="#000000" d="M2808,-163C2808,-163 2908,-163 2908,-163 2914,-163 2920,-169 2920,-175 2920,-175 2920,-242 2920,-242 2920,-248 2914,-254 2908,-254 2908,-254 2808,-254 2808,-254 2802,-254 2796,-248 2796,-242 2796,-242 2796,-175 2796,-175 2796,-169 2802,-163 2808,-163"/>
<text text-anchor="middle" x="2858" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
<text text-anchor="middle" x="2858" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
</a>
</g>
</g>
<g id="clust281" class="cluster">
<title>cluster_system_cpu1_dcache</title>
<g id="a_clust281"><a xlink:title="addr_ranges=0:18446744073709551615&#10;assoc=2&#10;clk_domain=system.cpu_clk_domain&#10;clusivity=mostly_incl&#10;compressor=Null&#10;data_latency=2&#10;demand_mshr_reserve=1&#10;eventq_index=0&#10;is_read_only=false&#10;max_miss_count=0&#10;mshrs=4&#10;power_model=&#10;power_state=system.cpu1.dcache.power_state&#10;prefetch_on_access=false&#10;prefetcher=Null&#10;&#13;eplacement_policy=system.cpu1.dcache.replacement_policy&#10;&#13;esponse_latency=2&#10;sequential_access=false&#10;size=65536&#10;system=system&#10;tag_latency=2&#10;tags=system.cpu1.dcache.tags&#10;tgts_per_mshr=20&#10;warmup_percentage=0&#10;write_allocator=Null&#10;write_buffers=8&#10;writeback_clean=false">
<path fill="#bab6ae" stroke="#000000" d="M2846,-32C2846,-32 3008,-32 3008,-32 3014,-32 3020,-38 3020,-44 3020,-44 3020,-111 3020,-111 3020,-117 3014,-123 3008,-123 3008,-123 2846,-123 2846,-123 2840,-123 2834,-117 2834,-111 2834,-111 2834,-44 2834,-44 2834,-38 2840,-32 2846,-32"/>
<text text-anchor="middle" x="2927" y="-107.8" font-family="Arial" font-size="14.00" fill="#000000">dcache </text>
<text text-anchor="middle" x="2927" y="-92.8" font-family="Arial" font-size="14.00" fill="#000000">: L1_DCache</text>
</a>
</g>
</g>
<g id="clust292" class="cluster">
<title>cluster_system_cpu2</title>
<g id="a_clust292"><a xlink:title="LFSTSize=1024&#10;LQEntries=32&#10;LSQCheckLoads=true&#10;LSQDepCheckShift=4&#10;SQEntries=32&#10;SSITSize=1024&#10;activity=0&#10;backComSize=5&#10;branchPred=system.cpu2.branchPred&#10;cacheLoadPorts=200&#10;cacheStorePorts=200&#10;checker=Null&#10;clk_domain=system.cpu_clk_domain&#10;commitToDecodeDelay=1&#10;commitToFetchDelay=1&#10;commitToIEWDelay=1&#10;commitToRenameDelay=1&#10;commitWidth=8&#10;cpu_id=2&#10;decodeToFetchDelay=1&#10;decodeToRenameDelay=1&#10;decodeWidth=8&#10;dispatchWidth=8&#10;do_checkpoint_insts=true&#10;do_statistics_insts=true&#10;dtb=system.cpu2.dtb&#10;eventq_index=0&#10;fetchBufferSize=64&#10;fetchQueueSize=32&#10;fetchToDecodeDelay=1&#10;fetchTrapLatency=1&#10;fetchWidth=8&#10;forwardComSize=5&#10;fuPool=system.cpu2.fuPool&#10;function_trace=false&#10;function_trace_start=0&#10;iewToCommitDelay=1&#10;iewToDecodeDelay=1&#10;iewToFetchDelay=1&#10;iewToRenameDelay=1&#10;interrupts=system.cpu2.interrupts&#10;isa=system.cpu2.isa&#10;issueToExecuteDelay=1&#10;issueWidth=8&#10;itb=system.cpu2.itb&#10;max_insts_all_threads=0&#10;max_insts_any_thread=0&#10;&#10;eedsTSO=false&#10;&#10;umIQEntries=64&#10;&#10;umPhysCCRegs=1280&#10;&#10;umPhysFloatRegs=256&#10;&#10;umPhysIntRegs=256&#10;&#10;umPhysVecPredRegs=32&#10;&#10;umPhysVecRegs=256&#10;&#10;umROBEntries=192&#10;&#10;umRobs=1&#10;&#10;umThreads=1&#10;power_gating_on_idle=false&#10;power_model=&#10;power_state=system.cpu2.power_state&#10;profile=0&#10;progress_interval=0&#10;pwr_gating_latency=300&#10;&#13;enameToDecodeDelay=1&#10;&#13;enameToFetchDelay=1&#10;&#13;enameToIEWDelay=2&#10;&#13;enameToROBDelay=1&#10;&#13;enameWidth=8&#10;simpoint_start_insts=&#10;smtCommitPolicy=RoundRobin&#10;smtFetchPolicy=SingleThread&#10;smtIQPolicy=Partitioned&#10;smtIQThreshold=100&#10;smtLSQPolicy=Partitioned&#10;smtLSQThreshold=100&#10;smtNumFetchingThreads=1&#10;smtROBPolicy=Partitioned&#10;smtROBThreshold=100&#10;socket_id=0&#10;squashWidth=8&#10;store_set_clear_period=250000&#10;switched_out=false&#10;syscallRetryLatency=10000&#10;system=system&#10;tracer=system.cpu2.tracer&#10;trapLatency=13&#10;wait_for_remote_gdb=false&#10;wbWidth=8&#10;workload=">
<path fill="#bbc6d9" stroke="#000000" d="M3108,-24C3108,-24 3592,-24 3592,-24 3598,-24 3604,-30 3604,-36 3604,-36 3604,-334 3604,-334 3604,-340 3598,-346 3592,-346 3592,-346 3108,-346 3108,-346 3102,-346 3096,-340 3096,-334 3096,-334 3096,-36 3096,-36 3096,-30 3102,-24 3108,-24"/>
<text text-anchor="middle" x="3350" y="-330.8" font-family="Arial" font-size="14.00" fill="#000000">cpu2 </text>
<text text-anchor="middle" x="3350" y="-315.8" font-family="Arial" font-size="14.00" fill="#000000">: DerivO3CPU</text>
</a>
</g>
</g>
<g id="clust293" class="cluster">
<title>cluster_system_cpu2_icache</title>
<g id="a_clust293"><a xlink:title="addr_ranges=0:18446744073709551615&#10;assoc=2&#10;clk_domain=system.cpu_clk_domain&#10;clusivity=mostly_incl&#10;compressor=Null&#10;data_latency=2&#10;demand_mshr_reserve=1&#10;eventq_index=0&#10;is_read_only=true&#10;max_miss_count=0&#10;mshrs=4&#10;power_model=&#10;power_state=system.cpu2.icache.power_state&#10;prefetch_on_access=false&#10;prefetcher=Null&#10;&#13;eplacement_policy=system.cpu2.icache.replacement_policy&#10;&#13;esponse_latency=2&#10;sequential_access=false&#10;size=32768&#10;system=system&#10;tag_latency=2&#10;tags=system.cpu2.icache.tags&#10;tgts_per_mshr=20&#10;warmup_percentage=0&#10;write_allocator=Null&#10;write_buffers=8&#10;writeback_clean=true">
<path fill="#bab6ae" stroke="#000000" d="M3394,-32C3394,-32 3556,-32 3556,-32 3562,-32 3568,-38 3568,-44 3568,-44 3568,-111 3568,-111 3568,-117 3562,-123 3556,-123 3556,-123 3394,-123 3394,-123 3388,-123 3382,-117 3382,-111 3382,-111 3382,-44 3382,-44 3382,-38 3388,-32 3394,-32"/>
<text text-anchor="middle" x="3475" y="-107.8" font-family="Arial" font-size="14.00" fill="#000000">icache </text>
<text text-anchor="middle" x="3475" y="-92.8" font-family="Arial" font-size="14.00" fill="#000000">: L1_ICache</text>
</a>
</g>
</g>
<g id="clust357" class="cluster">
<title>cluster_system_cpu2_dtb</title>
<g id="a_clust357"><a xlink:title="eventq_index=0&#10;is_stage2=false&#10;size=64&#10;sys=system&#10;walker=system.cpu2.dtb.walker">
<path fill="#bab6ae" stroke="#000000" d="M3468,-155C3468,-155 3584,-155 3584,-155 3590,-155 3596,-161 3596,-167 3596,-167 3596,-288 3596,-288 3596,-294 3590,-300 3584,-300 3584,-300 3468,-300 3468,-300 3462,-300 3456,-294 3456,-288 3456,-288 3456,-167 3456,-167 3456,-161 3462,-155 3468,-155"/>
<text text-anchor="middle" x="3526" y="-284.8" font-family="Arial" font-size="14.00" fill="#000000">dtb </text>
<text text-anchor="middle" x="3526" y="-269.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmDTB</text>
</a>
</g>
</g>
<g id="clust358" class="cluster">
<title>cluster_system_cpu2_dtb_walker</title>
<g id="a_clust358"><a xlink:title="clk_domain=system.cpu_clk_domain&#10;eventq_index=0&#10;is_stage2=false&#10;&#10;um_squash_per_cycle=2&#10;power_model=&#10;power_state=system.cpu2.dtb.walker.power_state&#10;sys=system">
<path fill="#9f9c95" stroke="#000000" d="M3476,-163C3476,-163 3576,-163 3576,-163 3582,-163 3588,-169 3588,-175 3588,-175 3588,-242 3588,-242 3588,-248 3582,-254 3576,-254 3576,-254 3476,-254 3476,-254 3470,-254 3464,-248 3464,-242 3464,-242 3464,-175 3464,-175 3464,-169 3470,-163 3476,-163"/>
<text text-anchor="middle" x="3526" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
<text text-anchor="middle" x="3526" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
</a>
</g>
</g>
<g id="clust365" class="cluster">
<title>cluster_system_cpu2_itb</title>
<g id="a_clust365"><a xlink:title="eventq_index=0&#10;is_stage2=false&#10;size=64&#10;sys=system&#10;walker=system.cpu2.itb.walker">
<path fill="#bab6ae" stroke="#000000" d="M3320,-155C3320,-155 3436,-155 3436,-155 3442,-155 3448,-161 3448,-167 3448,-167 3448,-288 3448,-288 3448,-294 3442,-300 3436,-300 3436,-300 3320,-300 3320,-300 3314,-300 3308,-294 3308,-288 3308,-288 3308,-167 3308,-167 3308,-161 3314,-155 3320,-155"/>
<text text-anchor="middle" x="3378" y="-284.8" font-family="Arial" font-size="14.00" fill="#000000">itb </text>
<text text-anchor="middle" x="3378" y="-269.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmITB</text>
</a>
</g>
</g>
<g id="clust366" class="cluster">
<title>cluster_system_cpu2_itb_walker</title>
<g id="a_clust366"><a xlink:title="clk_domain=system.cpu_clk_domain&#10;eventq_index=0&#10;is_stage2=false&#10;&#10;um_squash_per_cycle=2&#10;power_model=&#10;power_state=system.cpu2.itb.walker.power_state&#10;sys=system">
<path fill="#9f9c95" stroke="#000000" d="M3328,-163C3328,-163 3428,-163 3428,-163 3434,-163 3440,-169 3440,-175 3440,-175 3440,-242 3440,-242 3440,-248 3434,-254 3428,-254 3428,-254 3328,-254 3328,-254 3322,-254 3316,-248 3316,-242 3316,-242 3316,-175 3316,-175 3316,-169 3322,-163 3328,-163"/>
<text text-anchor="middle" x="3378" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
<text text-anchor="middle" x="3378" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
</a>
</g>
</g>
<g id="clust372" class="cluster">
<title>cluster_system_cpu2_dcache</title>
<g id="a_clust372"><a xlink:title="addr_ranges=0:18446744073709551615&#10;assoc=2&#10;clk_domain=system.cpu_clk_domain&#10;clusivity=mostly_incl&#10;compressor=Null&#10;data_latency=2&#10;demand_mshr_reserve=1&#10;eventq_index=0&#10;is_read_only=false&#10;max_miss_count=0&#10;mshrs=4&#10;power_model=&#10;power_state=system.cpu2.dcache.power_state&#10;prefetch_on_access=false&#10;prefetcher=Null&#10;&#13;eplacement_policy=system.cpu2.dcache.replacement_policy&#10;&#13;esponse_latency=2&#10;sequential_access=false&#10;size=65536&#10;system=system&#10;tag_latency=2&#10;tags=system.cpu2.dcache.tags&#10;tgts_per_mshr=20&#10;warmup_percentage=0&#10;write_allocator=Null&#10;write_buffers=8&#10;writeback_clean=false">
<path fill="#bab6ae" stroke="#000000" d="M3145,-32C3145,-32 3307,-32 3307,-32 3313,-32 3319,-38 3319,-44 3319,-44 3319,-111 3319,-111 3319,-117 3313,-123 3307,-123 3307,-123 3145,-123 3145,-123 3139,-123 3133,-117 3133,-111 3133,-111 3133,-44 3133,-44 3133,-38 3139,-32 3145,-32"/>
<text text-anchor="middle" x="3226" y="-107.8" font-family="Arial" font-size="14.00" fill="#000000">dcache </text>
<text text-anchor="middle" x="3226" y="-92.8" font-family="Arial" font-size="14.00" fill="#000000">: L1_DCache</text>
</a>
</g>
</g>
<g id="clust383" class="cluster">
<title>cluster_system_cpu3</title>
<g id="a_clust383"><a xlink:title="LFSTSize=1024&#10;LQEntries=32&#10;LSQCheckLoads=true&#10;LSQDepCheckShift=4&#10;SQEntries=32&#10;SSITSize=1024&#10;activity=0&#10;backComSize=5&#10;branchPred=system.cpu3.branchPred&#10;cacheLoadPorts=200&#10;cacheStorePorts=200&#10;checker=Null&#10;clk_domain=system.cpu_clk_domain&#10;commitToDecodeDelay=1&#10;commitToFetchDelay=1&#10;commitToIEWDelay=1&#10;commitToRenameDelay=1&#10;commitWidth=8&#10;cpu_id=3&#10;decodeToFetchDelay=1&#10;decodeToRenameDelay=1&#10;decodeWidth=8&#10;dispatchWidth=8&#10;do_checkpoint_insts=true&#10;do_statistics_insts=true&#10;dtb=system.cpu3.dtb&#10;eventq_index=0&#10;fetchBufferSize=64&#10;fetchQueueSize=32&#10;fetchToDecodeDelay=1&#10;fetchTrapLatency=1&#10;fetchWidth=8&#10;forwardComSize=5&#10;fuPool=system.cpu3.fuPool&#10;function_trace=false&#10;function_trace_start=0&#10;iewToCommitDelay=1&#10;iewToDecodeDelay=1&#10;iewToFetchDelay=1&#10;iewToRenameDelay=1&#10;interrupts=system.cpu3.interrupts&#10;isa=system.cpu3.isa&#10;issueToExecuteDelay=1&#10;issueWidth=8&#10;itb=system.cpu3.itb&#10;max_insts_all_threads=0&#10;max_insts_any_thread=0&#10;&#10;eedsTSO=false&#10;&#10;umIQEntries=64&#10;&#10;umPhysCCRegs=1280&#10;&#10;umPhysFloatRegs=256&#10;&#10;umPhysIntRegs=256&#10;&#10;umPhysVecPredRegs=32&#10;&#10;umPhysVecRegs=256&#10;&#10;umROBEntries=192&#10;&#10;umRobs=1&#10;&#10;umThreads=1&#10;power_gating_on_idle=false&#10;power_model=&#10;power_state=system.cpu3.power_state&#10;profile=0&#10;progress_interval=0&#10;pwr_gating_latency=300&#10;&#13;enameToDecodeDelay=1&#10;&#13;enameToFetchDelay=1&#10;&#13;enameToIEWDelay=2&#10;&#13;enameToROBDelay=1&#10;&#13;enameWidth=8&#10;simpoint_start_insts=&#10;smtCommitPolicy=RoundRobin&#10;smtFetchPolicy=SingleThread&#10;smtIQPolicy=Partitioned&#10;smtIQThreshold=100&#10;smtLSQPolicy=Partitioned&#10;smtLSQThreshold=100&#10;smtNumFetchingThreads=1&#10;smtROBPolicy=Partitioned&#10;smtROBThreshold=100&#10;socket_id=0&#10;squashWidth=8&#10;store_set_clear_period=250000&#10;switched_out=false&#10;syscallRetryLatency=10000&#10;system=system&#10;tracer=system.cpu3.tracer&#10;trapLatency=13&#10;wait_for_remote_gdb=false&#10;wbWidth=8&#10;workload=">
<path fill="#bbc6d9" stroke="#000000" d="M3668,-24C3668,-24 4152,-24 4152,-24 4158,-24 4164,-30 4164,-36 4164,-36 4164,-334 4164,-334 4164,-340 4158,-346 4152,-346 4152,-346 3668,-346 3668,-346 3662,-346 3656,-340 3656,-334 3656,-334 3656,-36 3656,-36 3656,-30 3662,-24 3668,-24"/>
<text text-anchor="middle" x="3910" y="-330.8" font-family="Arial" font-size="14.00" fill="#000000">cpu3 </text>
<text text-anchor="middle" x="3910" y="-315.8" font-family="Arial" font-size="14.00" fill="#000000">: DerivO3CPU</text>
</a>
</g>
</g>
<g id="clust384" class="cluster">
<title>cluster_system_cpu3_icache</title>
<g id="a_clust384"><a xlink:title="addr_ranges=0:18446744073709551615&#10;assoc=2&#10;clk_domain=system.cpu_clk_domain&#10;clusivity=mostly_incl&#10;compressor=Null&#10;data_latency=2&#10;demand_mshr_reserve=1&#10;eventq_index=0&#10;is_read_only=true&#10;max_miss_count=0&#10;mshrs=4&#10;power_model=&#10;power_state=system.cpu3.icache.power_state&#10;prefetch_on_access=false&#10;prefetcher=Null&#10;&#13;eplacement_policy=system.cpu3.icache.replacement_policy&#10;&#13;esponse_latency=2&#10;sequential_access=false&#10;size=32768&#10;system=system&#10;tag_latency=2&#10;tags=system.cpu3.icache.tags&#10;tgts_per_mshr=20&#10;warmup_percentage=0&#10;write_allocator=Null&#10;write_buffers=8&#10;writeback_clean=true">
<path fill="#bab6ae" stroke="#000000" d="M3676,-32C3676,-32 3838,-32 3838,-32 3844,-32 3850,-38 3850,-44 3850,-44 3850,-111 3850,-111 3850,-117 3844,-123 3838,-123 3838,-123 3676,-123 3676,-123 3670,-123 3664,-117 3664,-111 3664,-111 3664,-44 3664,-44 3664,-38 3670,-32 3676,-32"/>
<text text-anchor="middle" x="3757" y="-107.8" font-family="Arial" font-size="14.00" fill="#000000">icache </text>
<text text-anchor="middle" x="3757" y="-92.8" font-family="Arial" font-size="14.00" fill="#000000">: L1_ICache</text>
</a>
</g>
</g>
<g id="clust448" class="cluster">
<title>cluster_system_cpu3_dtb</title>
<g id="a_clust448"><a xlink:title="eventq_index=0&#10;is_stage2=false&#10;size=64&#10;sys=system&#10;walker=system.cpu3.dtb.walker">
<path fill="#bab6ae" stroke="#000000" d="M4028,-155C4028,-155 4144,-155 4144,-155 4150,-155 4156,-161 4156,-167 4156,-167 4156,-288 4156,-288 4156,-294 4150,-300 4144,-300 4144,-300 4028,-300 4028,-300 4022,-300 4016,-294 4016,-288 4016,-288 4016,-167 4016,-167 4016,-161 4022,-155 4028,-155"/>
<text text-anchor="middle" x="4086" y="-284.8" font-family="Arial" font-size="14.00" fill="#000000">dtb </text>
<text text-anchor="middle" x="4086" y="-269.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmDTB</text>
</a>
</g>
</g>
<g id="clust449" class="cluster">
<title>cluster_system_cpu3_dtb_walker</title>
<g id="a_clust449"><a xlink:title="clk_domain=system.cpu_clk_domain&#10;eventq_index=0&#10;is_stage2=false&#10;&#10;um_squash_per_cycle=2&#10;power_model=&#10;power_state=system.cpu3.dtb.walker.power_state&#10;sys=system">
<path fill="#9f9c95" stroke="#000000" d="M4036,-163C4036,-163 4136,-163 4136,-163 4142,-163 4148,-169 4148,-175 4148,-175 4148,-242 4148,-242 4148,-248 4142,-254 4136,-254 4136,-254 4036,-254 4036,-254 4030,-254 4024,-248 4024,-242 4024,-242 4024,-175 4024,-175 4024,-169 4030,-163 4036,-163"/>
<text text-anchor="middle" x="4086" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
<text text-anchor="middle" x="4086" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
</a>
</g>
</g>
<g id="clust456" class="cluster">
<title>cluster_system_cpu3_itb</title>
<g id="a_clust456"><a xlink:title="eventq_index=0&#10;is_stage2=false&#10;size=64&#10;sys=system&#10;walker=system.cpu3.itb.walker">
<path fill="#bab6ae" stroke="#000000" d="M3880,-155C3880,-155 3996,-155 3996,-155 4002,-155 4008,-161 4008,-167 4008,-167 4008,-288 4008,-288 4008,-294 4002,-300 3996,-300 3996,-300 3880,-300 3880,-300 3874,-300 3868,-294 3868,-288 3868,-288 3868,-167 3868,-167 3868,-161 3874,-155 3880,-155"/>
<text text-anchor="middle" x="3938" y="-284.8" font-family="Arial" font-size="14.00" fill="#000000">itb </text>
<text text-anchor="middle" x="3938" y="-269.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmITB</text>
</a>
</g>
</g>
<g id="clust457" class="cluster">
<title>cluster_system_cpu3_itb_walker</title>
<g id="a_clust457"><a xlink:title="clk_domain=system.cpu_clk_domain&#10;eventq_index=0&#10;is_stage2=false&#10;&#10;um_squash_per_cycle=2&#10;power_model=&#10;power_state=system.cpu3.itb.walker.power_state&#10;sys=system">
<path fill="#9f9c95" stroke="#000000" d="M3888,-163C3888,-163 3988,-163 3988,-163 3994,-163 4000,-169 4000,-175 4000,-175 4000,-242 4000,-242 4000,-248 3994,-254 3988,-254 3988,-254 3888,-254 3888,-254 3882,-254 3876,-248 3876,-242 3876,-242 3876,-175 3876,-175 3876,-169 3882,-163 3888,-163"/>
<text text-anchor="middle" x="3938" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
<text text-anchor="middle" x="3938" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
</a>
</g>
</g>
<g id="clust463" class="cluster">
<title>cluster_system_cpu3_dcache</title>
<g id="a_clust463"><a xlink:title="addr_ranges=0:18446744073709551615&#10;assoc=2&#10;clk_domain=system.cpu_clk_domain&#10;clusivity=mostly_incl&#10;compressor=Null&#10;data_latency=2&#10;demand_mshr_reserve=1&#10;eventq_index=0&#10;is_read_only=false&#10;max_miss_count=0&#10;mshrs=4&#10;power_model=&#10;power_state=system.cpu3.dcache.power_state&#10;prefetch_on_access=false&#10;prefetcher=Null&#10;&#13;eplacement_policy=system.cpu3.dcache.replacement_policy&#10;&#13;esponse_latency=2&#10;sequential_access=false&#10;size=65536&#10;system=system&#10;tag_latency=2&#10;tags=system.cpu3.dcache.tags&#10;tgts_per_mshr=20&#10;warmup_percentage=0&#10;write_allocator=Null&#10;write_buffers=8&#10;writeback_clean=false">
<path fill="#bab6ae" stroke="#000000" d="M3926,-32C3926,-32 4088,-32 4088,-32 4094,-32 4100,-38 4100,-44 4100,-44 4100,-111 4100,-111 4100,-117 4094,-123 4088,-123 4088,-123 3926,-123 3926,-123 3920,-123 3914,-117 3914,-111 3914,-111 3914,-44 3914,-44 3914,-38 3920,-32 3926,-32"/>
<text text-anchor="middle" x="4007" y="-107.8" font-family="Arial" font-size="14.00" fill="#000000">dcache </text>
<text text-anchor="middle" x="4007" y="-92.8" font-family="Arial" font-size="14.00" fill="#000000">: L1_DCache</text>
</a>
</g>
</g>
<g id="clust474" class="cluster">
<title>cluster_system_cpu4</title>
<g id="a_clust474"><a xlink:title="LFSTSize=1024&#10;LQEntries=32&#10;LSQCheckLoads=true&#10;LSQDepCheckShift=4&#10;SQEntries=32&#10;SSITSize=1024&#10;activity=0&#10;backComSize=5&#10;branchPred=system.cpu4.branchPred&#10;cacheLoadPorts=200&#10;cacheStorePorts=200&#10;checker=Null&#10;clk_domain=system.cpu_clk_domain&#10;commitToDecodeDelay=1&#10;commitToFetchDelay=1&#10;commitToIEWDelay=1&#10;commitToRenameDelay=1&#10;commitWidth=8&#10;cpu_id=4&#10;decodeToFetchDelay=1&#10;decodeToRenameDelay=1&#10;decodeWidth=8&#10;dispatchWidth=8&#10;do_checkpoint_insts=true&#10;do_statistics_insts=true&#10;dtb=system.cpu4.dtb&#10;eventq_index=0&#10;fetchBufferSize=64&#10;fetchQueueSize=32&#10;fetchToDecodeDelay=1&#10;fetchTrapLatency=1&#10;fetchWidth=8&#10;forwardComSize=5&#10;fuPool=system.cpu4.fuPool&#10;function_trace=false&#10;function_trace_start=0&#10;iewToCommitDelay=1&#10;iewToDecodeDelay=1&#10;iewToFetchDelay=1&#10;iewToRenameDelay=1&#10;interrupts=system.cpu4.interrupts&#10;isa=system.cpu4.isa&#10;issueToExecuteDelay=1&#10;issueWidth=8&#10;itb=system.cpu4.itb&#10;max_insts_all_threads=0&#10;max_insts_any_thread=0&#10;&#10;eedsTSO=false&#10;&#10;umIQEntries=64&#10;&#10;umPhysCCRegs=1280&#10;&#10;umPhysFloatRegs=256&#10;&#10;umPhysIntRegs=256&#10;&#10;umPhysVecPredRegs=32&#10;&#10;umPhysVecRegs=256&#10;&#10;umROBEntries=192&#10;&#10;umRobs=1&#10;&#10;umThreads=1&#10;power_gating_on_idle=false&#10;power_model=&#10;power_state=system.cpu4.power_state&#10;profile=0&#10;progress_interval=0&#10;pwr_gating_latency=300&#10;&#13;enameToDecodeDelay=1&#10;&#13;enameToFetchDelay=1&#10;&#13;enameToIEWDelay=2&#10;&#13;enameToROBDelay=1&#10;&#13;enameWidth=8&#10;simpoint_start_insts=&#10;smtCommitPolicy=RoundRobin&#10;smtFetchPolicy=SingleThread&#10;smtIQPolicy=Partitioned&#10;smtIQThreshold=100&#10;smtLSQPolicy=Partitioned&#10;smtLSQThreshold=100&#10;smtNumFetchingThreads=1&#10;smtROBPolicy=Partitioned&#10;smtROBThreshold=100&#10;socket_id=0&#10;squashWidth=8&#10;store_set_clear_period=250000&#10;switched_out=false&#10;syscallRetryLatency=10000&#10;system=system&#10;tracer=system.cpu4.tracer&#10;trapLatency=13&#10;wait_for_remote_gdb=false&#10;wbWidth=8&#10;workload=">
<path fill="#bbc6d9" stroke="#000000" d="M4188,-24C4188,-24 4672,-24 4672,-24 4678,-24 4684,-30 4684,-36 4684,-36 4684,-334 4684,-334 4684,-340 4678,-346 4672,-346 4672,-346 4188,-346 4188,-346 4182,-346 4176,-340 4176,-334 4176,-334 4176,-36 4176,-36 4176,-30 4182,-24 4188,-24"/>
<text text-anchor="middle" x="4430" y="-330.8" font-family="Arial" font-size="14.00" fill="#000000">cpu4 </text>
<text text-anchor="middle" x="4430" y="-315.8" font-family="Arial" font-size="14.00" fill="#000000">: DerivO3CPU</text>
</a>
</g>
</g>
<g id="clust475" class="cluster">
<title>cluster_system_cpu4_icache</title>
<g id="a_clust475"><a xlink:title="addr_ranges=0:18446744073709551615&#10;assoc=2&#10;clk_domain=system.cpu_clk_domain&#10;clusivity=mostly_incl&#10;compressor=Null&#10;data_latency=2&#10;demand_mshr_reserve=1&#10;eventq_index=0&#10;is_read_only=true&#10;max_miss_count=0&#10;mshrs=4&#10;power_model=&#10;power_state=system.cpu4.icache.power_state&#10;prefetch_on_access=false&#10;prefetcher=Null&#10;&#13;eplacement_policy=system.cpu4.icache.replacement_policy&#10;&#13;esponse_latency=2&#10;sequential_access=false&#10;size=32768&#10;system=system&#10;tag_latency=2&#10;tags=system.cpu4.icache.tags&#10;tgts_per_mshr=20&#10;warmup_percentage=0&#10;write_allocator=Null&#10;write_buffers=8&#10;writeback_clean=true">
<path fill="#bab6ae" stroke="#000000" d="M4474,-32C4474,-32 4636,-32 4636,-32 4642,-32 4648,-38 4648,-44 4648,-44 4648,-111 4648,-111 4648,-117 4642,-123 4636,-123 4636,-123 4474,-123 4474,-123 4468,-123 4462,-117 4462,-111 4462,-111 4462,-44 4462,-44 4462,-38 4468,-32 4474,-32"/>
<text text-anchor="middle" x="4555" y="-107.8" font-family="Arial" font-size="14.00" fill="#000000">icache </text>
<text text-anchor="middle" x="4555" y="-92.8" font-family="Arial" font-size="14.00" fill="#000000">: L1_ICache</text>
</a>
</g>
</g>
<g id="clust539" class="cluster">
<title>cluster_system_cpu4_dtb</title>
<g id="a_clust539"><a xlink:title="eventq_index=0&#10;is_stage2=false&#10;size=64&#10;sys=system&#10;walker=system.cpu4.dtb.walker">
<path fill="#bab6ae" stroke="#000000" d="M4548,-155C4548,-155 4664,-155 4664,-155 4670,-155 4676,-161 4676,-167 4676,-167 4676,-288 4676,-288 4676,-294 4670,-300 4664,-300 4664,-300 4548,-300 4548,-300 4542,-300 4536,-294 4536,-288 4536,-288 4536,-167 4536,-167 4536,-161 4542,-155 4548,-155"/>
<text text-anchor="middle" x="4606" y="-284.8" font-family="Arial" font-size="14.00" fill="#000000">dtb </text>
<text text-anchor="middle" x="4606" y="-269.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmDTB</text>
</a>
</g>
</g>
<g id="clust540" class="cluster">
<title>cluster_system_cpu4_dtb_walker</title>
<g id="a_clust540"><a xlink:title="clk_domain=system.cpu_clk_domain&#10;eventq_index=0&#10;is_stage2=false&#10;&#10;um_squash_per_cycle=2&#10;power_model=&#10;power_state=system.cpu4.dtb.walker.power_state&#10;sys=system">
<path fill="#9f9c95" stroke="#000000" d="M4556,-163C4556,-163 4656,-163 4656,-163 4662,-163 4668,-169 4668,-175 4668,-175 4668,-242 4668,-242 4668,-248 4662,-254 4656,-254 4656,-254 4556,-254 4556,-254 4550,-254 4544,-248 4544,-242 4544,-242 4544,-175 4544,-175 4544,-169 4550,-163 4556,-163"/>
<text text-anchor="middle" x="4606" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
<text text-anchor="middle" x="4606" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
</a>
</g>
</g>
<g id="clust547" class="cluster">
<title>cluster_system_cpu4_itb</title>
<g id="a_clust547"><a xlink:title="eventq_index=0&#10;is_stage2=false&#10;size=64&#10;sys=system&#10;walker=system.cpu4.itb.walker">
<path fill="#bab6ae" stroke="#000000" d="M4400,-155C4400,-155 4516,-155 4516,-155 4522,-155 4528,-161 4528,-167 4528,-167 4528,-288 4528,-288 4528,-294 4522,-300 4516,-300 4516,-300 4400,-300 4400,-300 4394,-300 4388,-294 4388,-288 4388,-288 4388,-167 4388,-167 4388,-161 4394,-155 4400,-155"/>
<text text-anchor="middle" x="4458" y="-284.8" font-family="Arial" font-size="14.00" fill="#000000">itb </text>
<text text-anchor="middle" x="4458" y="-269.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmITB</text>
</a>
</g>
</g>
<g id="clust548" class="cluster">
<title>cluster_system_cpu4_itb_walker</title>
<g id="a_clust548"><a xlink:title="clk_domain=system.cpu_clk_domain&#10;eventq_index=0&#10;is_stage2=false&#10;&#10;um_squash_per_cycle=2&#10;power_model=&#10;power_state=system.cpu4.itb.walker.power_state&#10;sys=system">
<path fill="#9f9c95" stroke="#000000" d="M4408,-163C4408,-163 4508,-163 4508,-163 4514,-163 4520,-169 4520,-175 4520,-175 4520,-242 4520,-242 4520,-248 4514,-254 4508,-254 4508,-254 4408,-254 4408,-254 4402,-254 4396,-248 4396,-242 4396,-242 4396,-175 4396,-175 4396,-169 4402,-163 4408,-163"/>
<text text-anchor="middle" x="4458" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
<text text-anchor="middle" x="4458" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
</a>
</g>
</g>
<g id="clust554" class="cluster">
<title>cluster_system_cpu4_dcache</title>
<g id="a_clust554"><a xlink:title="addr_ranges=0:18446744073709551615&#10;assoc=2&#10;clk_domain=system.cpu_clk_domain&#10;clusivity=mostly_incl&#10;compressor=Null&#10;data_latency=2&#10;demand_mshr_reserve=1&#10;eventq_index=0&#10;is_read_only=false&#10;max_miss_count=0&#10;mshrs=4&#10;power_model=&#10;power_state=system.cpu4.dcache.power_state&#10;prefetch_on_access=false&#10;prefetcher=Null&#10;&#13;eplacement_policy=system.cpu4.dcache.replacement_policy&#10;&#13;esponse_latency=2&#10;sequential_access=false&#10;size=65536&#10;system=system&#10;tag_latency=2&#10;tags=system.cpu4.dcache.tags&#10;tgts_per_mshr=20&#10;warmup_percentage=0&#10;write_allocator=Null&#10;write_buffers=8&#10;writeback_clean=false">
<path fill="#bab6ae" stroke="#000000" d="M4225,-32C4225,-32 4387,-32 4387,-32 4393,-32 4399,-38 4399,-44 4399,-44 4399,-111 4399,-111 4399,-117 4393,-123 4387,-123 4387,-123 4225,-123 4225,-123 4219,-123 4213,-117 4213,-111 4213,-111 4213,-44 4213,-44 4213,-38 4219,-32 4225,-32"/>
<text text-anchor="middle" x="4306" y="-107.8" font-family="Arial" font-size="14.00" fill="#000000">dcache </text>
<text text-anchor="middle" x="4306" y="-92.8" font-family="Arial" font-size="14.00" fill="#000000">: L1_DCache</text>
</a>
</g>
</g>
<g id="clust565" class="cluster">
<title>cluster_system_cpu5</title>
<g id="a_clust565"><a xlink:title="LFSTSize=1024&#10;LQEntries=32&#10;LSQCheckLoads=true&#10;LSQDepCheckShift=4&#10;SQEntries=32&#10;SSITSize=1024&#10;activity=0&#10;backComSize=5&#10;branchPred=system.cpu5.branchPred&#10;cacheLoadPorts=200&#10;cacheStorePorts=200&#10;checker=Null&#10;clk_domain=system.cpu_clk_domain&#10;commitToDecodeDelay=1&#10;commitToFetchDelay=1&#10;commitToIEWDelay=1&#10;commitToRenameDelay=1&#10;commitWidth=8&#10;cpu_id=5&#10;decodeToFetchDelay=1&#10;decodeToRenameDelay=1&#10;decodeWidth=8&#10;dispatchWidth=8&#10;do_checkpoint_insts=true&#10;do_statistics_insts=true&#10;dtb=system.cpu5.dtb&#10;eventq_index=0&#10;fetchBufferSize=64&#10;fetchQueueSize=32&#10;fetchToDecodeDelay=1&#10;fetchTrapLatency=1&#10;fetchWidth=8&#10;forwardComSize=5&#10;fuPool=system.cpu5.fuPool&#10;function_trace=false&#10;function_trace_start=0&#10;iewToCommitDelay=1&#10;iewToDecodeDelay=1&#10;iewToFetchDelay=1&#10;iewToRenameDelay=1&#10;interrupts=system.cpu5.interrupts&#10;isa=system.cpu5.isa&#10;issueToExecuteDelay=1&#10;issueWidth=8&#10;itb=system.cpu5.itb&#10;max_insts_all_threads=0&#10;max_insts_any_thread=0&#10;&#10;eedsTSO=false&#10;&#10;umIQEntries=64&#10;&#10;umPhysCCRegs=1280&#10;&#10;umPhysFloatRegs=256&#10;&#10;umPhysIntRegs=256&#10;&#10;umPhysVecPredRegs=32&#10;&#10;umPhysVecRegs=256&#10;&#10;umROBEntries=192&#10;&#10;umRobs=1&#10;&#10;umThreads=1&#10;power_gating_on_idle=false&#10;power_model=&#10;power_state=system.cpu5.power_state&#10;profile=0&#10;progress_interval=0&#10;pwr_gating_latency=300&#10;&#13;enameToDecodeDelay=1&#10;&#13;enameToFetchDelay=1&#10;&#13;enameToIEWDelay=2&#10;&#13;enameToROBDelay=1&#10;&#13;enameWidth=8&#10;simpoint_start_insts=&#10;smtCommitPolicy=RoundRobin&#10;smtFetchPolicy=SingleThread&#10;smtIQPolicy=Partitioned&#10;smtIQThreshold=100&#10;smtLSQPolicy=Partitioned&#10;smtLSQThreshold=100&#10;smtNumFetchingThreads=1&#10;smtROBPolicy=Partitioned&#10;smtROBThreshold=100&#10;socket_id=0&#10;squashWidth=8&#10;store_set_clear_period=250000&#10;switched_out=false&#10;syscallRetryLatency=10000&#10;system=system&#10;tracer=system.cpu5.tracer&#10;trapLatency=13&#10;wait_for_remote_gdb=false&#10;wbWidth=8&#10;workload=">
<path fill="#bbc6d9" stroke="#000000" d="M4748,-24C4748,-24 5232,-24 5232,-24 5238,-24 5244,-30 5244,-36 5244,-36 5244,-334 5244,-334 5244,-340 5238,-346 5232,-346 5232,-346 4748,-346 4748,-346 4742,-346 4736,-340 4736,-334 4736,-334 4736,-36 4736,-36 4736,-30 4742,-24 4748,-24"/>
<text text-anchor="middle" x="4990" y="-330.8" font-family="Arial" font-size="14.00" fill="#000000">cpu5 </text>
<text text-anchor="middle" x="4990" y="-315.8" font-family="Arial" font-size="14.00" fill="#000000">: DerivO3CPU</text>
</a>
</g>
</g>
<g id="clust566" class="cluster">
<title>cluster_system_cpu5_icache</title>
<g id="a_clust566"><a xlink:title="addr_ranges=0:18446744073709551615&#10;assoc=2&#10;clk_domain=system.cpu_clk_domain&#10;clusivity=mostly_incl&#10;compressor=Null&#10;data_latency=2&#10;demand_mshr_reserve=1&#10;eventq_index=0&#10;is_read_only=true&#10;max_miss_count=0&#10;mshrs=4&#10;power_model=&#10;power_state=system.cpu5.icache.power_state&#10;prefetch_on_access=false&#10;prefetcher=Null&#10;&#13;eplacement_policy=system.cpu5.icache.replacement_policy&#10;&#13;esponse_latency=2&#10;sequential_access=false&#10;size=32768&#10;system=system&#10;tag_latency=2&#10;tags=system.cpu5.icache.tags&#10;tgts_per_mshr=20&#10;warmup_percentage=0&#10;write_allocator=Null&#10;write_buffers=8&#10;writeback_clean=true">
<path fill="#bab6ae" stroke="#000000" d="M4756,-32C4756,-32 4918,-32 4918,-32 4924,-32 4930,-38 4930,-44 4930,-44 4930,-111 4930,-111 4930,-117 4924,-123 4918,-123 4918,-123 4756,-123 4756,-123 4750,-123 4744,-117 4744,-111 4744,-111 4744,-44 4744,-44 4744,-38 4750,-32 4756,-32"/>
<text text-anchor="middle" x="4837" y="-107.8" font-family="Arial" font-size="14.00" fill="#000000">icache </text>
<text text-anchor="middle" x="4837" y="-92.8" font-family="Arial" font-size="14.00" fill="#000000">: L1_ICache</text>
</a>
</g>
</g>
<g id="clust630" class="cluster">
<title>cluster_system_cpu5_dtb</title>
<g id="a_clust630"><a xlink:title="eventq_index=0&#10;is_stage2=false&#10;size=64&#10;sys=system&#10;walker=system.cpu5.dtb.walker">
<path fill="#bab6ae" stroke="#000000" d="M5108,-155C5108,-155 5224,-155 5224,-155 5230,-155 5236,-161 5236,-167 5236,-167 5236,-288 5236,-288 5236,-294 5230,-300 5224,-300 5224,-300 5108,-300 5108,-300 5102,-300 5096,-294 5096,-288 5096,-288 5096,-167 5096,-167 5096,-161 5102,-155 5108,-155"/>
<text text-anchor="middle" x="5166" y="-284.8" font-family="Arial" font-size="14.00" fill="#000000">dtb </text>
<text text-anchor="middle" x="5166" y="-269.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmDTB</text>
</a>
</g>
</g>
<g id="clust631" class="cluster">
<title>cluster_system_cpu5_dtb_walker</title>
<g id="a_clust631"><a xlink:title="clk_domain=system.cpu_clk_domain&#10;eventq_index=0&#10;is_stage2=false&#10;&#10;um_squash_per_cycle=2&#10;power_model=&#10;power_state=system.cpu5.dtb.walker.power_state&#10;sys=system">
<path fill="#9f9c95" stroke="#000000" d="M5116,-163C5116,-163 5216,-163 5216,-163 5222,-163 5228,-169 5228,-175 5228,-175 5228,-242 5228,-242 5228,-248 5222,-254 5216,-254 5216,-254 5116,-254 5116,-254 5110,-254 5104,-248 5104,-242 5104,-242 5104,-175 5104,-175 5104,-169 5110,-163 5116,-163"/>
<text text-anchor="middle" x="5166" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
<text text-anchor="middle" x="5166" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
</a>
</g>
</g>
<g id="clust638" class="cluster">
<title>cluster_system_cpu5_itb</title>
<g id="a_clust638"><a xlink:title="eventq_index=0&#10;is_stage2=false&#10;size=64&#10;sys=system&#10;walker=system.cpu5.itb.walker">
<path fill="#bab6ae" stroke="#000000" d="M4960,-155C4960,-155 5076,-155 5076,-155 5082,-155 5088,-161 5088,-167 5088,-167 5088,-288 5088,-288 5088,-294 5082,-300 5076,-300 5076,-300 4960,-300 4960,-300 4954,-300 4948,-294 4948,-288 4948,-288 4948,-167 4948,-167 4948,-161 4954,-155 4960,-155"/>
<text text-anchor="middle" x="5018" y="-284.8" font-family="Arial" font-size="14.00" fill="#000000">itb </text>
<text text-anchor="middle" x="5018" y="-269.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmITB</text>
</a>
</g>
</g>
<g id="clust639" class="cluster">
<title>cluster_system_cpu5_itb_walker</title>
<g id="a_clust639"><a xlink:title="clk_domain=system.cpu_clk_domain&#10;eventq_index=0&#10;is_stage2=false&#10;&#10;um_squash_per_cycle=2&#10;power_model=&#10;power_state=system.cpu5.itb.walker.power_state&#10;sys=system">
<path fill="#9f9c95" stroke="#000000" d="M4968,-163C4968,-163 5068,-163 5068,-163 5074,-163 5080,-169 5080,-175 5080,-175 5080,-242 5080,-242 5080,-248 5074,-254 5068,-254 5068,-254 4968,-254 4968,-254 4962,-254 4956,-248 4956,-242 4956,-242 4956,-175 4956,-175 4956,-169 4962,-163 4968,-163"/>
<text text-anchor="middle" x="5018" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
<text text-anchor="middle" x="5018" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
</a>
</g>
</g>
<g id="clust645" class="cluster">
<title>cluster_system_cpu5_dcache</title>
<g id="a_clust645"><a xlink:title="addr_ranges=0:18446744073709551615&#10;assoc=2&#10;clk_domain=system.cpu_clk_domain&#10;clusivity=mostly_incl&#10;compressor=Null&#10;data_latency=2&#10;demand_mshr_reserve=1&#10;eventq_index=0&#10;is_read_only=false&#10;max_miss_count=0&#10;mshrs=4&#10;power_model=&#10;power_state=system.cpu5.dcache.power_state&#10;prefetch_on_access=false&#10;prefetcher=Null&#10;&#13;eplacement_policy=system.cpu5.dcache.replacement_policy&#10;&#13;esponse_latency=2&#10;sequential_access=false&#10;size=65536&#10;system=system&#10;tag_latency=2&#10;tags=system.cpu5.dcache.tags&#10;tgts_per_mshr=20&#10;warmup_percentage=0&#10;write_allocator=Null&#10;write_buffers=8&#10;writeback_clean=false">
<path fill="#bab6ae" stroke="#000000" d="M5006,-32C5006,-32 5168,-32 5168,-32 5174,-32 5180,-38 5180,-44 5180,-44 5180,-111 5180,-111 5180,-117 5174,-123 5168,-123 5168,-123 5006,-123 5006,-123 5000,-123 4994,-117 4994,-111 4994,-111 4994,-44 4994,-44 4994,-38 5000,-32 5006,-32"/>
<text text-anchor="middle" x="5087" y="-107.8" font-family="Arial" font-size="14.00" fill="#000000">dcache </text>
<text text-anchor="middle" x="5087" y="-92.8" font-family="Arial" font-size="14.00" fill="#000000">: L1_DCache</text>
</a>
</g>
</g>
<g id="clust656" class="cluster">
<title>cluster_system_cpu6</title>
<g id="a_clust656"><a xlink:title="LFSTSize=1024&#10;LQEntries=32&#10;LSQCheckLoads=true&#10;LSQDepCheckShift=4&#10;SQEntries=32&#10;SSITSize=1024&#10;activity=0&#10;backComSize=5&#10;branchPred=system.cpu6.branchPred&#10;cacheLoadPorts=200&#10;cacheStorePorts=200&#10;checker=Null&#10;clk_domain=system.cpu_clk_domain&#10;commitToDecodeDelay=1&#10;commitToFetchDelay=1&#10;commitToIEWDelay=1&#10;commitToRenameDelay=1&#10;commitWidth=8&#10;cpu_id=6&#10;decodeToFetchDelay=1&#10;decodeToRenameDelay=1&#10;decodeWidth=8&#10;dispatchWidth=8&#10;do_checkpoint_insts=true&#10;do_statistics_insts=true&#10;dtb=system.cpu6.dtb&#10;eventq_index=0&#10;fetchBufferSize=64&#10;fetchQueueSize=32&#10;fetchToDecodeDelay=1&#10;fetchTrapLatency=1&#10;fetchWidth=8&#10;forwardComSize=5&#10;fuPool=system.cpu6.fuPool&#10;function_trace=false&#10;function_trace_start=0&#10;iewToCommitDelay=1&#10;iewToDecodeDelay=1&#10;iewToFetchDelay=1&#10;iewToRenameDelay=1&#10;interrupts=system.cpu6.interrupts&#10;isa=system.cpu6.isa&#10;issueToExecuteDelay=1&#10;issueWidth=8&#10;itb=system.cpu6.itb&#10;max_insts_all_threads=0&#10;max_insts_any_thread=0&#10;&#10;eedsTSO=false&#10;&#10;umIQEntries=64&#10;&#10;umPhysCCRegs=1280&#10;&#10;umPhysFloatRegs=256&#10;&#10;umPhysIntRegs=256&#10;&#10;umPhysVecPredRegs=32&#10;&#10;umPhysVecRegs=256&#10;&#10;umROBEntries=192&#10;&#10;umRobs=1&#10;&#10;umThreads=1&#10;power_gating_on_idle=false&#10;power_model=&#10;power_state=system.cpu6.power_state&#10;profile=0&#10;progress_interval=0&#10;pwr_gating_latency=300&#10;&#13;enameToDecodeDelay=1&#10;&#13;enameToFetchDelay=1&#10;&#13;enameToIEWDelay=2&#10;&#13;enameToROBDelay=1&#10;&#13;enameWidth=8&#10;simpoint_start_insts=&#10;smtCommitPolicy=RoundRobin&#10;smtFetchPolicy=SingleThread&#10;smtIQPolicy=Partitioned&#10;smtIQThreshold=100&#10;smtLSQPolicy=Partitioned&#10;smtLSQThreshold=100&#10;smtNumFetchingThreads=1&#10;smtROBPolicy=Partitioned&#10;smtROBThreshold=100&#10;socket_id=0&#10;squashWidth=8&#10;store_set_clear_period=250000&#10;switched_out=false&#10;syscallRetryLatency=10000&#10;system=system&#10;tracer=system.cpu6.tracer&#10;trapLatency=13&#10;wait_for_remote_gdb=false&#10;wbWidth=8&#10;workload=">
<path fill="#bbc6d9" stroke="#000000" d="M948,-24C948,-24 1432,-24 1432,-24 1438,-24 1444,-30 1444,-36 1444,-36 1444,-334 1444,-334 1444,-340 1438,-346 1432,-346 1432,-346 948,-346 948,-346 942,-346 936,-340 936,-334 936,-334 936,-36 936,-36 936,-30 942,-24 948,-24"/>
<text text-anchor="middle" x="1190" y="-330.8" font-family="Arial" font-size="14.00" fill="#000000">cpu6 </text>
<text text-anchor="middle" x="1190" y="-315.8" font-family="Arial" font-size="14.00" fill="#000000">: DerivO3CPU</text>
</a>
</g>
</g>
<g id="clust657" class="cluster">
<title>cluster_system_cpu6_icache</title>
<g id="a_clust657"><a xlink:title="addr_ranges=0:18446744073709551615&#10;assoc=2&#10;clk_domain=system.cpu_clk_domain&#10;clusivity=mostly_incl&#10;compressor=Null&#10;data_latency=2&#10;demand_mshr_reserve=1&#10;eventq_index=0&#10;is_read_only=true&#10;max_miss_count=0&#10;mshrs=4&#10;power_model=&#10;power_state=system.cpu6.icache.power_state&#10;prefetch_on_access=false&#10;prefetcher=Null&#10;&#13;eplacement_policy=system.cpu6.icache.replacement_policy&#10;&#13;esponse_latency=2&#10;sequential_access=false&#10;size=32768&#10;system=system&#10;tag_latency=2&#10;tags=system.cpu6.icache.tags&#10;tgts_per_mshr=20&#10;warmup_percentage=0&#10;write_allocator=Null&#10;write_buffers=8&#10;writeback_clean=true">
<path fill="#bab6ae" stroke="#000000" d="M1234,-32C1234,-32 1396,-32 1396,-32 1402,-32 1408,-38 1408,-44 1408,-44 1408,-111 1408,-111 1408,-117 1402,-123 1396,-123 1396,-123 1234,-123 1234,-123 1228,-123 1222,-117 1222,-111 1222,-111 1222,-44 1222,-44 1222,-38 1228,-32 1234,-32"/>
<text text-anchor="middle" x="1315" y="-107.8" font-family="Arial" font-size="14.00" fill="#000000">icache </text>
<text text-anchor="middle" x="1315" y="-92.8" font-family="Arial" font-size="14.00" fill="#000000">: L1_ICache</text>
</a>
</g>
</g>
<g id="clust721" class="cluster">
<title>cluster_system_cpu6_dtb</title>
<g id="a_clust721"><a xlink:title="eventq_index=0&#10;is_stage2=false&#10;size=64&#10;sys=system&#10;walker=system.cpu6.dtb.walker">
<path fill="#bab6ae" stroke="#000000" d="M1308,-155C1308,-155 1424,-155 1424,-155 1430,-155 1436,-161 1436,-167 1436,-167 1436,-288 1436,-288 1436,-294 1430,-300 1424,-300 1424,-300 1308,-300 1308,-300 1302,-300 1296,-294 1296,-288 1296,-288 1296,-167 1296,-167 1296,-161 1302,-155 1308,-155"/>
<text text-anchor="middle" x="1366" y="-284.8" font-family="Arial" font-size="14.00" fill="#000000">dtb </text>
<text text-anchor="middle" x="1366" y="-269.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmDTB</text>
</a>
</g>
</g>
<g id="clust722" class="cluster">
<title>cluster_system_cpu6_dtb_walker</title>
<g id="a_clust722"><a xlink:title="clk_domain=system.cpu_clk_domain&#10;eventq_index=0&#10;is_stage2=false&#10;&#10;um_squash_per_cycle=2&#10;power_model=&#10;power_state=system.cpu6.dtb.walker.power_state&#10;sys=system">
<path fill="#9f9c95" stroke="#000000" d="M1316,-163C1316,-163 1416,-163 1416,-163 1422,-163 1428,-169 1428,-175 1428,-175 1428,-242 1428,-242 1428,-248 1422,-254 1416,-254 1416,-254 1316,-254 1316,-254 1310,-254 1304,-248 1304,-242 1304,-242 1304,-175 1304,-175 1304,-169 1310,-163 1316,-163"/>
<text text-anchor="middle" x="1366" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
<text text-anchor="middle" x="1366" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
</a>
</g>
</g>
<g id="clust729" class="cluster">
<title>cluster_system_cpu6_itb</title>
<g id="a_clust729"><a xlink:title="eventq_index=0&#10;is_stage2=false&#10;size=64&#10;sys=system&#10;walker=system.cpu6.itb.walker">
<path fill="#bab6ae" stroke="#000000" d="M1160,-155C1160,-155 1276,-155 1276,-155 1282,-155 1288,-161 1288,-167 1288,-167 1288,-288 1288,-288 1288,-294 1282,-300 1276,-300 1276,-300 1160,-300 1160,-300 1154,-300 1148,-294 1148,-288 1148,-288 1148,-167 1148,-167 1148,-161 1154,-155 1160,-155"/>
<text text-anchor="middle" x="1218" y="-284.8" font-family="Arial" font-size="14.00" fill="#000000">itb </text>
<text text-anchor="middle" x="1218" y="-269.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmITB</text>
</a>
</g>
</g>
<g id="clust730" class="cluster">
<title>cluster_system_cpu6_itb_walker</title>
<g id="a_clust730"><a xlink:title="clk_domain=system.cpu_clk_domain&#10;eventq_index=0&#10;is_stage2=false&#10;&#10;um_squash_per_cycle=2&#10;power_model=&#10;power_state=system.cpu6.itb.walker.power_state&#10;sys=system">
<path fill="#9f9c95" stroke="#000000" d="M1168,-163C1168,-163 1268,-163 1268,-163 1274,-163 1280,-169 1280,-175 1280,-175 1280,-242 1280,-242 1280,-248 1274,-254 1268,-254 1268,-254 1168,-254 1168,-254 1162,-254 1156,-248 1156,-242 1156,-242 1156,-175 1156,-175 1156,-169 1162,-163 1168,-163"/>
<text text-anchor="middle" x="1218" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
<text text-anchor="middle" x="1218" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
</a>
</g>
</g>
<g id="clust736" class="cluster">
<title>cluster_system_cpu6_dcache</title>
<g id="a_clust736"><a xlink:title="addr_ranges=0:18446744073709551615&#10;assoc=2&#10;clk_domain=system.cpu_clk_domain&#10;clusivity=mostly_incl&#10;compressor=Null&#10;data_latency=2&#10;demand_mshr_reserve=1&#10;eventq_index=0&#10;is_read_only=false&#10;max_miss_count=0&#10;mshrs=4&#10;power_model=&#10;power_state=system.cpu6.dcache.power_state&#10;prefetch_on_access=false&#10;prefetcher=Null&#10;&#13;eplacement_policy=system.cpu6.dcache.replacement_policy&#10;&#13;esponse_latency=2&#10;sequential_access=false&#10;size=65536&#10;system=system&#10;tag_latency=2&#10;tags=system.cpu6.dcache.tags&#10;tgts_per_mshr=20&#10;warmup_percentage=0&#10;write_allocator=Null&#10;write_buffers=8&#10;writeback_clean=false">
<path fill="#bab6ae" stroke="#000000" d="M985,-32C985,-32 1147,-32 1147,-32 1153,-32 1159,-38 1159,-44 1159,-44 1159,-111 1159,-111 1159,-117 1153,-123 1147,-123 1147,-123 985,-123 985,-123 979,-123 973,-117 973,-111 973,-111 973,-44 973,-44 973,-38 979,-32 985,-32"/>
<text text-anchor="middle" x="1066" y="-107.8" font-family="Arial" font-size="14.00" fill="#000000">dcache </text>
<text text-anchor="middle" x="1066" y="-92.8" font-family="Arial" font-size="14.00" fill="#000000">: L1_DCache</text>
</a>
</g>
</g>
<g id="clust747" class="cluster">
<title>cluster_system_cpu7</title>
<g id="a_clust747"><a xlink:title="LFSTSize=1024&#10;LQEntries=32&#10;LSQCheckLoads=true&#10;LSQDepCheckShift=4&#10;SQEntries=32&#10;SSITSize=1024&#10;activity=0&#10;backComSize=5&#10;branchPred=system.cpu7.branchPred&#10;cacheLoadPorts=200&#10;cacheStorePorts=200&#10;checker=Null&#10;clk_domain=system.cpu_clk_domain&#10;commitToDecodeDelay=1&#10;commitToFetchDelay=1&#10;commitToIEWDelay=1&#10;commitToRenameDelay=1&#10;commitWidth=8&#10;cpu_id=7&#10;decodeToFetchDelay=1&#10;decodeToRenameDelay=1&#10;decodeWidth=8&#10;dispatchWidth=8&#10;do_checkpoint_insts=true&#10;do_statistics_insts=true&#10;dtb=system.cpu7.dtb&#10;eventq_index=0&#10;fetchBufferSize=64&#10;fetchQueueSize=32&#10;fetchToDecodeDelay=1&#10;fetchTrapLatency=1&#10;fetchWidth=8&#10;forwardComSize=5&#10;fuPool=system.cpu7.fuPool&#10;function_trace=false&#10;function_trace_start=0&#10;iewToCommitDelay=1&#10;iewToDecodeDelay=1&#10;iewToFetchDelay=1&#10;iewToRenameDelay=1&#10;interrupts=system.cpu7.interrupts&#10;isa=system.cpu7.isa&#10;issueToExecuteDelay=1&#10;issueWidth=8&#10;itb=system.cpu7.itb&#10;max_insts_all_threads=0&#10;max_insts_any_thread=0&#10;&#10;eedsTSO=false&#10;&#10;umIQEntries=64&#10;&#10;umPhysCCRegs=1280&#10;&#10;umPhysFloatRegs=256&#10;&#10;umPhysIntRegs=256&#10;&#10;umPhysVecPredRegs=32&#10;&#10;umPhysVecRegs=256&#10;&#10;umROBEntries=192&#10;&#10;umRobs=1&#10;&#10;umThreads=1&#10;power_gating_on_idle=false&#10;power_model=&#10;power_state=system.cpu7.power_state&#10;profile=0&#10;progress_interval=0&#10;pwr_gating_latency=300&#10;&#13;enameToDecodeDelay=1&#10;&#13;enameToFetchDelay=1&#10;&#13;enameToIEWDelay=2&#10;&#13;enameToROBDelay=1&#10;&#13;enameWidth=8&#10;simpoint_start_insts=&#10;smtCommitPolicy=RoundRobin&#10;smtFetchPolicy=SingleThread&#10;smtIQPolicy=Partitioned&#10;smtIQThreshold=100&#10;smtLSQPolicy=Partitioned&#10;smtLSQThreshold=100&#10;smtNumFetchingThreads=1&#10;smtROBPolicy=Partitioned&#10;smtROBThreshold=100&#10;socket_id=0&#10;squashWidth=8&#10;store_set_clear_period=250000&#10;switched_out=false&#10;syscallRetryLatency=10000&#10;system=system&#10;tracer=system.cpu7.tracer&#10;trapLatency=13&#10;wait_for_remote_gdb=false&#10;wbWidth=8&#10;workload=">
<path fill="#bbc6d9" stroke="#000000" d="M1488,-24C1488,-24 1972,-24 1972,-24 1978,-24 1984,-30 1984,-36 1984,-36 1984,-334 1984,-334 1984,-340 1978,-346 1972,-346 1972,-346 1488,-346 1488,-346 1482,-346 1476,-340 1476,-334 1476,-334 1476,-36 1476,-36 1476,-30 1482,-24 1488,-24"/>
<text text-anchor="middle" x="1730" y="-330.8" font-family="Arial" font-size="14.00" fill="#000000">cpu7 </text>
<text text-anchor="middle" x="1730" y="-315.8" font-family="Arial" font-size="14.00" fill="#000000">: DerivO3CPU</text>
</a>
</g>
</g>
<g id="clust748" class="cluster">
<title>cluster_system_cpu7_icache</title>
<g id="a_clust748"><a xlink:title="addr_ranges=0:18446744073709551615&#10;assoc=2&#10;clk_domain=system.cpu_clk_domain&#10;clusivity=mostly_incl&#10;compressor=Null&#10;data_latency=2&#10;demand_mshr_reserve=1&#10;eventq_index=0&#10;is_read_only=true&#10;max_miss_count=0&#10;mshrs=4&#10;power_model=&#10;power_state=system.cpu7.icache.power_state&#10;prefetch_on_access=false&#10;prefetcher=Null&#10;&#13;eplacement_policy=system.cpu7.icache.replacement_policy&#10;&#13;esponse_latency=2&#10;sequential_access=false&#10;size=32768&#10;system=system&#10;tag_latency=2&#10;tags=system.cpu7.icache.tags&#10;tgts_per_mshr=20&#10;warmup_percentage=0&#10;write_allocator=Null&#10;write_buffers=8&#10;writeback_clean=true">
<path fill="#bab6ae" stroke="#000000" d="M1774,-32C1774,-32 1936,-32 1936,-32 1942,-32 1948,-38 1948,-44 1948,-44 1948,-111 1948,-111 1948,-117 1942,-123 1936,-123 1936,-123 1774,-123 1774,-123 1768,-123 1762,-117 1762,-111 1762,-111 1762,-44 1762,-44 1762,-38 1768,-32 1774,-32"/>
<text text-anchor="middle" x="1855" y="-107.8" font-family="Arial" font-size="14.00" fill="#000000">icache </text>
<text text-anchor="middle" x="1855" y="-92.8" font-family="Arial" font-size="14.00" fill="#000000">: L1_ICache</text>
</a>
</g>
</g>
<g id="clust812" class="cluster">
<title>cluster_system_cpu7_dtb</title>
<g id="a_clust812"><a xlink:title="eventq_index=0&#10;is_stage2=false&#10;size=64&#10;sys=system&#10;walker=system.cpu7.dtb.walker">
<path fill="#bab6ae" stroke="#000000" d="M1848,-155C1848,-155 1964,-155 1964,-155 1970,-155 1976,-161 1976,-167 1976,-167 1976,-288 1976,-288 1976,-294 1970,-300 1964,-300 1964,-300 1848,-300 1848,-300 1842,-300 1836,-294 1836,-288 1836,-288 1836,-167 1836,-167 1836,-161 1842,-155 1848,-155"/>
<text text-anchor="middle" x="1906" y="-284.8" font-family="Arial" font-size="14.00" fill="#000000">dtb </text>
<text text-anchor="middle" x="1906" y="-269.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmDTB</text>
</a>
</g>
</g>
<g id="clust813" class="cluster">
<title>cluster_system_cpu7_dtb_walker</title>
<g id="a_clust813"><a xlink:title="clk_domain=system.cpu_clk_domain&#10;eventq_index=0&#10;is_stage2=false&#10;&#10;um_squash_per_cycle=2&#10;power_model=&#10;power_state=system.cpu7.dtb.walker.power_state&#10;sys=system">
<path fill="#9f9c95" stroke="#000000" d="M1856,-163C1856,-163 1956,-163 1956,-163 1962,-163 1968,-169 1968,-175 1968,-175 1968,-242 1968,-242 1968,-248 1962,-254 1956,-254 1956,-254 1856,-254 1856,-254 1850,-254 1844,-248 1844,-242 1844,-242 1844,-175 1844,-175 1844,-169 1850,-163 1856,-163"/>
<text text-anchor="middle" x="1906" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
<text text-anchor="middle" x="1906" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
</a>
</g>
</g>
<g id="clust820" class="cluster">
<title>cluster_system_cpu7_itb</title>
<g id="a_clust820"><a xlink:title="eventq_index=0&#10;is_stage2=false&#10;size=64&#10;sys=system&#10;walker=system.cpu7.itb.walker">
<path fill="#bab6ae" stroke="#000000" d="M1700,-155C1700,-155 1816,-155 1816,-155 1822,-155 1828,-161 1828,-167 1828,-167 1828,-288 1828,-288 1828,-294 1822,-300 1816,-300 1816,-300 1700,-300 1700,-300 1694,-300 1688,-294 1688,-288 1688,-288 1688,-167 1688,-167 1688,-161 1694,-155 1700,-155"/>
<text text-anchor="middle" x="1758" y="-284.8" font-family="Arial" font-size="14.00" fill="#000000">itb </text>
<text text-anchor="middle" x="1758" y="-269.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmITB</text>
</a>
</g>
</g>
<g id="clust821" class="cluster">
<title>cluster_system_cpu7_itb_walker</title>
<g id="a_clust821"><a xlink:title="clk_domain=system.cpu_clk_domain&#10;eventq_index=0&#10;is_stage2=false&#10;&#10;um_squash_per_cycle=2&#10;power_model=&#10;power_state=system.cpu7.itb.walker.power_state&#10;sys=system">
<path fill="#9f9c95" stroke="#000000" d="M1708,-163C1708,-163 1808,-163 1808,-163 1814,-163 1820,-169 1820,-175 1820,-175 1820,-242 1820,-242 1820,-248 1814,-254 1808,-254 1808,-254 1708,-254 1708,-254 1702,-254 1696,-248 1696,-242 1696,-242 1696,-175 1696,-175 1696,-169 1702,-163 1708,-163"/>
<text text-anchor="middle" x="1758" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
<text text-anchor="middle" x="1758" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
</a>
</g>
</g>
<g id="clust827" class="cluster">
<title>cluster_system_cpu7_dcache</title>
<g id="a_clust827"><a xlink:title="addr_ranges=0:18446744073709551615&#10;assoc=2&#10;clk_domain=system.cpu_clk_domain&#10;clusivity=mostly_incl&#10;compressor=Null&#10;data_latency=2&#10;demand_mshr_reserve=1&#10;eventq_index=0&#10;is_read_only=false&#10;max_miss_count=0&#10;mshrs=4&#10;power_model=&#10;power_state=system.cpu7.dcache.power_state&#10;prefetch_on_access=false&#10;prefetcher=Null&#10;&#13;eplacement_policy=system.cpu7.dcache.replacement_policy&#10;&#13;esponse_latency=2&#10;sequential_access=false&#10;size=65536&#10;system=system&#10;tag_latency=2&#10;tags=system.cpu7.dcache.tags&#10;tgts_per_mshr=20&#10;warmup_percentage=0&#10;write_allocator=Null&#10;write_buffers=8&#10;writeback_clean=false">
<path fill="#bab6ae" stroke="#000000" d="M1525,-32C1525,-32 1687,-32 1687,-32 1693,-32 1699,-38 1699,-44 1699,-44 1699,-111 1699,-111 1699,-117 1693,-123 1687,-123 1687,-123 1525,-123 1525,-123 1519,-123 1513,-117 1513,-111 1513,-111 1513,-44 1513,-44 1513,-38 1519,-32 1525,-32"/>
<text text-anchor="middle" x="1606" y="-107.8" font-family="Arial" font-size="14.00" fill="#000000">dcache </text>
<text text-anchor="middle" x="1606" y="-92.8" font-family="Arial" font-size="14.00" fill="#000000">: L1_DCache</text>
</a>
</g>
</g>
<g id="clust839" class="cluster">
<title>cluster_system_l2</title>
<g id="a_clust839"><a xlink:title="addr_ranges=0:18446744073709551615&#10;assoc=8&#10;clk_domain=system.cpu_clk_domain&#10;clusivity=mostly_incl&#10;compressor=Null&#10;data_latency=20&#10;demand_mshr_reserve=1&#10;eventq_index=0&#10;is_read_only=false&#10;max_miss_count=0&#10;mshrs=20&#10;power_model=&#10;power_state=system.l2.power_state&#10;prefetch_on_access=false&#10;prefetcher=Null&#10;&#13;eplacement_policy=system.l2.replacement_policy&#10;&#13;esponse_latency=20&#10;sequential_access=false&#10;size=2097152&#10;system=system&#10;tag_latency=20&#10;tags=system.l2.tags&#10;tgts_per_mshr=12&#10;warmup_percentage=0&#10;write_allocator=Null&#10;write_buffers=8&#10;writeback_clean=false">
<path fill="#bab6ae" stroke="#000000" d="M754,-163C754,-163 916,-163 916,-163 922,-163 928,-169 928,-175 928,-175 928,-242 928,-242 928,-248 922,-254 916,-254 916,-254 754,-254 754,-254 748,-254 742,-248 742,-242 742,-242 742,-175 742,-175 742,-169 748,-163 754,-163"/>
<text text-anchor="middle" x="835" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">l2 </text>
<text text-anchor="middle" x="835" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: L2Cache</text>
</a>
</g>
</g>
<g id="clust846" class="cluster">
<title>cluster_system_mem_ctrls</title>
<g id="a_clust846"><a xlink:title="IDD0=0.055&#10;IDD02=0.0&#10;IDD2N=0.032&#10;IDD2N2=0.0&#10;IDD2P0=0.0&#10;IDD2P02=0.0&#10;IDD2P1=0.032&#10;IDD2P12=0.0&#10;IDD3N=0.038&#10;IDD3N2=0.0&#10;IDD3P0=0.0&#10;IDD3P02=0.0&#10;IDD3P1=0.038&#10;IDD3P12=0.0&#10;IDD4R=0.157&#10;IDD4R2=0.0&#10;IDD4W=0.125&#10;IDD4W2=0.0&#10;IDD5=0.235&#10;IDD52=0.0&#10;IDD6=0.02&#10;IDD62=0.0&#10;VDD=1.5&#10;VDD2=0.0&#10;activation_limit=4&#10;addr_mapping=RoRaBaCoCh&#10;bank_groups_per_rank=0&#10;banks_per_rank=8&#10;beats_per_clock=2&#10;burst_length=8&#10;clk_domain=system.clk_domain&#10;conf_table_reported=true&#10;data_clock_sync=false&#10;device_bus_width=8&#10;device_rowbuffer_size=1024&#10;device_size=536870912&#10;devices_per_rank=8&#10;dll=true&#10;enable_dram_powerdown=false&#10;eventq_index=0&#10;image_file=&#10;in_addr_map=true&#10;kvm_map=true&#10;max_accesses_per_row=16&#10;mem_sched_policy=frfcfs&#10;min_writes_per_switch=16&#10;&#10;ull=false&#10;page_policy=open_adaptive&#10;power_model=&#10;power_state=system.mem_ctrls.power_state&#10;qos_masters= &#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#10;qos_policy=Null&#10;qos_priorities=1&#10;qos_priority_escalation=false&#10;qos_q_policy=fifo&#10;qos_syncro_scheduler=false&#10;qos_turnaround_policy=Null&#10;&#13;ange=2147483648:2415919104&#10;&#13;anks_per_channel=2&#10;&#13;ead_buffer_size=32&#10;static_backend_latency=10000&#10;static_frontend_latency=10000&#10;tAAD=1250&#10;tBURST=5000&#10;tBURST_MAX=5000&#10;tBURST_MIN=5000&#10;tCCD_L=0&#10;tCCD_L_WR=0&#10;tCK=1250&#10;tCL=13750&#10;tCS=2500&#10;tPPD=0&#10;tRAS=35000&#10;tRCD=13750&#10;tREFI=7800000&#10;tRFC=260000&#10;tRP=13750&#10;tRRD=6000&#10;tRRD_L=0&#10;tRTP=7500&#10;tRTW=2500&#10;tWR=15000&#10;tWTR=7500&#10;tWTR_L=7500&#10;tXAW=30000&#10;tXP=6000&#10;tXPDLL=0&#10;tXS=270000&#10;tXSDLL=0&#10;two_cycle_activate=false&#10;write_buffer_size=64&#10;write_high_thresh_perc=85&#10;write_low_thresh_perc=50">
<path fill="#5e5958" stroke="#000000" d="M268,-163C268,-163 372,-163 372,-163 378,-163 384,-169 384,-175 384,-175 384,-242 384,-242 384,-248 378,-254 372,-254 372,-254 268,-254 268,-254 262,-254 256,-248 256,-242 256,-242 256,-175 256,-175 256,-169 262,-163 268,-163"/>
<text text-anchor="middle" x="320" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">mem_ctrls </text>
<text text-anchor="middle" x="320" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: DDR3_1600_8x8</text>
</a>
</g>
</g>
<g id="clust849" class="cluster">
<title>cluster_system_iobus</title>
<g id="a_clust849"><a xlink:title="clk_domain=system.clk_domain&#10;eventq_index=0&#10;forward_latency=1&#10;frontend_latency=2&#10;header_latency=1&#10;power_model=&#10;power_state=system.iobus.power_state&#10;&#13;esponse_latency=2&#10;use_default_range=false&#10;width=16">
<path fill="#6f798c" stroke="#000000" d="M2140,-354C2140,-354 2264,-354 2264,-354 2270,-354 2276,-360 2276,-366 2276,-366 2276,-433 2276,-433 2276,-439 2270,-445 2264,-445 2264,-445 2140,-445 2140,-445 2134,-445 2128,-439 2128,-433 2128,-433 2128,-366 2128,-366 2128,-360 2134,-354 2140,-354"/>
<text text-anchor="middle" x="2202" y="-429.8" font-family="Arial" font-size="14.00" fill="#000000">iobus </text>
<text text-anchor="middle" x="2202" y="-414.8" font-family="Arial" font-size="14.00" fill="#000000">: IOXBar</text>
</a>
</g>
</g>
<g id="clust852" class="cluster">
<title>cluster_system_pci_ide</title>
<g id="a_clust852"><a xlink:title="BAR0=1&#10;BAR0LegacyIO=false&#10;BAR0Size=8&#10;BAR1=1&#10;BAR1LegacyIO=false&#10;BAR1Size=4&#10;BAR2=1&#10;BAR2LegacyIO=false&#10;BAR2Size=8&#10;BAR3=1&#10;BAR3LegacyIO=false&#10;BAR3Size=4&#10;BAR4=1&#10;BAR4LegacyIO=false&#10;BAR4Size=16&#10;BAR5=1&#10;BAR5LegacyIO=false&#10;BAR5Size=0&#10;BIST=0&#10;CacheLineSize=0&#10;CapabilityPtr=0&#10;CardbusCIS=0&#10;ClassCode=1&#10;Command=0&#10;DeviceID=28945&#10;ExpansionROM=0&#10;HeaderType=0&#10;InterruptLine=31&#10;InterruptPin=1&#10;LatencyTimer=0&#10;LegacyIOBase=0&#10;MSICAPBaseOffset=0&#10;MSICAPCapId=0&#10;MSICAPMaskBits=0&#10;MSICAPMsgAddr=0&#10;MSICAPMsgCtrl=0&#10;MSICAPMsgData=0&#10;MSICAPMsgUpperAddr=0&#10;MSICAPNextCapability=0&#10;MSICAPPendingBits=0&#10;MSIXCAPBaseOffset=0&#10;MSIXCAPCapId=0&#10;MSIXCAPNextCapability=0&#10;MSIXMsgCtrl=0&#10;MSIXPbaOffset=0&#10;MSIXTableOffset=0&#10;MaximumLatency=0&#10;MinimumGrant=0&#10;PMCAPBaseOffset=0&#10;PMCAPCapId=0&#10;PMCAPCapabilities=0&#10;PMCAPCtrlStatus=0&#10;PMCAPNextCapability=0&#10;PXCAPBaseOffset=0&#10;PXCAPCapId=0&#10;PXCAPCapabilities=0&#10;PXCAPDevCap2=0&#10;PXCAPDevCapabilities=0&#10;PXCAPDevCtrl=0&#10;PXCAPDevCtrl2=0&#10;PXCAPDevStatus=0&#10;PXCAPLinkCap=0&#10;PXCAPLinkCtrl=0&#10;PXCAPLinkStatus=0&#10;PXCAPNextCapability=0&#10;ProgIF=133&#10;Revision=0&#10;Status=640&#10;SubClassCode=1&#10;SubsystemID=0&#10;SubsystemVendorID=0&#10;VendorID=32902&#10;clk_domain=system.clk_domain&#10;config_latency=20000&#10;ctrl_offset=0&#10;disks=system.pci_ide.disks&#10;eventq_index=0&#10;host=system.realview.pci_host&#10;io_shift=0&#10;pci_bus=0&#10;pci_dev=1&#10;pci_func=0&#10;pio_latency=30000&#10;power_model=&#10;power_state=system.pci_ide.power_state&#10;sid=0&#10;ssid=0&#10;system=system">
<path fill="#c7a793" stroke="#000000" d="M3020,-485C3020,-485 3138,-485 3138,-485 3144,-485 3150,-491 3150,-497 3150,-497 3150,-564 3150,-564 3150,-570 3144,-576 3138,-576 3138,-576 3020,-576 3020,-576 3014,-576 3008,-570 3008,-564 3008,-564 3008,-497 3008,-497 3008,-491 3014,-485 3020,-485"/>
<text text-anchor="middle" x="3079" y="-560.8" font-family="Arial" font-size="14.00" fill="#000000">pci_ide </text>
<text text-anchor="middle" x="3079" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">: IdeController</text>
</a>
</g>
</g>
<g id="clust857" class="cluster">
<title>cluster_system_iocache</title>
<g id="a_clust857"><a xlink:title="addr_ranges=2147483648:2415919104&#10;assoc=8&#10;clk_domain=system.clk_domain&#10;clusivity=mostly_incl&#10;compressor=Null&#10;data_latency=50&#10;demand_mshr_reserve=1&#10;eventq_index=0&#10;is_read_only=false&#10;max_miss_count=0&#10;mshrs=20&#10;power_model=&#10;power_state=system.iocache.power_state&#10;prefetch_on_access=false&#10;prefetcher=Null&#10;&#13;eplacement_policy=system.iocache.replacement_policy&#10;&#13;esponse_latency=50&#10;sequential_access=false&#10;size=1024&#10;system=system&#10;tag_latency=50&#10;tags=system.iocache.tags&#10;tgts_per_mshr=12&#10;warmup_percentage=0&#10;write_allocator=Null&#10;write_buffers=8&#10;writeback_clean=false">
<path fill="#bab6ae" stroke="#000000" d="M560,-163C560,-163 722,-163 722,-163 728,-163 734,-169 734,-175 734,-175 734,-242 734,-242 734,-248 728,-254 722,-254 722,-254 560,-254 560,-254 554,-254 548,-248 548,-242 548,-242 548,-175 548,-175 548,-169 554,-163 560,-163"/>
<text text-anchor="middle" x="641" y="-238.8" font-family="Arial" font-size="14.00" fill="#000000">iocache </text>
<text text-anchor="middle" x="641" y="-223.8" font-family="Arial" font-size="14.00" fill="#000000">: IOCache</text>
</a>
</g>
</g>
<!-- system_system_port -->
<g id="node1" class="node">
<title>system_system_port</title>
<path fill="#b6b8bc" stroke="#000000" d="M36.5,-493.5C36.5,-493.5 103.5,-493.5 103.5,-493.5 109.5,-493.5 115.5,-499.5 115.5,-505.5 115.5,-505.5 115.5,-517.5 115.5,-517.5 115.5,-523.5 109.5,-529.5 103.5,-529.5 103.5,-529.5 36.5,-529.5 36.5,-529.5 30.5,-529.5 24.5,-523.5 24.5,-517.5 24.5,-517.5 24.5,-505.5 24.5,-505.5 24.5,-499.5 30.5,-493.5 36.5,-493.5"/>
<text text-anchor="middle" x="70" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">system_port</text>
</g>
<!-- system_membus_slave -->
<g id="node8" class="node">
<title>system_membus_slave</title>
<path fill="#586070" stroke="#000000" d="M120,-362.5C120,-362.5 150,-362.5 150,-362.5 156,-362.5 162,-368.5 162,-374.5 162,-374.5 162,-386.5 162,-386.5 162,-392.5 156,-398.5 150,-398.5 150,-398.5 120,-398.5 120,-398.5 114,-398.5 108,-392.5 108,-386.5 108,-386.5 108,-374.5 108,-374.5 108,-368.5 114,-362.5 120,-362.5"/>
<text text-anchor="middle" x="135" y="-376.8" font-family="Arial" font-size="14.00" fill="#000000">slave</text>
</g>
<!-- system_system_port&#45;&gt;system_membus_slave -->
<g id="edge1" class="edge">
<title>system_system_port&#45;&gt;system_membus_slave</title>
<path fill="none" stroke="black" d="M78.63,-493.37C89.66,-471.49 108.84,-433.41 121.73,-407.83"/>
<polygon fill="black" stroke="black" points="124.96,-409.21 126.33,-398.7 118.71,-406.06 124.96,-409.21"/>
</g>
<!-- system_tol2bus_master -->
<g id="node2" class="node">
<title>system_tol2bus_master</title>
<path fill="#586070" stroke="#000000" d="M2992.5,-362.5C2992.5,-362.5 3027.5,-362.5 3027.5,-362.5 3033.5,-362.5 3039.5,-368.5 3039.5,-374.5 3039.5,-374.5 3039.5,-386.5 3039.5,-386.5 3039.5,-392.5 3033.5,-398.5 3027.5,-398.5 3027.5,-398.5 2992.5,-398.5 2992.5,-398.5 2986.5,-398.5 2980.5,-392.5 2980.5,-386.5 2980.5,-386.5 2980.5,-374.5 2980.5,-374.5 2980.5,-368.5 2986.5,-362.5 2992.5,-362.5"/>
<text text-anchor="middle" x="3010" y="-376.8" font-family="Arial" font-size="14.00" fill="#000000">master</text>
</g>
<!-- system_l2_cpu_side -->
<g id="node103" class="node">
<title>system_l2_cpu_side</title>
<path fill="#94918b" stroke="#000000" d="M860.5,-171.5C860.5,-171.5 907.5,-171.5 907.5,-171.5 913.5,-171.5 919.5,-177.5 919.5,-183.5 919.5,-183.5 919.5,-195.5 919.5,-195.5 919.5,-201.5 913.5,-207.5 907.5,-207.5 907.5,-207.5 860.5,-207.5 860.5,-207.5 854.5,-207.5 848.5,-201.5 848.5,-195.5 848.5,-195.5 848.5,-183.5 848.5,-183.5 848.5,-177.5 854.5,-171.5 860.5,-171.5"/>
<text text-anchor="middle" x="884" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_tol2bus_master&#45;&gt;system_l2_cpu_side -->
<g id="edge2" class="edge">
<title>system_tol2bus_master&#45;&gt;system_l2_cpu_side</title>
<path fill="none" stroke="black" d="M2980.46,-378.16C2881.44,-373.74 2552.27,-359.56 2280,-354 2270.64,-353.81 939.52,-351.58 932,-346 892.12,-316.39 884.38,-254.11 883.44,-218"/>
<polygon fill="black" stroke="black" points="886.94,-217.66 883.34,-207.7 879.94,-217.73 886.94,-217.66"/>
</g>
<!-- system_tol2bus_slave -->
<g id="node3" class="node">
<title>system_tol2bus_slave</title>
<path fill="#586070" stroke="#000000" d="M3070,-362.5C3070,-362.5 3100,-362.5 3100,-362.5 3106,-362.5 3112,-368.5 3112,-374.5 3112,-374.5 3112,-386.5 3112,-386.5 3112,-392.5 3106,-398.5 3100,-398.5 3100,-398.5 3070,-398.5 3070,-398.5 3064,-398.5 3058,-392.5 3058,-386.5 3058,-386.5 3058,-374.5 3058,-374.5 3058,-368.5 3064,-362.5 3070,-362.5"/>
<text text-anchor="middle" x="3085" y="-376.8" font-family="Arial" font-size="14.00" fill="#000000">slave</text>
</g>
<!-- system_cpu0_icache_mem_side -->
<g id="node40" class="node">
<title>system_cpu0_icache_mem_side</title>
<path fill="#94918b" stroke="#000000" d="M2412,-40.5C2412,-40.5 2468,-40.5 2468,-40.5 2474,-40.5 2480,-46.5 2480,-52.5 2480,-52.5 2480,-64.5 2480,-64.5 2480,-70.5 2474,-76.5 2468,-76.5 2468,-76.5 2412,-76.5 2412,-76.5 2406,-76.5 2400,-70.5 2400,-64.5 2400,-64.5 2400,-52.5 2400,-52.5 2400,-46.5 2406,-40.5 2412,-40.5"/>
<text text-anchor="middle" x="2440" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu0_icache_mem_side -->
<g id="edge3" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu0_icache_mem_side</title>
<path fill="none" stroke="black" d="M3056.6,-357.2C3054.12,-355.94 3051.57,-354.84 3049,-354 3035.85,-349.7 2561.23,-355.32 2551,-346 2519.43,-317.25 2547.9,-193.77 2530,-155 2515,-122.53 2484.55,-93.97 2463.24,-76.73"/>
<polygon fill="black" stroke="black" points="3054.85,-360.23 3065.22,-362.35 3058.44,-354.22 3054.85,-360.23"/>
</g>
<!-- system_cpu0_dtb_walker_port -->
<g id="node42" class="node">
<title>system_cpu0_dtb_walker_port</title>
<path fill="#7f7c77" stroke="#000000" d="M2458,-171.5C2458,-171.5 2488,-171.5 2488,-171.5 2494,-171.5 2500,-177.5 2500,-183.5 2500,-183.5 2500,-195.5 2500,-195.5 2500,-201.5 2494,-207.5 2488,-207.5 2488,-207.5 2458,-207.5 2458,-207.5 2452,-207.5 2446,-201.5 2446,-195.5 2446,-195.5 2446,-183.5 2446,-183.5 2446,-177.5 2452,-171.5 2458,-171.5"/>
<text text-anchor="middle" x="2473" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu0_dtb_walker_port -->
<g id="edge6" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu0_dtb_walker_port</title>
<path fill="none" stroke="black" d="M3056.6,-357.2C3054.12,-355.93 3051.57,-354.84 3049,-354 3021.06,-344.87 2543.47,-363.7 2520,-346 2476.32,-313.05 2471.85,-240.74 2472.25,-207.65"/>
<polygon fill="black" stroke="black" points="3054.85,-360.22 3065.23,-362.35 3058.44,-354.22 3054.85,-360.22"/>
</g>
<!-- system_cpu0_itb_walker_port -->
<g id="node43" class="node">
<title>system_cpu0_itb_walker_port</title>
<path fill="#7f7c77" stroke="#000000" d="M2310,-171.5C2310,-171.5 2340,-171.5 2340,-171.5 2346,-171.5 2352,-177.5 2352,-183.5 2352,-183.5 2352,-195.5 2352,-195.5 2352,-201.5 2346,-207.5 2340,-207.5 2340,-207.5 2310,-207.5 2310,-207.5 2304,-207.5 2298,-201.5 2298,-195.5 2298,-195.5 2298,-183.5 2298,-183.5 2298,-177.5 2304,-171.5 2310,-171.5"/>
<text text-anchor="middle" x="2325" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu0_itb_walker_port -->
<g id="edge5" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu0_itb_walker_port</title>
<path fill="none" stroke="black" d="M3056.61,-357.19C3054.12,-355.93 3051.57,-354.84 3049,-354 3031.32,-348.26 2395.11,-356.82 2380,-346 2334.83,-313.66 2326.54,-241.03 2325.17,-207.75"/>
<polygon fill="black" stroke="black" points="3054.85,-360.22 3065.23,-362.34 3058.44,-354.21 3054.85,-360.22"/>
</g>
<!-- system_cpu0_dcache_mem_side -->
<g id="node44" class="node">
<title>system_cpu0_dcache_mem_side</title>
<path fill="#94918b" stroke="#000000" d="M2163,-40.5C2163,-40.5 2219,-40.5 2219,-40.5 2225,-40.5 2231,-46.5 2231,-52.5 2231,-52.5 2231,-64.5 2231,-64.5 2231,-70.5 2225,-76.5 2219,-76.5 2219,-76.5 2163,-76.5 2163,-76.5 2157,-76.5 2151,-70.5 2151,-64.5 2151,-64.5 2151,-52.5 2151,-52.5 2151,-46.5 2157,-40.5 2163,-40.5"/>
<text text-anchor="middle" x="2191" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu0_dcache_mem_side -->
<g id="edge4" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu0_dcache_mem_side</title>
<path fill="none" stroke="black" d="M3056.6,-357.2C3054.12,-355.94 3051.57,-354.84 3049,-354 3035.29,-349.52 2540.59,-355.79 2530,-346 2498.69,-317.06 2541.31,-185.96 2512,-155 2478.94,-120.09 2343.3,-139.13 2298,-123 2266.86,-111.92 2234.73,-91.4 2213.9,-76.68"/>
<polygon fill="black" stroke="black" points="3054.85,-360.22 3065.23,-362.35 3058.44,-354.22 3054.85,-360.22"/>
</g>
<!-- system_cpu1_icache_mem_side -->
<g id="node48" class="node">
<title>system_cpu1_icache_mem_side</title>
<path fill="#94918b" stroke="#000000" d="M2604,-40.5C2604,-40.5 2660,-40.5 2660,-40.5 2666,-40.5 2672,-46.5 2672,-52.5 2672,-52.5 2672,-64.5 2672,-64.5 2672,-70.5 2666,-76.5 2660,-76.5 2660,-76.5 2604,-76.5 2604,-76.5 2598,-76.5 2592,-70.5 2592,-64.5 2592,-64.5 2592,-52.5 2592,-52.5 2592,-46.5 2598,-40.5 2604,-40.5"/>
<text text-anchor="middle" x="2632" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu1_icache_mem_side -->
<g id="edge7" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu1_icache_mem_side</title>
<path fill="none" stroke="black" d="M3056.6,-357.2C3054.12,-355.94 3051.57,-354.84 3049,-354 3036.41,-349.88 2581.29,-355.45 2572,-346 2542.24,-315.74 2560.25,-195.79 2572,-155 2580.73,-124.71 2602.21,-94.74 2616.95,-76.68"/>
<polygon fill="black" stroke="black" points="3054.84,-360.23 3065.22,-362.36 3058.44,-354.22 3054.84,-360.23"/>
</g>
<!-- system_cpu1_dtb_walker_port -->
<g id="node50" class="node">
<title>system_cpu1_dtb_walker_port</title>
<path fill="#7f7c77" stroke="#000000" d="M3018,-171.5C3018,-171.5 3048,-171.5 3048,-171.5 3054,-171.5 3060,-177.5 3060,-183.5 3060,-183.5 3060,-195.5 3060,-195.5 3060,-201.5 3054,-207.5 3048,-207.5 3048,-207.5 3018,-207.5 3018,-207.5 3012,-207.5 3006,-201.5 3006,-195.5 3006,-195.5 3006,-183.5 3006,-183.5 3006,-177.5 3012,-171.5 3018,-171.5"/>
<text text-anchor="middle" x="3033" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu1_dtb_walker_port -->
<g id="edge10" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu1_dtb_walker_port</title>
<path fill="none" stroke="black" d="M3077.62,-352.67C3066.77,-313.23 3046.82,-240.73 3037.73,-207.7"/>
<polygon fill="black" stroke="black" points="3074.27,-353.68 3080.29,-362.39 3081.02,-351.82 3074.27,-353.68"/>
</g>
<!-- system_cpu1_itb_walker_port -->
<g id="node51" class="node">
<title>system_cpu1_itb_walker_port</title>
<path fill="#7f7c77" stroke="#000000" d="M2870,-171.5C2870,-171.5 2900,-171.5 2900,-171.5 2906,-171.5 2912,-177.5 2912,-183.5 2912,-183.5 2912,-195.5 2912,-195.5 2912,-201.5 2906,-207.5 2900,-207.5 2900,-207.5 2870,-207.5 2870,-207.5 2864,-207.5 2858,-201.5 2858,-195.5 2858,-195.5 2858,-183.5 2858,-183.5 2858,-177.5 2864,-171.5 2870,-171.5"/>
<text text-anchor="middle" x="2885" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu1_itb_walker_port -->
<g id="edge9" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu1_itb_walker_port</title>
<path fill="none" stroke="black" d="M3056.11,-357.13C3053.78,-355.93 3051.4,-354.86 3049,-354 3026.14,-345.79 2959.3,-360.74 2940,-346 2895.84,-312.29 2887.03,-240.37 2885.35,-207.51"/>
<polygon fill="black" stroke="black" points="3054.38,-360.18 3064.76,-362.33 3057.99,-354.18 3054.38,-360.18"/>
</g>
<!-- system_cpu1_dcache_mem_side -->
<g id="node52" class="node">
<title>system_cpu1_dcache_mem_side</title>
<path fill="#94918b" stroke="#000000" d="M2944,-40.5C2944,-40.5 3000,-40.5 3000,-40.5 3006,-40.5 3012,-46.5 3012,-52.5 3012,-52.5 3012,-64.5 3012,-64.5 3012,-70.5 3006,-76.5 3000,-76.5 3000,-76.5 2944,-76.5 2944,-76.5 2938,-76.5 2932,-70.5 2932,-64.5 2932,-64.5 2932,-52.5 2932,-52.5 2932,-46.5 2938,-40.5 2944,-40.5"/>
<text text-anchor="middle" x="2972" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu1_dcache_mem_side -->
<g id="edge8" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu1_dcache_mem_side</title>
<path fill="none" stroke="black" d="M3085.88,-352.2C3087.17,-300.26 3087.87,-189.32 3072,-155 3056.38,-121.23 3023.02,-93.34 2999.12,-76.59"/>
<polygon fill="black" stroke="black" points="3082.38,-352.25 3085.61,-362.34 3089.38,-352.44 3082.38,-352.25"/>
</g>
<!-- system_cpu2_icache_mem_side -->
<g id="node56" class="node">
<title>system_cpu2_icache_mem_side</title>
<path fill="#94918b" stroke="#000000" d="M3492,-40.5C3492,-40.5 3548,-40.5 3548,-40.5 3554,-40.5 3560,-46.5 3560,-52.5 3560,-52.5 3560,-64.5 3560,-64.5 3560,-70.5 3554,-76.5 3548,-76.5 3548,-76.5 3492,-76.5 3492,-76.5 3486,-76.5 3480,-70.5 3480,-64.5 3480,-64.5 3480,-52.5 3480,-52.5 3480,-46.5 3486,-40.5 3492,-40.5"/>
<text text-anchor="middle" x="3520" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu2_icache_mem_side -->
<g id="edge11" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu2_icache_mem_side</title>
<path fill="none" stroke="black" d="M3122.4,-379.98C3236.43,-381.04 3574.01,-381.17 3607,-346 3636.04,-315.04 3622.33,-194.58 3607,-155 3594.29,-122.16 3564.44,-93.68 3543.27,-76.57"/>
<polygon fill="black" stroke="black" points="3122.11,-376.47 3112.08,-379.87 3122.04,-383.47 3122.11,-376.47"/>
</g>
<!-- system_cpu2_dtb_walker_port -->
<g id="node58" class="node">
<title>system_cpu2_dtb_walker_port</title>
<path fill="#7f7c77" stroke="#000000" d="M3484,-171.5C3484,-171.5 3514,-171.5 3514,-171.5 3520,-171.5 3526,-177.5 3526,-183.5 3526,-183.5 3526,-195.5 3526,-195.5 3526,-201.5 3520,-207.5 3514,-207.5 3514,-207.5 3484,-207.5 3484,-207.5 3478,-207.5 3472,-201.5 3472,-195.5 3472,-195.5 3472,-183.5 3472,-183.5 3472,-177.5 3478,-171.5 3484,-171.5"/>
<text text-anchor="middle" x="3499" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu2_dtb_walker_port -->
<g id="edge14" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu2_dtb_walker_port</title>
<path fill="none" stroke="black" d="M3122.45,-378.27C3209.31,-375.08 3419.03,-365.46 3444,-346 3487.71,-311.94 3496.76,-240.53 3498.58,-207.69"/>
<polygon fill="black" stroke="black" points="3122.11,-374.78 3112.25,-378.63 3122.36,-381.77 3122.11,-374.78"/>
</g>
<!-- system_cpu2_itb_walker_port -->
<g id="node59" class="node">
<title>system_cpu2_itb_walker_port</title>
<path fill="#7f7c77" stroke="#000000" d="M3336,-171.5C3336,-171.5 3366,-171.5 3366,-171.5 3372,-171.5 3378,-177.5 3378,-183.5 3378,-183.5 3378,-195.5 3378,-195.5 3378,-201.5 3372,-207.5 3366,-207.5 3366,-207.5 3336,-207.5 3336,-207.5 3330,-207.5 3324,-201.5 3324,-195.5 3324,-195.5 3324,-183.5 3324,-183.5 3324,-177.5 3330,-171.5 3336,-171.5"/>
<text text-anchor="middle" x="3351" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu2_itb_walker_port -->
<g id="edge13" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu2_itb_walker_port</title>
<path fill="none" stroke="black" d="M3122.46,-379.25C3181.48,-378.05 3292.26,-372.25 3320,-346 3358.39,-309.67 3356.63,-240.37 3353.35,-207.99"/>
<polygon fill="black" stroke="black" points="3122.36,-375.75 3112.42,-379.42 3122.47,-382.75 3122.36,-375.75"/>
</g>
<!-- system_cpu2_dcache_mem_side -->
<g id="node60" class="node">
<title>system_cpu2_dcache_mem_side</title>
<path fill="#94918b" stroke="#000000" d="M3243,-40.5C3243,-40.5 3299,-40.5 3299,-40.5 3305,-40.5 3311,-46.5 3311,-52.5 3311,-52.5 3311,-64.5 3311,-64.5 3311,-70.5 3305,-76.5 3299,-76.5 3299,-76.5 3243,-76.5 3243,-76.5 3237,-76.5 3231,-70.5 3231,-64.5 3231,-64.5 3231,-52.5 3231,-52.5 3231,-46.5 3237,-40.5 3243,-40.5"/>
<text text-anchor="middle" x="3271" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu2_dcache_mem_side -->
<g id="edge12" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu2_dcache_mem_side</title>
<path fill="none" stroke="black" d="M3122.47,-379.9C3234.33,-380.7 3560.1,-380.08 3592,-346 3621.01,-315.01 3619.7,-187.16 3592,-155 3560.61,-118.57 3423.3,-139.13 3378,-123 3346.86,-111.92 3314.73,-91.4 3293.9,-76.68"/>
<polygon fill="black" stroke="black" points="3122.36,-376.4 3112.33,-379.82 3122.3,-383.4 3122.36,-376.4"/>
</g>
<!-- system_cpu3_icache_mem_side -->
<g id="node64" class="node">
<title>system_cpu3_icache_mem_side</title>
<path fill="#94918b" stroke="#000000" d="M3684,-40.5C3684,-40.5 3740,-40.5 3740,-40.5 3746,-40.5 3752,-46.5 3752,-52.5 3752,-52.5 3752,-64.5 3752,-64.5 3752,-70.5 3746,-76.5 3740,-76.5 3740,-76.5 3684,-76.5 3684,-76.5 3678,-76.5 3672,-70.5 3672,-64.5 3672,-64.5 3672,-52.5 3672,-52.5 3672,-46.5 3678,-40.5 3684,-40.5"/>
<text text-anchor="middle" x="3712" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu3_icache_mem_side -->
<g id="edge15" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu3_icache_mem_side</title>
<path fill="none" stroke="black" d="M3122.33,-379.79C3237.74,-380.34 3583.22,-379.16 3620,-346 3683.93,-288.37 3621.4,-235.45 3652,-155 3663.28,-125.35 3684.31,-94.98 3698.23,-76.68"/>
<polygon fill="black" stroke="black" points="3122.23,-376.29 3112.21,-379.74 3122.19,-383.29 3122.23,-376.29"/>
</g>
<!-- system_cpu3_dtb_walker_port -->
<g id="node66" class="node">
<title>system_cpu3_dtb_walker_port</title>
<path fill="#7f7c77" stroke="#000000" d="M4044,-171.5C4044,-171.5 4074,-171.5 4074,-171.5 4080,-171.5 4086,-177.5 4086,-183.5 4086,-183.5 4086,-195.5 4086,-195.5 4086,-201.5 4080,-207.5 4074,-207.5 4074,-207.5 4044,-207.5 4044,-207.5 4038,-207.5 4032,-201.5 4032,-195.5 4032,-195.5 4032,-183.5 4032,-183.5 4032,-177.5 4038,-171.5 4044,-171.5"/>
<text text-anchor="middle" x="4059" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu3_dtb_walker_port -->
<g id="edge18" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu3_dtb_walker_port</title>
<path fill="none" stroke="black" d="M3122.37,-379.3C3290.22,-378.28 3967.94,-372.49 4004,-346 4048.77,-313.11 4057.27,-240.77 4058.76,-207.66"/>
<polygon fill="black" stroke="black" points="3122.26,-375.8 3112.28,-379.36 3122.3,-382.8 3122.26,-375.8"/>
</g>
<!-- system_cpu3_itb_walker_port -->
<g id="node67" class="node">
<title>system_cpu3_itb_walker_port</title>
<path fill="#7f7c77" stroke="#000000" d="M3896,-171.5C3896,-171.5 3926,-171.5 3926,-171.5 3932,-171.5 3938,-177.5 3938,-183.5 3938,-183.5 3938,-195.5 3938,-195.5 3938,-201.5 3932,-207.5 3926,-207.5 3926,-207.5 3896,-207.5 3896,-207.5 3890,-207.5 3884,-201.5 3884,-195.5 3884,-195.5 3884,-183.5 3884,-183.5 3884,-177.5 3890,-171.5 3896,-171.5"/>
<text text-anchor="middle" x="3911" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu3_itb_walker_port -->
<g id="edge17" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu3_itb_walker_port</title>
<path fill="none" stroke="black" d="M3122.47,-379.2C3276.08,-377.8 3850.92,-370.9 3880,-346 3920.46,-311.36 3917.47,-240.24 3913.59,-207.59"/>
<polygon fill="black" stroke="black" points="3122.12,-375.7 3112.15,-379.29 3122.18,-382.7 3122.12,-375.7"/>
</g>
<!-- system_cpu3_dcache_mem_side -->
<g id="node68" class="node">
<title>system_cpu3_dcache_mem_side</title>
<path fill="#94918b" stroke="#000000" d="M4024,-40.5C4024,-40.5 4080,-40.5 4080,-40.5 4086,-40.5 4092,-46.5 4092,-52.5 4092,-52.5 4092,-64.5 4092,-64.5 4092,-70.5 4086,-76.5 4080,-76.5 4080,-76.5 4024,-76.5 4024,-76.5 4018,-76.5 4012,-70.5 4012,-64.5 4012,-64.5 4012,-52.5 4012,-52.5 4012,-46.5 4018,-40.5 4024,-40.5"/>
<text text-anchor="middle" x="4052" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu3_dcache_mem_side -->
<g id="edge16" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu3_dcache_mem_side</title>
<path fill="none" stroke="black" d="M3122.24,-379.77C3306.73,-380.9 4115.45,-383.72 4152,-346 4181.54,-315.52 4168.69,-194.02 4152,-155 4137.46,-121.01 4104.23,-93.35 4080.05,-76.71"/>
<polygon fill="black" stroke="black" points="3122.23,-376.27 3112.21,-379.7 3122.19,-383.27 3122.23,-376.27"/>
</g>
<!-- system_cpu4_icache_mem_side -->
<g id="node72" class="node">
<title>system_cpu4_icache_mem_side</title>
<path fill="#94918b" stroke="#000000" d="M4572,-40.5C4572,-40.5 4628,-40.5 4628,-40.5 4634,-40.5 4640,-46.5 4640,-52.5 4640,-52.5 4640,-64.5 4640,-64.5 4640,-70.5 4634,-76.5 4628,-76.5 4628,-76.5 4572,-76.5 4572,-76.5 4566,-76.5 4560,-70.5 4560,-64.5 4560,-64.5 4560,-52.5 4560,-52.5 4560,-46.5 4566,-40.5 4572,-40.5"/>
<text text-anchor="middle" x="4600" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu4_icache_mem_side -->
<g id="edge19" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu4_icache_mem_side</title>
<path fill="none" stroke="black" d="M3122.53,-379.43C3361.23,-378.93 4658.73,-374.87 4687,-346 4716.7,-315.68 4702.33,-194.58 4687,-155 4674.29,-122.16 4644.44,-93.68 4623.27,-76.57"/>
<polygon fill="black" stroke="black" points="3122.27,-375.94 3112.28,-379.46 3122.29,-382.93 3122.27,-375.94"/>
</g>
<!-- system_cpu4_dtb_walker_port -->
<g id="node74" class="node">
<title>system_cpu4_dtb_walker_port</title>
<path fill="#7f7c77" stroke="#000000" d="M4564,-171.5C4564,-171.5 4594,-171.5 4594,-171.5 4600,-171.5 4606,-177.5 4606,-183.5 4606,-183.5 4606,-195.5 4606,-195.5 4606,-201.5 4600,-207.5 4594,-207.5 4594,-207.5 4564,-207.5 4564,-207.5 4558,-207.5 4552,-201.5 4552,-195.5 4552,-195.5 4552,-183.5 4552,-183.5 4552,-177.5 4558,-171.5 4564,-171.5"/>
<text text-anchor="middle" x="4579" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu4_dtb_walker_port -->
<g id="edge22" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu4_dtb_walker_port</title>
<path fill="none" stroke="black" d="M3122.39,-379.21C3345.73,-377.42 4494.77,-367.18 4524,-346 4568.98,-313.4 4577.37,-240.91 4578.8,-207.71"/>
<polygon fill="black" stroke="black" points="3122.14,-375.71 3112.17,-379.29 3122.2,-382.71 3122.14,-375.71"/>
</g>
<!-- system_cpu4_itb_walker_port -->
<g id="node75" class="node">
<title>system_cpu4_itb_walker_port</title>
<path fill="#7f7c77" stroke="#000000" d="M4416,-171.5C4416,-171.5 4446,-171.5 4446,-171.5 4452,-171.5 4458,-177.5 4458,-183.5 4458,-183.5 4458,-195.5 4458,-195.5 4458,-201.5 4452,-207.5 4446,-207.5 4446,-207.5 4416,-207.5 4416,-207.5 4410,-207.5 4404,-201.5 4404,-195.5 4404,-195.5 4404,-183.5 4404,-183.5 4404,-177.5 4410,-171.5 4416,-171.5"/>
<text text-anchor="middle" x="4431" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu4_itb_walker_port -->
<g id="edge21" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu4_itb_walker_port</title>
<path fill="none" stroke="black" d="M3122.5,-379.18C3334.55,-377.32 4374.9,-367.13 4400,-346 4440.75,-311.7 4437.61,-240.41 4433.65,-207.65"/>
<polygon fill="black" stroke="black" points="3122.17,-375.69 3112.2,-379.27 3122.23,-382.69 3122.17,-375.69"/>
</g>
<!-- system_cpu4_dcache_mem_side -->
<g id="node76" class="node">
<title>system_cpu4_dcache_mem_side</title>
<path fill="#94918b" stroke="#000000" d="M4323,-40.5C4323,-40.5 4379,-40.5 4379,-40.5 4385,-40.5 4391,-46.5 4391,-52.5 4391,-52.5 4391,-64.5 4391,-64.5 4391,-70.5 4385,-76.5 4379,-76.5 4379,-76.5 4323,-76.5 4323,-76.5 4317,-76.5 4311,-70.5 4311,-64.5 4311,-64.5 4311,-52.5 4311,-52.5 4311,-46.5 4317,-40.5 4323,-40.5"/>
<text text-anchor="middle" x="4351" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu4_dcache_mem_side -->
<g id="edge20" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu4_dcache_mem_side</title>
<path fill="none" stroke="black" d="M3122.18,-379.43C3358.65,-378.88 4643.99,-374.6 4672,-346 4701.69,-315.67 4699.7,-187.16 4672,-155 4640.61,-118.57 4503.3,-139.13 4458,-123 4426.86,-111.92 4394.73,-91.4 4373.9,-76.68"/>
<polygon fill="black" stroke="black" points="3122.02,-375.93 3112.02,-379.45 3122.03,-382.93 3122.02,-375.93"/>
</g>
<!-- system_cpu5_icache_mem_side -->
<g id="node80" class="node">
<title>system_cpu5_icache_mem_side</title>
<path fill="#94918b" stroke="#000000" d="M4764,-40.5C4764,-40.5 4820,-40.5 4820,-40.5 4826,-40.5 4832,-46.5 4832,-52.5 4832,-52.5 4832,-64.5 4832,-64.5 4832,-70.5 4826,-76.5 4820,-76.5 4820,-76.5 4764,-76.5 4764,-76.5 4758,-76.5 4752,-70.5 4752,-64.5 4752,-64.5 4752,-52.5 4752,-52.5 4752,-46.5 4758,-40.5 4764,-40.5"/>
<text text-anchor="middle" x="4792" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu5_icache_mem_side -->
<g id="edge23" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu5_icache_mem_side</title>
<path fill="none" stroke="black" d="M3122.39,-379.38C3361.66,-378.53 4669.16,-372.65 4700,-346 4765.12,-289.71 4701.4,-235.45 4732,-155 4743.28,-125.35 4764.31,-94.98 4778.23,-76.68"/>
<polygon fill="black" stroke="black" points="3122.11,-375.88 3112.13,-379.41 3122.14,-382.88 3122.11,-375.88"/>
</g>
<!-- system_cpu5_dtb_walker_port -->
<g id="node82" class="node">
<title>system_cpu5_dtb_walker_port</title>
<path fill="#7f7c77" stroke="#000000" d="M5124,-171.5C5124,-171.5 5154,-171.5 5154,-171.5 5160,-171.5 5166,-177.5 5166,-183.5 5166,-183.5 5166,-195.5 5166,-195.5 5166,-201.5 5160,-207.5 5154,-207.5 5154,-207.5 5124,-207.5 5124,-207.5 5118,-207.5 5112,-201.5 5112,-195.5 5112,-195.5 5112,-183.5 5112,-183.5 5112,-177.5 5118,-171.5 5124,-171.5"/>
<text text-anchor="middle" x="5139" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu5_dtb_walker_port -->
<g id="edge26" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu5_dtb_walker_port</title>
<path fill="none" stroke="black" d="M3122.36,-379.46C3392.92,-379.11 5042.62,-375.78 5084,-346 5129.09,-313.55 5137.43,-240.98 5138.82,-207.73"/>
<polygon fill="black" stroke="black" points="3122.26,-375.96 3112.26,-379.47 3122.27,-382.96 3122.26,-375.96"/>
</g>
<!-- system_cpu5_itb_walker_port -->
<g id="node83" class="node">
<title>system_cpu5_itb_walker_port</title>
<path fill="#7f7c77" stroke="#000000" d="M4976,-171.5C4976,-171.5 5006,-171.5 5006,-171.5 5012,-171.5 5018,-177.5 5018,-183.5 5018,-183.5 5018,-195.5 5018,-195.5 5018,-201.5 5012,-207.5 5006,-207.5 5006,-207.5 4976,-207.5 4976,-207.5 4970,-207.5 4964,-201.5 4964,-195.5 4964,-195.5 4964,-183.5 4964,-183.5 4964,-177.5 4970,-171.5 4976,-171.5"/>
<text text-anchor="middle" x="4991" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu5_itb_walker_port -->
<g id="edge25" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu5_itb_walker_port</title>
<path fill="none" stroke="black" d="M3122.09,-379.48C3382.19,-379.24 4923.4,-376.58 4960,-346 5000.88,-311.85 4997.67,-240.48 4993.67,-207.67"/>
<polygon fill="black" stroke="black" points="3122.02,-375.98 3112.02,-379.49 3122.02,-382.98 3122.02,-375.98"/>
</g>
<!-- system_cpu5_dcache_mem_side -->
<g id="node84" class="node">
<title>system_cpu5_dcache_mem_side</title>
<path fill="#94918b" stroke="#000000" d="M5104,-40.5C5104,-40.5 5160,-40.5 5160,-40.5 5166,-40.5 5172,-46.5 5172,-52.5 5172,-52.5 5172,-64.5 5172,-64.5 5172,-70.5 5166,-76.5 5160,-76.5 5160,-76.5 5104,-76.5 5104,-76.5 5098,-76.5 5092,-70.5 5092,-64.5 5092,-64.5 5092,-52.5 5092,-52.5 5092,-46.5 5098,-40.5 5104,-40.5"/>
<text text-anchor="middle" x="5132" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu5_dcache_mem_side -->
<g id="edge24" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu5_dcache_mem_side</title>
<path fill="none" stroke="black" d="M3122.12,-379.64C3403.73,-380.6 5193.45,-385.16 5232,-346 5291.56,-285.51 5265.39,-233.05 5232,-155 5217.46,-121.01 5184.23,-93.35 5160.05,-76.71"/>
<polygon fill="black" stroke="black" points="3122.03,-376.14 3112.01,-379.6 3122,-383.14 3122.03,-376.14"/>
</g>
<!-- system_cpu6_icache_mem_side -->
<g id="node88" class="node">
<title>system_cpu6_icache_mem_side</title>
<path fill="#94918b" stroke="#000000" d="M1332,-40.5C1332,-40.5 1388,-40.5 1388,-40.5 1394,-40.5 1400,-46.5 1400,-52.5 1400,-52.5 1400,-64.5 1400,-64.5 1400,-70.5 1394,-76.5 1388,-76.5 1388,-76.5 1332,-76.5 1332,-76.5 1326,-76.5 1320,-70.5 1320,-64.5 1320,-64.5 1320,-52.5 1320,-52.5 1320,-46.5 1326,-40.5 1332,-40.5"/>
<text text-anchor="middle" x="1360" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu6_icache_mem_side -->
<g id="edge27" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu6_icache_mem_side</title>
<path fill="none" stroke="black" d="M3056.61,-357.17C3054.13,-355.91 3051.58,-354.83 3049,-354 3028.15,-347.3 1488.31,-360.62 1472,-346 1440.18,-317.49 1468.01,-193.74 1450,-155 1434.92,-122.57 1404.49,-94 1383.2,-76.75"/>
<polygon fill="black" stroke="black" points="3054.86,-360.2 3065.24,-362.31 3058.44,-354.18 3054.86,-360.2"/>
</g>
<!-- system_cpu6_dtb_walker_port -->
<g id="node90" class="node">
<title>system_cpu6_dtb_walker_port</title>
<path fill="#7f7c77" stroke="#000000" d="M1378,-171.5C1378,-171.5 1408,-171.5 1408,-171.5 1414,-171.5 1420,-177.5 1420,-183.5 1420,-183.5 1420,-195.5 1420,-195.5 1420,-201.5 1414,-207.5 1408,-207.5 1408,-207.5 1378,-207.5 1378,-207.5 1372,-207.5 1366,-201.5 1366,-195.5 1366,-195.5 1366,-183.5 1366,-183.5 1366,-177.5 1372,-171.5 1378,-171.5"/>
<text text-anchor="middle" x="1393" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu6_dtb_walker_port -->
<g id="edge30" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu6_dtb_walker_port</title>
<path fill="none" stroke="black" d="M3056.61,-357.17C3054.13,-355.91 3051.58,-354.83 3049,-354 3027.72,-347.17 1457.91,-359.37 1440,-346 1396.15,-313.28 1391.77,-240.85 1392.22,-207.69"/>
<polygon fill="black" stroke="black" points="3054.86,-360.2 3065.24,-362.31 3058.44,-354.18 3054.86,-360.2"/>
</g>
<!-- system_cpu6_itb_walker_port -->
<g id="node91" class="node">
<title>system_cpu6_itb_walker_port</title>
<path fill="#7f7c77" stroke="#000000" d="M1230,-171.5C1230,-171.5 1260,-171.5 1260,-171.5 1266,-171.5 1272,-177.5 1272,-183.5 1272,-183.5 1272,-195.5 1272,-195.5 1272,-201.5 1266,-207.5 1260,-207.5 1260,-207.5 1230,-207.5 1230,-207.5 1224,-207.5 1218,-201.5 1218,-195.5 1218,-195.5 1218,-183.5 1218,-183.5 1218,-177.5 1224,-171.5 1230,-171.5"/>
<text text-anchor="middle" x="1245" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu6_itb_walker_port -->
<g id="edge29" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu6_itb_walker_port</title>
<path fill="none" stroke="black" d="M3056.61,-357.17C3054.13,-355.91 3051.58,-354.83 3049,-354 3025.87,-346.58 1319.8,-360.07 1300,-346 1254.6,-313.74 1246.44,-240.74 1245.14,-207.53"/>
<polygon fill="black" stroke="black" points="3054.86,-360.19 3065.24,-362.31 3058.44,-354.18 3054.86,-360.19"/>
</g>
<!-- system_cpu6_dcache_mem_side -->
<g id="node92" class="node">
<title>system_cpu6_dcache_mem_side</title>
<path fill="#94918b" stroke="#000000" d="M1083,-40.5C1083,-40.5 1139,-40.5 1139,-40.5 1145,-40.5 1151,-46.5 1151,-52.5 1151,-52.5 1151,-64.5 1151,-64.5 1151,-70.5 1145,-76.5 1139,-76.5 1139,-76.5 1083,-76.5 1083,-76.5 1077,-76.5 1071,-70.5 1071,-64.5 1071,-64.5 1071,-52.5 1071,-52.5 1071,-46.5 1077,-40.5 1083,-40.5"/>
<text text-anchor="middle" x="1111" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu6_dcache_mem_side -->
<g id="edge28" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu6_dcache_mem_side</title>
<path fill="none" stroke="black" d="M3056.61,-357.17C3054.13,-355.91 3051.58,-354.83 3049,-354 3027.85,-347.21 1466.39,-360.99 1450,-346 1418.54,-317.22 1461.31,-185.96 1432,-155 1398.94,-120.09 1263.3,-139.13 1218,-123 1186.86,-111.92 1154.73,-91.4 1133.9,-76.68"/>
<polygon fill="black" stroke="black" points="3054.86,-360.2 3065.24,-362.31 3058.44,-354.18 3054.86,-360.2"/>
</g>
<!-- system_cpu7_icache_mem_side -->
<g id="node96" class="node">
<title>system_cpu7_icache_mem_side</title>
<path fill="#94918b" stroke="#000000" d="M1872,-40.5C1872,-40.5 1928,-40.5 1928,-40.5 1934,-40.5 1940,-46.5 1940,-52.5 1940,-52.5 1940,-64.5 1940,-64.5 1940,-70.5 1934,-76.5 1928,-76.5 1928,-76.5 1872,-76.5 1872,-76.5 1866,-76.5 1860,-70.5 1860,-64.5 1860,-64.5 1860,-52.5 1860,-52.5 1860,-46.5 1866,-40.5 1872,-40.5"/>
<text text-anchor="middle" x="1900" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu7_icache_mem_side -->
<g id="edge31" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu7_icache_mem_side</title>
<path fill="none" stroke="black" d="M3056.61,-357.18C3054.13,-355.92 3051.58,-354.83 3049,-354 3035.29,-349.58 2022.71,-355.63 2012,-346 1980.22,-317.45 2008.01,-193.74 1990,-155 1974.92,-122.57 1944.49,-94 1923.2,-76.75"/>
<polygon fill="black" stroke="black" points="3054.85,-360.2 3065.24,-362.32 3058.44,-354.19 3054.85,-360.2"/>
</g>
<!-- system_cpu7_dtb_walker_port -->
<g id="node98" class="node">
<title>system_cpu7_dtb_walker_port</title>
<path fill="#7f7c77" stroke="#000000" d="M1918,-171.5C1918,-171.5 1948,-171.5 1948,-171.5 1954,-171.5 1960,-177.5 1960,-183.5 1960,-183.5 1960,-195.5 1960,-195.5 1960,-201.5 1954,-207.5 1948,-207.5 1948,-207.5 1918,-207.5 1918,-207.5 1912,-207.5 1906,-201.5 1906,-195.5 1906,-195.5 1906,-183.5 1906,-183.5 1906,-177.5 1912,-171.5 1918,-171.5"/>
<text text-anchor="middle" x="1933" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu7_dtb_walker_port -->
<g id="edge34" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu7_dtb_walker_port</title>
<path fill="none" stroke="black" d="M3056.61,-357.18C3054.13,-355.92 3051.58,-354.83 3049,-354 3020.74,-344.89 2003.78,-363.79 1980,-346 1936.19,-313.22 1931.79,-240.82 1932.23,-207.68"/>
<polygon fill="black" stroke="black" points="3054.85,-360.2 3065.24,-362.32 3058.44,-354.19 3054.85,-360.2"/>
</g>
<!-- system_cpu7_itb_walker_port -->
<g id="node99" class="node">
<title>system_cpu7_itb_walker_port</title>
<path fill="#7f7c77" stroke="#000000" d="M1770,-171.5C1770,-171.5 1800,-171.5 1800,-171.5 1806,-171.5 1812,-177.5 1812,-183.5 1812,-183.5 1812,-195.5 1812,-195.5 1812,-201.5 1806,-207.5 1800,-207.5 1800,-207.5 1770,-207.5 1770,-207.5 1764,-207.5 1758,-201.5 1758,-195.5 1758,-195.5 1758,-183.5 1758,-183.5 1758,-177.5 1764,-171.5 1770,-171.5"/>
<text text-anchor="middle" x="1785" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu7_itb_walker_port -->
<g id="edge33" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu7_itb_walker_port</title>
<path fill="none" stroke="black" d="M3056.61,-357.17C3054.13,-355.92 3051.58,-354.83 3049,-354 3033.02,-348.85 1853.68,-355.74 1840,-346 1794.63,-313.7 1786.45,-240.72 1785.14,-207.52"/>
<polygon fill="black" stroke="black" points="3054.86,-360.2 3065.24,-362.31 3058.44,-354.19 3054.86,-360.2"/>
</g>
<!-- system_cpu7_dcache_mem_side -->
<g id="node100" class="node">
<title>system_cpu7_dcache_mem_side</title>
<path fill="#94918b" stroke="#000000" d="M1623,-40.5C1623,-40.5 1679,-40.5 1679,-40.5 1685,-40.5 1691,-46.5 1691,-52.5 1691,-52.5 1691,-64.5 1691,-64.5 1691,-70.5 1685,-76.5 1679,-76.5 1679,-76.5 1623,-76.5 1623,-76.5 1617,-76.5 1611,-70.5 1611,-64.5 1611,-64.5 1611,-52.5 1611,-52.5 1611,-46.5 1617,-40.5 1623,-40.5"/>
<text text-anchor="middle" x="1651" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_tol2bus_slave&#45;&gt;system_cpu7_dcache_mem_side -->
<g id="edge32" class="edge">
<title>system_tol2bus_slave&#45;&gt;system_cpu7_dcache_mem_side</title>
<path fill="none" stroke="black" d="M3056.61,-357.18C3054.13,-355.92 3051.58,-354.83 3049,-354 3035,-349.49 2000.84,-355.94 1990,-346 1958.58,-317.18 2001.31,-185.96 1972,-155 1938.94,-120.09 1803.3,-139.13 1758,-123 1726.86,-111.92 1694.73,-91.4 1673.9,-76.68"/>
<polygon fill="black" stroke="black" points="3054.85,-360.2 3065.24,-362.32 3058.44,-354.19 3054.85,-360.2"/>
</g>
<!-- system_bridge_master -->
<g id="node4" class="node">
<title>system_bridge_master</title>
<path fill="#94918b" stroke="#000000" d="M484.5,-171.5C484.5,-171.5 519.5,-171.5 519.5,-171.5 525.5,-171.5 531.5,-177.5 531.5,-183.5 531.5,-183.5 531.5,-195.5 531.5,-195.5 531.5,-201.5 525.5,-207.5 519.5,-207.5 519.5,-207.5 484.5,-207.5 484.5,-207.5 478.5,-207.5 472.5,-201.5 472.5,-195.5 472.5,-195.5 472.5,-183.5 472.5,-183.5 472.5,-177.5 478.5,-171.5 484.5,-171.5"/>
<text text-anchor="middle" x="502" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">master</text>
</g>
<!-- system_bridge_slave -->
<g id="node5" class="node">
<title>system_bridge_slave</title>
<path fill="#94918b" stroke="#000000" d="M412,-171.5C412,-171.5 442,-171.5 442,-171.5 448,-171.5 454,-177.5 454,-183.5 454,-183.5 454,-195.5 454,-195.5 454,-201.5 448,-207.5 442,-207.5 442,-207.5 412,-207.5 412,-207.5 406,-207.5 400,-201.5 400,-195.5 400,-195.5 400,-183.5 400,-183.5 400,-177.5 406,-171.5 412,-171.5"/>
<text text-anchor="middle" x="427" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">slave</text>
</g>
<!-- system_membus_default -->
<g id="node6" class="node">
<title>system_membus_default</title>
<path fill="#586070" stroke="#000000" d="M44.5,-362.5C44.5,-362.5 77.5,-362.5 77.5,-362.5 83.5,-362.5 89.5,-368.5 89.5,-374.5 89.5,-374.5 89.5,-386.5 89.5,-386.5 89.5,-392.5 83.5,-398.5 77.5,-398.5 77.5,-398.5 44.5,-398.5 44.5,-398.5 38.5,-398.5 32.5,-392.5 32.5,-386.5 32.5,-386.5 32.5,-374.5 32.5,-374.5 32.5,-368.5 38.5,-362.5 44.5,-362.5"/>
<text text-anchor="middle" x="61" y="-376.8" font-family="Arial" font-size="14.00" fill="#000000">default</text>
</g>
<!-- system_membus_badaddr_responder_pio -->
<g id="node9" class="node">
<title>system_membus_badaddr_responder_pio</title>
<path fill="#9f8575" stroke="#000000" d="M52,-171.5C52,-171.5 82,-171.5 82,-171.5 88,-171.5 94,-177.5 94,-183.5 94,-183.5 94,-195.5 94,-195.5 94,-201.5 88,-207.5 82,-207.5 82,-207.5 52,-207.5 52,-207.5 46,-207.5 40,-201.5 40,-195.5 40,-195.5 40,-183.5 40,-183.5 40,-177.5 46,-171.5 52,-171.5"/>
<text text-anchor="middle" x="67" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_membus_default&#45;&gt;system_membus_badaddr_responder_pio -->
<g id="edge35" class="edge">
<title>system_membus_default&#45;&gt;system_membus_badaddr_responder_pio</title>
<path fill="none" stroke="black" d="M61.54,-362.39C62.59,-329.52 64.88,-257.26 66.14,-217.7"/>
<polygon fill="black" stroke="black" points="69.63,-217.81 66.45,-207.7 62.64,-217.59 69.63,-217.81"/>
</g>
<!-- system_membus_master -->
<g id="node7" class="node">
<title>system_membus_master</title>
<path fill="#586070" stroke="#000000" d="M192.5,-362.5C192.5,-362.5 227.5,-362.5 227.5,-362.5 233.5,-362.5 239.5,-368.5 239.5,-374.5 239.5,-374.5 239.5,-386.5 239.5,-386.5 239.5,-392.5 233.5,-398.5 227.5,-398.5 227.5,-398.5 192.5,-398.5 192.5,-398.5 186.5,-398.5 180.5,-392.5 180.5,-386.5 180.5,-386.5 180.5,-374.5 180.5,-374.5 180.5,-368.5 186.5,-362.5 192.5,-362.5"/>
<text text-anchor="middle" x="210" y="-376.8" font-family="Arial" font-size="14.00" fill="#000000">master</text>
</g>
<!-- system_membus_master&#45;&gt;system_bridge_slave -->
<g id="edge36" class="edge">
<title>system_membus_master&#45;&gt;system_bridge_slave</title>
<path fill="none" stroke="black" d="M239.69,-377.72C284.65,-374.42 367,-365.78 388,-346 423.1,-312.94 428.55,-253.41 428.41,-218.37"/>
<polygon fill="black" stroke="black" points="431.9,-217.85 428.2,-207.93 424.9,-218 431.9,-217.85"/>
</g>
<!-- system_mem_ctrls_port -->
<g id="node104" class="node">
<title>system_mem_ctrls_port</title>
<path fill="#4b4746" stroke="#000000" d="M276,-171.5C276,-171.5 306,-171.5 306,-171.5 312,-171.5 318,-177.5 318,-183.5 318,-183.5 318,-195.5 318,-195.5 318,-201.5 312,-207.5 306,-207.5 306,-207.5 276,-207.5 276,-207.5 270,-207.5 264,-201.5 264,-195.5 264,-195.5 264,-183.5 264,-183.5 264,-177.5 270,-171.5 276,-171.5"/>
<text text-anchor="middle" x="291" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_membus_master&#45;&gt;system_mem_ctrls_port -->
<g id="edge37" class="edge">
<title>system_membus_master&#45;&gt;system_mem_ctrls_port</title>
<path fill="none" stroke="black" d="M217.33,-362.39C231.51,-329.31 262.78,-256.34 279.66,-216.95"/>
<polygon fill="black" stroke="black" points="282.9,-218.27 283.63,-207.7 276.47,-215.52 282.9,-218.27"/>
</g>
<!-- system_l2_mem_side -->
<g id="node102" class="node">
<title>system_l2_mem_side</title>
<path fill="#94918b" stroke="#000000" d="M762,-171.5C762,-171.5 818,-171.5 818,-171.5 824,-171.5 830,-177.5 830,-183.5 830,-183.5 830,-195.5 830,-195.5 830,-201.5 824,-207.5 818,-207.5 818,-207.5 762,-207.5 762,-207.5 756,-207.5 750,-201.5 750,-195.5 750,-195.5 750,-183.5 750,-183.5 750,-177.5 756,-171.5 762,-171.5"/>
<text text-anchor="middle" x="790" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_membus_slave&#45;&gt;system_l2_mem_side -->
<g id="edge39" class="edge">
<title>system_membus_slave&#45;&gt;system_l2_mem_side</title>
<path fill="none" stroke="black" d="M164.22,-357.19C166.77,-355.93 169.37,-354.84 172,-354 186.98,-349.22 725.31,-355.28 738,-346 782.59,-313.42 789.46,-240.92 790.17,-207.71"/>
<polygon fill="black" stroke="black" points="162.26,-354.28 155.38,-362.34 165.78,-360.33 162.26,-354.28"/>
</g>
<!-- system_iocache_mem_side -->
<g id="node109" class="node">
<title>system_iocache_mem_side</title>
<path fill="#94918b" stroke="#000000" d="M568,-171.5C568,-171.5 624,-171.5 624,-171.5 630,-171.5 636,-177.5 636,-183.5 636,-183.5 636,-195.5 636,-195.5 636,-201.5 630,-207.5 624,-207.5 624,-207.5 568,-207.5 568,-207.5 562,-207.5 556,-201.5 556,-195.5 556,-195.5 556,-183.5 556,-183.5 556,-177.5 562,-171.5 568,-171.5"/>
<text text-anchor="middle" x="596" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_membus_slave&#45;&gt;system_iocache_mem_side -->
<g id="edge38" class="edge">
<title>system_membus_slave&#45;&gt;system_iocache_mem_side</title>
<path fill="none" stroke="black" d="M164.23,-357.21C166.77,-355.95 169.38,-354.85 172,-354 191.67,-347.65 527.36,-358.26 544,-346 588.47,-313.25 595.4,-240.84 596.15,-207.68"/>
<polygon fill="black" stroke="black" points="162.26,-354.31 155.39,-362.37 165.79,-360.36 162.26,-354.31"/>
</g>
<!-- system_realview_hdlcd_dma -->
<g id="node10" class="node">
<title>system_realview_hdlcd_dma</title>
<path fill="#9f8575" stroke="#000000" d="M152,-493.5C152,-493.5 182,-493.5 182,-493.5 188,-493.5 194,-499.5 194,-505.5 194,-505.5 194,-517.5 194,-517.5 194,-523.5 188,-529.5 182,-529.5 182,-529.5 152,-529.5 152,-529.5 146,-529.5 140,-523.5 140,-517.5 140,-517.5 140,-505.5 140,-505.5 140,-499.5 146,-493.5 152,-493.5"/>
<text text-anchor="middle" x="167" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">dma</text>
</g>
<!-- system_realview_hdlcd_dma&#45;&gt;system_membus_slave -->
<g id="edge40" class="edge">
<title>system_realview_hdlcd_dma&#45;&gt;system_membus_slave</title>
<path fill="none" stroke="black" d="M162.75,-493.37C157.37,-471.68 148.04,-434.08 141.7,-408.51"/>
<polygon fill="black" stroke="black" points="145.07,-407.56 139.27,-398.7 138.28,-409.25 145.07,-407.56"/>
</g>
<!-- system_realview_hdlcd_pio -->
<g id="node11" class="node">
<title>system_realview_hdlcd_pio</title>
<path fill="#9f8575" stroke="#000000" d="M224,-493.5C224,-493.5 254,-493.5 254,-493.5 260,-493.5 266,-499.5 266,-505.5 266,-505.5 266,-517.5 266,-517.5 266,-523.5 260,-529.5 254,-529.5 254,-529.5 224,-529.5 224,-529.5 218,-529.5 212,-523.5 212,-517.5 212,-517.5 212,-505.5 212,-505.5 212,-499.5 218,-493.5 224,-493.5"/>
<text text-anchor="middle" x="239" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_hdlcd_pio&#45;&gt;system_membus_master -->
<g id="edge41" class="edge">
<title>system_realview_hdlcd_pio&#45;&gt;system_membus_master</title>
<path fill="none" stroke="black" d="M232.95,-483.57C227.2,-458.03 218.75,-420.42 213.87,-398.7"/>
<polygon fill="black" stroke="black" points="229.54,-484.38 235.15,-493.37 236.37,-482.85 229.54,-484.38"/>
</g>
<!-- system_realview_rtc_pio -->
<g id="node12" class="node">
<title>system_realview_rtc_pio</title>
<path fill="#9f8575" stroke="#000000" d="M2942,-493.5C2942,-493.5 2972,-493.5 2972,-493.5 2978,-493.5 2984,-499.5 2984,-505.5 2984,-505.5 2984,-517.5 2984,-517.5 2984,-523.5 2978,-529.5 2972,-529.5 2972,-529.5 2942,-529.5 2942,-529.5 2936,-529.5 2930,-523.5 2930,-517.5 2930,-517.5 2930,-505.5 2930,-505.5 2930,-499.5 2936,-493.5 2942,-493.5"/>
<text text-anchor="middle" x="2957" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_iobus_master -->
<g id="node105" class="node">
<title>system_iobus_master</title>
<path fill="#586070" stroke="#000000" d="M2148.5,-362.5C2148.5,-362.5 2183.5,-362.5 2183.5,-362.5 2189.5,-362.5 2195.5,-368.5 2195.5,-374.5 2195.5,-374.5 2195.5,-386.5 2195.5,-386.5 2195.5,-392.5 2189.5,-398.5 2183.5,-398.5 2183.5,-398.5 2148.5,-398.5 2148.5,-398.5 2142.5,-398.5 2136.5,-392.5 2136.5,-386.5 2136.5,-386.5 2136.5,-374.5 2136.5,-374.5 2136.5,-368.5 2142.5,-362.5 2148.5,-362.5"/>
<text text-anchor="middle" x="2166" y="-376.8" font-family="Arial" font-size="14.00" fill="#000000">master</text>
</g>
<!-- system_realview_rtc_pio&#45;&gt;system_iobus_master -->
<g id="edge42" class="edge">
<title>system_realview_rtc_pio&#45;&gt;system_iobus_master</title>
<path fill="none" stroke="black" d="M2939.41,-485.53C2933.42,-478.97 2926.16,-472.69 2918,-469 2845.79,-436.31 2273.52,-484.86 2205,-445 2187.67,-434.92 2177.03,-413.77 2171.33,-398.64"/>
<polygon fill="black" stroke="black" points="2936.74,-487.79 2945.82,-493.24 2942.12,-483.31 2936.74,-487.79"/>
</g>
<!-- system_realview_trusted_watchdog_pio -->
<g id="node13" class="node">
<title>system_realview_trusted_watchdog_pio</title>
<path fill="#9f8575" stroke="#000000" d="M426,-493.5C426,-493.5 456,-493.5 456,-493.5 462,-493.5 468,-499.5 468,-505.5 468,-505.5 468,-517.5 468,-517.5 468,-523.5 462,-529.5 456,-529.5 456,-529.5 426,-529.5 426,-529.5 420,-529.5 414,-523.5 414,-517.5 414,-517.5 414,-505.5 414,-505.5 414,-499.5 420,-493.5 426,-493.5"/>
<text text-anchor="middle" x="441" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_trusted_watchdog_pio&#45;&gt;system_membus_master -->
<g id="edge43" class="edge">
<title>system_realview_trusted_watchdog_pio&#45;&gt;system_membus_master</title>
<path fill="none" stroke="black" d="M420.77,-485.8C415.11,-479.82 408.67,-473.78 402,-469 349.75,-431.54 278.91,-404.32 239.52,-390.9"/>
<polygon fill="black" stroke="black" points="418.19,-488.17 427.49,-493.25 423.39,-483.48 418.19,-488.17"/>
</g>
<!-- system_realview_pwr_ctrl_pio -->
<g id="node14" class="node">
<title>system_realview_pwr_ctrl_pio</title>
<path fill="#9f8575" stroke="#000000" d="M2809,-493.5C2809,-493.5 2839,-493.5 2839,-493.5 2845,-493.5 2851,-499.5 2851,-505.5 2851,-505.5 2851,-517.5 2851,-517.5 2851,-523.5 2845,-529.5 2839,-529.5 2839,-529.5 2809,-529.5 2809,-529.5 2803,-529.5 2797,-523.5 2797,-517.5 2797,-517.5 2797,-505.5 2797,-505.5 2797,-499.5 2803,-493.5 2809,-493.5"/>
<text text-anchor="middle" x="2824" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_pwr_ctrl_pio&#45;&gt;system_iobus_master -->
<g id="edge44" class="edge">
<title>system_realview_pwr_ctrl_pio&#45;&gt;system_iobus_master</title>
<path fill="none" stroke="black" d="M2806.39,-485.57C2800.41,-479.01 2793.14,-472.72 2785,-469 2667.69,-415.35 2316.26,-510.29 2205,-445 2187.7,-434.85 2177.06,-413.71 2171.35,-398.61"/>
<polygon fill="black" stroke="black" points="2803.72,-487.83 2812.81,-493.27 2809.09,-483.35 2803.72,-487.83"/>
</g>
<!-- system_realview_system_watchdog_pio -->
<g id="node15" class="node">
<title>system_realview_system_watchdog_pio</title>
<path fill="#9f8575" stroke="#000000" d="M1432,-493.5C1432,-493.5 1462,-493.5 1462,-493.5 1468,-493.5 1474,-499.5 1474,-505.5 1474,-505.5 1474,-517.5 1474,-517.5 1474,-523.5 1468,-529.5 1462,-529.5 1462,-529.5 1432,-529.5 1432,-529.5 1426,-529.5 1420,-523.5 1420,-517.5 1420,-517.5 1420,-505.5 1420,-505.5 1420,-499.5 1426,-493.5 1432,-493.5"/>
<text text-anchor="middle" x="1447" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_system_watchdog_pio&#45;&gt;system_membus_master -->
<g id="edge45" class="edge">
<title>system_realview_system_watchdog_pio&#45;&gt;system_membus_master</title>
<path fill="none" stroke="black" d="M1429.32,-485.73C1423.33,-479.17 1416.08,-472.85 1408,-469 1299.46,-417.28 414.21,-387.73 239.78,-382.38"/>
<polygon fill="black" stroke="black" points="1426.64,-487.99 1435.74,-493.41 1432.01,-483.49 1426.64,-487.99"/>
</g>
<!-- system_realview_watchdog_pio -->
<g id="node16" class="node">
<title>system_realview_watchdog_pio</title>
<path fill="#9f8575" stroke="#000000" d="M2723,-493.5C2723,-493.5 2753,-493.5 2753,-493.5 2759,-493.5 2765,-499.5 2765,-505.5 2765,-505.5 2765,-517.5 2765,-517.5 2765,-523.5 2759,-529.5 2753,-529.5 2753,-529.5 2723,-529.5 2723,-529.5 2717,-529.5 2711,-523.5 2711,-517.5 2711,-517.5 2711,-505.5 2711,-505.5 2711,-499.5 2717,-493.5 2723,-493.5"/>
<text text-anchor="middle" x="2738" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_watchdog_pio&#45;&gt;system_iobus_master -->
<g id="edge46" class="edge">
<title>system_realview_watchdog_pio&#45;&gt;system_iobus_master</title>
<path fill="none" stroke="black" d="M2720.37,-485.61C2714.39,-479.04 2707.13,-472.75 2699,-469 2599.21,-422.93 2299.59,-500.97 2205,-445 2187.74,-434.79 2177.08,-413.66 2171.36,-398.58"/>
<polygon fill="black" stroke="black" points="2717.7,-487.87 2726.79,-493.3 2723.08,-483.38 2717.7,-487.87"/>
</g>
<!-- system_realview_realview_io_pio -->
<g id="node17" class="node">
<title>system_realview_realview_io_pio</title>
<path fill="#9f8575" stroke="#000000" d="M2613,-493.5C2613,-493.5 2643,-493.5 2643,-493.5 2649,-493.5 2655,-499.5 2655,-505.5 2655,-505.5 2655,-517.5 2655,-517.5 2655,-523.5 2649,-529.5 2643,-529.5 2643,-529.5 2613,-529.5 2613,-529.5 2607,-529.5 2601,-523.5 2601,-517.5 2601,-517.5 2601,-505.5 2601,-505.5 2601,-499.5 2607,-493.5 2613,-493.5"/>
<text text-anchor="middle" x="2628" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_realview_io_pio&#45;&gt;system_iobus_master -->
<g id="edge47" class="edge">
<title>system_realview_realview_io_pio&#45;&gt;system_iobus_master</title>
<path fill="none" stroke="black" d="M2610.34,-485.68C2604.35,-479.12 2597.1,-472.81 2589,-469 2511.62,-432.63 2278.28,-489.05 2205,-445 2187.81,-434.67 2177.14,-413.57 2171.4,-398.53"/>
<polygon fill="black" stroke="black" points="2607.67,-487.94 2616.76,-493.36 2613.04,-483.45 2607.67,-487.94"/>
</g>
<!-- system_realview_bootmem_port -->
<g id="node18" class="node">
<title>system_realview_bootmem_port</title>
<path fill="#4b4746" stroke="#000000" d="M1106,-493.5C1106,-493.5 1136,-493.5 1136,-493.5 1142,-493.5 1148,-499.5 1148,-505.5 1148,-505.5 1148,-517.5 1148,-517.5 1148,-523.5 1142,-529.5 1136,-529.5 1136,-529.5 1106,-529.5 1106,-529.5 1100,-529.5 1094,-523.5 1094,-517.5 1094,-517.5 1094,-505.5 1094,-505.5 1094,-499.5 1100,-493.5 1106,-493.5"/>
<text text-anchor="middle" x="1121" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_realview_bootmem_port&#45;&gt;system_membus_master -->
<g id="edge48" class="edge">
<title>system_realview_bootmem_port&#45;&gt;system_membus_master</title>
<path fill="none" stroke="black" d="M1098.92,-485.96C1091.65,-479.37 1083.08,-472.97 1074,-469 919.28,-401.36 373.82,-385.1 239.87,-382.09"/>
<polygon fill="black" stroke="black" points="1096.65,-488.64 1106.26,-493.09 1101.53,-483.61 1096.65,-488.64"/>
</g>
<!-- system_realview_generic_timer_mem_pio -->
<g id="node19" class="node">
<title>system_realview_generic_timer_mem_pio</title>
<path fill="#9f8575" stroke="#000000" d="M718,-493.5C718,-493.5 748,-493.5 748,-493.5 754,-493.5 760,-499.5 760,-505.5 760,-505.5 760,-517.5 760,-517.5 760,-523.5 754,-529.5 748,-529.5 748,-529.5 718,-529.5 718,-529.5 712,-529.5 706,-523.5 706,-517.5 706,-517.5 706,-505.5 706,-505.5 706,-499.5 712,-493.5 718,-493.5"/>
<text text-anchor="middle" x="733" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_generic_timer_mem_pio&#45;&gt;system_membus_master -->
<g id="edge49" class="edge">
<title>system_realview_generic_timer_mem_pio&#45;&gt;system_membus_master</title>
<path fill="none" stroke="black" d="M714.37,-485.53C708.51,-479.24 701.57,-473.11 694,-469 614.09,-425.59 332.09,-393.84 239.62,-384.4"/>
<polygon fill="black" stroke="black" points="712,-488.15 721.18,-493.45 717.31,-483.58 712,-488.15"/>
</g>
<!-- system_realview_generic_timer_mem_frames0_pio -->
<g id="node20" class="node">
<title>system_realview_generic_timer_mem_frames0_pio</title>
<path fill="#887264" stroke="#000000" d="M943,-493.5C943,-493.5 973,-493.5 973,-493.5 979,-493.5 985,-499.5 985,-505.5 985,-505.5 985,-517.5 985,-517.5 985,-523.5 979,-529.5 973,-529.5 973,-529.5 943,-529.5 943,-529.5 937,-529.5 931,-523.5 931,-517.5 931,-517.5 931,-505.5 931,-505.5 931,-499.5 937,-493.5 943,-493.5"/>
<text text-anchor="middle" x="958" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_generic_timer_mem_frames0_pio&#45;&gt;system_membus_master -->
<g id="edge50" class="edge">
<title>system_realview_generic_timer_mem_frames0_pio&#45;&gt;system_membus_master</title>
<path fill="none" stroke="black" d="M939.52,-485.25C933.66,-478.96 926.69,-472.9 919,-469 796.93,-407.05 358.19,-386.88 239.68,-382.5"/>
<polygon fill="black" stroke="black" points="937.15,-487.87 946.31,-493.2 942.48,-483.32 937.15,-487.87"/>
</g>
<!-- system_realview_generic_timer_mem_frames1_pio -->
<g id="node21" class="node">
<title>system_realview_generic_timer_mem_frames1_pio</title>
<path fill="#887264" stroke="#000000" d="M790,-493.5C790,-493.5 820,-493.5 820,-493.5 826,-493.5 832,-499.5 832,-505.5 832,-505.5 832,-517.5 832,-517.5 832,-523.5 826,-529.5 820,-529.5 820,-529.5 790,-529.5 790,-529.5 784,-529.5 778,-523.5 778,-517.5 778,-517.5 778,-505.5 778,-505.5 778,-499.5 784,-493.5 790,-493.5"/>
<text text-anchor="middle" x="805" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_generic_timer_mem_frames1_pio&#45;&gt;system_membus_master -->
<g id="edge51" class="edge">
<title>system_realview_generic_timer_mem_frames1_pio&#45;&gt;system_membus_master</title>
<path fill="none" stroke="black" d="M790.79,-485.02C786.2,-478.87 780.57,-472.95 774,-469 682.09,-413.71 342.26,-389.36 239.57,-383.16"/>
<polygon fill="black" stroke="black" points="787.92,-487.01 796.4,-493.36 793.73,-483.11 787.92,-487.01"/>
</g>
<!-- system_realview_gic_pio -->
<g id="node22" class="node">
<title>system_realview_gic_pio</title>
<path fill="#9f8575" stroke="#000000" d="M640,-493.5C640,-493.5 670,-493.5 670,-493.5 676,-493.5 682,-499.5 682,-505.5 682,-505.5 682,-517.5 682,-517.5 682,-523.5 676,-529.5 670,-529.5 670,-529.5 640,-529.5 640,-529.5 634,-529.5 628,-523.5 628,-517.5 628,-517.5 628,-505.5 628,-505.5 628,-499.5 634,-493.5 640,-493.5"/>
<text text-anchor="middle" x="655" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_gic_pio&#45;&gt;system_membus_master -->
<g id="edge52" class="edge">
<title>system_realview_gic_pio&#45;&gt;system_membus_master</title>
<path fill="none" stroke="black" d="M636,-485.39C630.2,-479.21 623.38,-473.17 616,-469 489.19,-397.34 309.72,-384.29 239.65,-381.97"/>
<polygon fill="black" stroke="black" points="633.56,-487.92 642.76,-493.17 638.84,-483.33 633.56,-487.92"/>
</g>
<!-- system_realview_energy_ctrl_pio -->
<g id="node23" class="node">
<title>system_realview_energy_ctrl_pio</title>
<path fill="#9f8575" stroke="#000000" d="M2517,-493.5C2517,-493.5 2547,-493.5 2547,-493.5 2553,-493.5 2559,-499.5 2559,-505.5 2559,-505.5 2559,-517.5 2559,-517.5 2559,-523.5 2553,-529.5 2547,-529.5 2547,-529.5 2517,-529.5 2517,-529.5 2511,-529.5 2505,-523.5 2505,-517.5 2505,-517.5 2505,-505.5 2505,-505.5 2505,-499.5 2511,-493.5 2517,-493.5"/>
<text text-anchor="middle" x="2532" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_energy_ctrl_pio&#45;&gt;system_iobus_master -->
<g id="edge53" class="edge">
<title>system_realview_energy_ctrl_pio&#45;&gt;system_iobus_master</title>
<path fill="none" stroke="black" d="M2514.29,-485.78C2508.3,-479.23 2501.06,-472.89 2493,-469 2435.17,-441.08 2259.7,-478.65 2205,-445 2188.03,-434.56 2177.36,-413.7 2171.56,-398.74"/>
<polygon fill="black" stroke="black" points="2511.62,-488.04 2520.72,-493.45 2516.98,-483.54 2511.62,-488.04"/>
</g>
<!-- system_realview_flash0_port -->
<g id="node24" class="node">
<title>system_realview_flash0_port</title>
<path fill="#4b4746" stroke="#000000" d="M302,-493.5C302,-493.5 332,-493.5 332,-493.5 338,-493.5 344,-499.5 344,-505.5 344,-505.5 344,-517.5 344,-517.5 344,-523.5 338,-529.5 332,-529.5 332,-529.5 302,-529.5 302,-529.5 296,-529.5 290,-523.5 290,-517.5 290,-517.5 290,-505.5 290,-505.5 290,-499.5 296,-493.5 302,-493.5"/>
<text text-anchor="middle" x="317" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_realview_flash0_port&#45;&gt;system_membus_master -->
<g id="edge54" class="edge">
<title>system_realview_flash0_port&#45;&gt;system_membus_master</title>
<path fill="none" stroke="black" d="M296.34,-485.59C275.15,-460.05 242.76,-421 224.27,-398.7"/>
<polygon fill="black" stroke="black" points="293.71,-487.91 302.79,-493.37 299.1,-483.44 293.71,-487.91"/>
</g>
<!-- system_realview_flash1_port -->
<g id="node25" class="node">
<title>system_realview_flash1_port</title>
<path fill="#4b4746" stroke="#000000" d="M2393,-493.5C2393,-493.5 2423,-493.5 2423,-493.5 2429,-493.5 2435,-499.5 2435,-505.5 2435,-505.5 2435,-517.5 2435,-517.5 2435,-523.5 2429,-529.5 2423,-529.5 2423,-529.5 2393,-529.5 2393,-529.5 2387,-529.5 2381,-523.5 2381,-517.5 2381,-517.5 2381,-505.5 2381,-505.5 2381,-499.5 2387,-493.5 2393,-493.5"/>
<text text-anchor="middle" x="2408" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_realview_flash1_port&#45;&gt;system_iobus_master -->
<g id="edge55" class="edge">
<title>system_realview_flash1_port&#45;&gt;system_iobus_master</title>
<path fill="none" stroke="black" d="M2389.46,-485.36C2383.6,-479.07 2376.64,-472.99 2369,-469 2303.69,-434.93 2266.51,-485.53 2205,-445 2188.47,-434.11 2177.77,-413.55 2171.83,-398.78"/>
<polygon fill="black" stroke="black" points="2387.09,-487.98 2396.26,-493.3 2392.41,-483.43 2387.09,-487.98"/>
</g>
<!-- system_realview_pci_host_pio -->
<g id="node26" class="node">
<title>system_realview_pci_host_pio</title>
<path fill="#9f8575" stroke="#000000" d="M2241,-493.5C2241,-493.5 2271,-493.5 2271,-493.5 2277,-493.5 2283,-499.5 2283,-505.5 2283,-505.5 2283,-517.5 2283,-517.5 2283,-523.5 2277,-529.5 2271,-529.5 2271,-529.5 2241,-529.5 2241,-529.5 2235,-529.5 2229,-523.5 2229,-517.5 2229,-517.5 2229,-505.5 2229,-505.5 2229,-499.5 2235,-493.5 2241,-493.5"/>
<text text-anchor="middle" x="2256" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_pci_host_pio&#45;&gt;system_iobus_master -->
<g id="edge56" class="edge">
<title>system_realview_pci_host_pio&#45;&gt;system_iobus_master</title>
<path fill="none" stroke="black" d="M2235.52,-485.54C2225.93,-473.52 2214.54,-458.76 2205,-445 2194.39,-429.69 2183.37,-411.51 2175.77,-398.54"/>
<polygon fill="black" stroke="black" points="2232.83,-487.79 2241.83,-493.38 2238.28,-483.4 2232.83,-487.79"/>
</g>
<!-- system_realview_gicv2m_pio -->
<g id="node27" class="node">
<title>system_realview_gicv2m_pio</title>
<path fill="#9f8575" stroke="#000000" d="M561,-493.5C561,-493.5 591,-493.5 591,-493.5 597,-493.5 603,-499.5 603,-505.5 603,-505.5 603,-517.5 603,-517.5 603,-523.5 597,-529.5 591,-529.5 591,-529.5 561,-529.5 561,-529.5 555,-529.5 549,-523.5 549,-517.5 549,-517.5 549,-505.5 549,-505.5 549,-499.5 555,-493.5 561,-493.5"/>
<text text-anchor="middle" x="576" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_gicv2m_pio&#45;&gt;system_membus_master -->
<g id="edge57" class="edge">
<title>system_realview_gicv2m_pio&#45;&gt;system_membus_master</title>
<path fill="none" stroke="black" d="M556.86,-485.63C551.06,-479.45 544.28,-473.35 537,-469 438.39,-410.03 299.69,-390.1 239.64,-383.97"/>
<polygon fill="black" stroke="black" points="554.42,-488.16 563.64,-493.38 559.69,-483.55 554.42,-488.16"/>
</g>
<!-- system_realview_vio0_pio -->
<g id="node28" class="node">
<title>system_realview_vio0_pio</title>
<path fill="#9f8575" stroke="#000000" d="M2151,-493.5C2151,-493.5 2181,-493.5 2181,-493.5 2187,-493.5 2193,-499.5 2193,-505.5 2193,-505.5 2193,-517.5 2193,-517.5 2193,-523.5 2187,-529.5 2181,-529.5 2181,-529.5 2151,-529.5 2151,-529.5 2145,-529.5 2139,-523.5 2139,-517.5 2139,-517.5 2139,-505.5 2139,-505.5 2139,-499.5 2145,-493.5 2151,-493.5"/>
<text text-anchor="middle" x="2166" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_vio0_pio&#45;&gt;system_iobus_master -->
<g id="edge58" class="edge">
<title>system_realview_vio0_pio&#45;&gt;system_iobus_master</title>
<path fill="none" stroke="black" d="M2166,-483.23C2166,-457.7 2166,-420.32 2166,-398.7"/>
<polygon fill="black" stroke="black" points="2162.5,-483.37 2166,-493.37 2169.5,-483.37 2162.5,-483.37"/>
</g>
<!-- system_realview_vio1_pio -->
<g id="node29" class="node">
<title>system_realview_vio1_pio</title>
<path fill="#9f8575" stroke="#000000" d="M2061,-493.5C2061,-493.5 2091,-493.5 2091,-493.5 2097,-493.5 2103,-499.5 2103,-505.5 2103,-505.5 2103,-517.5 2103,-517.5 2103,-523.5 2097,-529.5 2091,-529.5 2091,-529.5 2061,-529.5 2061,-529.5 2055,-529.5 2049,-523.5 2049,-517.5 2049,-517.5 2049,-505.5 2049,-505.5 2049,-499.5 2055,-493.5 2061,-493.5"/>
<text text-anchor="middle" x="2076" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_vio1_pio&#45;&gt;system_iobus_master -->
<g id="edge59" class="edge">
<title>system_realview_vio1_pio&#45;&gt;system_iobus_master</title>
<path fill="none" stroke="black" d="M2093.84,-484.92C2111.67,-459.37 2138.58,-420.81 2154,-398.7"/>
<polygon fill="black" stroke="black" points="2090.8,-483.17 2087.95,-493.37 2096.54,-487.17 2090.8,-483.17"/>
</g>
<!-- system_realview_trusted_sram_port -->
<g id="node30" class="node">
<title>system_realview_trusted_sram_port</title>
<path fill="#4b4746" stroke="#000000" d="M1308,-493.5C1308,-493.5 1338,-493.5 1338,-493.5 1344,-493.5 1350,-499.5 1350,-505.5 1350,-505.5 1350,-517.5 1350,-517.5 1350,-523.5 1344,-529.5 1338,-529.5 1338,-529.5 1308,-529.5 1308,-529.5 1302,-529.5 1296,-523.5 1296,-517.5 1296,-517.5 1296,-505.5 1296,-505.5 1296,-499.5 1302,-493.5 1308,-493.5"/>
<text text-anchor="middle" x="1323" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_realview_trusted_sram_port&#45;&gt;system_membus_master -->
<g id="edge60" class="edge">
<title>system_realview_trusted_sram_port&#45;&gt;system_membus_master</title>
<path fill="none" stroke="black" d="M1305.3,-485.77C1299.31,-479.22 1292.07,-472.89 1284,-469 1092.18,-376.61 392.37,-379.34 239.59,-381.08"/>
<polygon fill="black" stroke="black" points="1302.62,-488.03 1311.73,-493.45 1307.98,-483.53 1302.62,-488.03"/>
</g>
<!-- system_realview_uart0_pio -->
<g id="node31" class="node">
<title>system_realview_uart0_pio</title>
<path fill="#9f8575" stroke="#000000" d="M1959,-493.5C1959,-493.5 1989,-493.5 1989,-493.5 1995,-493.5 2001,-499.5 2001,-505.5 2001,-505.5 2001,-517.5 2001,-517.5 2001,-523.5 1995,-529.5 1989,-529.5 1989,-529.5 1959,-529.5 1959,-529.5 1953,-529.5 1947,-523.5 1947,-517.5 1947,-517.5 1947,-505.5 1947,-505.5 1947,-499.5 1953,-493.5 1959,-493.5"/>
<text text-anchor="middle" x="1974" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_uart0_pio&#45;&gt;system_iobus_master -->
<g id="edge61" class="edge">
<title>system_realview_uart0_pio&#45;&gt;system_iobus_master</title>
<path fill="none" stroke="black" d="M1995.2,-485.52C2000.69,-479.75 2006.81,-473.88 2013,-469 2052.52,-437.82 2104.42,-410.58 2136.48,-395.09"/>
<polygon fill="black" stroke="black" points="1992.33,-483.47 1988.16,-493.21 1997.49,-488.2 1992.33,-483.47"/>
</g>
<!-- system_realview_uart1_pio -->
<g id="node32" class="node">
<title>system_realview_uart1_pio</title>
<path fill="#9f8575" stroke="#000000" d="M1881,-493.5C1881,-493.5 1911,-493.5 1911,-493.5 1917,-493.5 1923,-499.5 1923,-505.5 1923,-505.5 1923,-517.5 1923,-517.5 1923,-523.5 1917,-529.5 1911,-529.5 1911,-529.5 1881,-529.5 1881,-529.5 1875,-529.5 1869,-523.5 1869,-517.5 1869,-517.5 1869,-505.5 1869,-505.5 1869,-499.5 1875,-493.5 1881,-493.5"/>
<text text-anchor="middle" x="1896" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_uart1_pio&#45;&gt;system_iobus_master -->
<g id="edge62" class="edge">
<title>system_realview_uart1_pio&#45;&gt;system_iobus_master</title>
<path fill="none" stroke="black" d="M1915.73,-485.8C1921.46,-479.72 1928.06,-473.64 1935,-469 2000.24,-425.39 2090.25,-399.41 2136.28,-388.15"/>
<polygon fill="black" stroke="black" points="1913.01,-483.59 1908.97,-493.39 1918.24,-488.25 1913.01,-483.59"/>
</g>
<!-- system_realview_uart2_pio -->
<g id="node33" class="node">
<title>system_realview_uart2_pio</title>
<path fill="#9f8575" stroke="#000000" d="M1803,-493.5C1803,-493.5 1833,-493.5 1833,-493.5 1839,-493.5 1845,-499.5 1845,-505.5 1845,-505.5 1845,-517.5 1845,-517.5 1845,-523.5 1839,-529.5 1833,-529.5 1833,-529.5 1803,-529.5 1803,-529.5 1797,-529.5 1791,-523.5 1791,-517.5 1791,-517.5 1791,-505.5 1791,-505.5 1791,-499.5 1797,-493.5 1803,-493.5"/>
<text text-anchor="middle" x="1818" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_uart2_pio&#45;&gt;system_iobus_master -->
<g id="edge63" class="edge">
<title>system_realview_uart2_pio&#45;&gt;system_iobus_master</title>
<path fill="none" stroke="black" d="M1837.19,-485.7C1842.98,-479.52 1849.75,-473.41 1857,-469 1949.19,-412.96 2078.55,-391.65 2136.22,-384.58"/>
<polygon fill="black" stroke="black" points="1834.36,-483.62 1830.4,-493.44 1839.62,-488.23 1834.36,-483.62"/>
</g>
<!-- system_realview_uart3_pio -->
<g id="node34" class="node">
<title>system_realview_uart3_pio</title>
<path fill="#9f8575" stroke="#000000" d="M1725,-493.5C1725,-493.5 1755,-493.5 1755,-493.5 1761,-493.5 1767,-499.5 1767,-505.5 1767,-505.5 1767,-517.5 1767,-517.5 1767,-523.5 1761,-529.5 1755,-529.5 1755,-529.5 1725,-529.5 1725,-529.5 1719,-529.5 1713,-523.5 1713,-517.5 1713,-517.5 1713,-505.5 1713,-505.5 1713,-499.5 1719,-493.5 1725,-493.5"/>
<text text-anchor="middle" x="1740" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_uart3_pio&#45;&gt;system_iobus_master -->
<g id="edge64" class="edge">
<title>system_realview_uart3_pio&#45;&gt;system_iobus_master</title>
<path fill="none" stroke="black" d="M1759.03,-485.44C1764.83,-479.26 1771.64,-473.21 1779,-469 1899.05,-400.36 2068.8,-385.57 2136.48,-382.38"/>
<polygon fill="black" stroke="black" points="1756.19,-483.37 1752.26,-493.21 1761.47,-487.97 1756.19,-483.37"/>
</g>
<!-- system_realview_kmi1_pio -->
<g id="node35" class="node">
<title>system_realview_kmi1_pio</title>
<path fill="#9f8575" stroke="#000000" d="M1647,-493.5C1647,-493.5 1677,-493.5 1677,-493.5 1683,-493.5 1689,-499.5 1689,-505.5 1689,-505.5 1689,-517.5 1689,-517.5 1689,-523.5 1683,-529.5 1677,-529.5 1677,-529.5 1647,-529.5 1647,-529.5 1641,-529.5 1635,-523.5 1635,-517.5 1635,-517.5 1635,-505.5 1635,-505.5 1635,-499.5 1641,-493.5 1647,-493.5"/>
<text text-anchor="middle" x="1662" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_kmi1_pio&#45;&gt;system_iobus_master -->
<g id="edge65" class="edge">
<title>system_realview_kmi1_pio&#45;&gt;system_iobus_master</title>
<path fill="none" stroke="black" d="M1680.65,-485.57C1686.51,-479.28 1693.44,-473.14 1701,-469 1849.23,-387.79 2059.56,-380.6 2136.42,-380.9"/>
<polygon fill="black" stroke="black" points="1677.71,-483.61 1673.84,-493.48 1683.01,-488.18 1677.71,-483.61"/>
</g>
<!-- system_realview_kmi0_pio -->
<g id="node36" class="node">
<title>system_realview_kmi0_pio</title>
<path fill="#9f8575" stroke="#000000" d="M1569,-493.5C1569,-493.5 1599,-493.5 1599,-493.5 1605,-493.5 1611,-499.5 1611,-505.5 1611,-505.5 1611,-517.5 1611,-517.5 1611,-523.5 1605,-529.5 1599,-529.5 1599,-529.5 1569,-529.5 1569,-529.5 1563,-529.5 1557,-523.5 1557,-517.5 1557,-517.5 1557,-505.5 1557,-505.5 1557,-499.5 1563,-493.5 1569,-493.5"/>
<text text-anchor="middle" x="1584" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_kmi0_pio&#45;&gt;system_iobus_master -->
<g id="edge66" class="edge">
<title>system_realview_kmi0_pio&#45;&gt;system_iobus_master</title>
<path fill="none" stroke="black" d="M1602.58,-485.44C1608.44,-479.15 1615.39,-473.04 1623,-469 1713.87,-420.75 2036.53,-391.73 2136.35,-383.75"/>
<polygon fill="black" stroke="black" points="1599.63,-483.49 1595.78,-493.36 1604.94,-488.05 1599.63,-483.49"/>
</g>
<!-- system_realview_vgic_pio -->
<g id="node37" class="node">
<title>system_realview_vgic_pio</title>
<path fill="#9f8575" stroke="#000000" d="M1230,-493.5C1230,-493.5 1260,-493.5 1260,-493.5 1266,-493.5 1272,-499.5 1272,-505.5 1272,-505.5 1272,-517.5 1272,-517.5 1272,-523.5 1266,-529.5 1260,-529.5 1260,-529.5 1230,-529.5 1230,-529.5 1224,-529.5 1218,-523.5 1218,-517.5 1218,-517.5 1218,-505.5 1218,-505.5 1218,-499.5 1224,-493.5 1230,-493.5"/>
<text text-anchor="middle" x="1245" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_realview_vgic_pio&#45;&gt;system_membus_master -->
<g id="edge67" class="edge">
<title>system_realview_vgic_pio&#45;&gt;system_membus_master</title>
<path fill="none" stroke="black" d="M1227.28,-485.81C1221.29,-479.25 1214.05,-472.91 1206,-469 1029.16,-383.13 385.57,-380.71 239.58,-381.3"/>
<polygon fill="black" stroke="black" points="1224.6,-488.06 1233.71,-493.47 1229.97,-483.56 1224.6,-488.06"/>
</g>
<!-- system_cpu0_icache_port -->
<g id="node38" class="node">
<title>system_cpu0_icache_port</title>
<path fill="#959ead" stroke="#000000" d="M2146,-171.5C2146,-171.5 2208,-171.5 2208,-171.5 2214,-171.5 2220,-177.5 2220,-183.5 2220,-183.5 2220,-195.5 2220,-195.5 2220,-201.5 2214,-207.5 2208,-207.5 2208,-207.5 2146,-207.5 2146,-207.5 2140,-207.5 2134,-201.5 2134,-195.5 2134,-195.5 2134,-183.5 2134,-183.5 2134,-177.5 2140,-171.5 2146,-171.5"/>
<text text-anchor="middle" x="2177" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">icache_port</text>
</g>
<!-- system_cpu0_icache_cpu_side -->
<g id="node41" class="node">
<title>system_cpu0_icache_cpu_side</title>
<path fill="#94918b" stroke="#000000" d="M2322.5,-40.5C2322.5,-40.5 2369.5,-40.5 2369.5,-40.5 2375.5,-40.5 2381.5,-46.5 2381.5,-52.5 2381.5,-52.5 2381.5,-64.5 2381.5,-64.5 2381.5,-70.5 2375.5,-76.5 2369.5,-76.5 2369.5,-76.5 2322.5,-76.5 2322.5,-76.5 2316.5,-76.5 2310.5,-70.5 2310.5,-64.5 2310.5,-64.5 2310.5,-52.5 2310.5,-52.5 2310.5,-46.5 2316.5,-40.5 2322.5,-40.5"/>
<text text-anchor="middle" x="2346" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_cpu0_icache_port&#45;&gt;system_cpu0_icache_cpu_side -->
<g id="edge68" class="edge">
<title>system_cpu0_icache_port&#45;&gt;system_cpu0_icache_cpu_side</title>
<path fill="none" stroke="black" d="M2199.44,-171.37C2229.24,-148.62 2281.99,-108.36 2315.41,-82.85"/>
<polygon fill="black" stroke="black" points="2317.64,-85.55 2323.47,-76.7 2313.39,-79.99 2317.64,-85.55"/>
</g>
<!-- system_cpu0_dcache_port -->
<g id="node39" class="node">
<title>system_cpu0_dcache_port</title>
<path fill="#959ead" stroke="#000000" d="M2036.5,-171.5C2036.5,-171.5 2103.5,-171.5 2103.5,-171.5 2109.5,-171.5 2115.5,-177.5 2115.5,-183.5 2115.5,-183.5 2115.5,-195.5 2115.5,-195.5 2115.5,-201.5 2109.5,-207.5 2103.5,-207.5 2103.5,-207.5 2036.5,-207.5 2036.5,-207.5 2030.5,-207.5 2024.5,-201.5 2024.5,-195.5 2024.5,-195.5 2024.5,-183.5 2024.5,-183.5 2024.5,-177.5 2030.5,-171.5 2036.5,-171.5"/>
<text text-anchor="middle" x="2070" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">dcache_port</text>
</g>
<!-- system_cpu0_dcache_cpu_side -->
<g id="node45" class="node">
<title>system_cpu0_dcache_cpu_side</title>
<path fill="#94918b" stroke="#000000" d="M2073.5,-40.5C2073.5,-40.5 2120.5,-40.5 2120.5,-40.5 2126.5,-40.5 2132.5,-46.5 2132.5,-52.5 2132.5,-52.5 2132.5,-64.5 2132.5,-64.5 2132.5,-70.5 2126.5,-76.5 2120.5,-76.5 2120.5,-76.5 2073.5,-76.5 2073.5,-76.5 2067.5,-76.5 2061.5,-70.5 2061.5,-64.5 2061.5,-64.5 2061.5,-52.5 2061.5,-52.5 2061.5,-46.5 2067.5,-40.5 2073.5,-40.5"/>
<text text-anchor="middle" x="2097" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_cpu0_dcache_port&#45;&gt;system_cpu0_dcache_cpu_side -->
<g id="edge69" class="edge">
<title>system_cpu0_dcache_port&#45;&gt;system_cpu0_dcache_cpu_side</title>
<path fill="none" stroke="black" d="M2073.59,-171.37C2078.12,-149.68 2086,-112.08 2091.35,-86.51"/>
<polygon fill="black" stroke="black" points="2094.78,-87.21 2093.4,-76.7 2087.93,-85.77 2094.78,-87.21"/>
</g>
<!-- system_cpu1_icache_port -->
<g id="node46" class="node">
<title>system_cpu1_icache_port</title>
<path fill="#959ead" stroke="#000000" d="M2596,-171.5C2596,-171.5 2658,-171.5 2658,-171.5 2664,-171.5 2670,-177.5 2670,-183.5 2670,-183.5 2670,-195.5 2670,-195.5 2670,-201.5 2664,-207.5 2658,-207.5 2658,-207.5 2596,-207.5 2596,-207.5 2590,-207.5 2584,-201.5 2584,-195.5 2584,-195.5 2584,-183.5 2584,-183.5 2584,-177.5 2590,-171.5 2596,-171.5"/>
<text text-anchor="middle" x="2627" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">icache_port</text>
</g>
<!-- system_cpu1_icache_cpu_side -->
<g id="node49" class="node">
<title>system_cpu1_icache_cpu_side</title>
<path fill="#94918b" stroke="#000000" d="M2702.5,-40.5C2702.5,-40.5 2749.5,-40.5 2749.5,-40.5 2755.5,-40.5 2761.5,-46.5 2761.5,-52.5 2761.5,-52.5 2761.5,-64.5 2761.5,-64.5 2761.5,-70.5 2755.5,-76.5 2749.5,-76.5 2749.5,-76.5 2702.5,-76.5 2702.5,-76.5 2696.5,-76.5 2690.5,-70.5 2690.5,-64.5 2690.5,-64.5 2690.5,-52.5 2690.5,-52.5 2690.5,-46.5 2696.5,-40.5 2702.5,-40.5"/>
<text text-anchor="middle" x="2726" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_cpu1_icache_port&#45;&gt;system_cpu1_icache_cpu_side -->
<g id="edge70" class="edge">
<title>system_cpu1_icache_port&#45;&gt;system_cpu1_icache_cpu_side</title>
<path fill="none" stroke="black" d="M2641.79,-171.26C2652.85,-158.22 2668.2,-139.74 2681,-123 2690.35,-110.77 2700.3,-96.85 2708.45,-85.16"/>
<polygon fill="black" stroke="black" points="2711.48,-86.94 2714.3,-76.72 2705.73,-82.95 2711.48,-86.94"/>
</g>
<!-- system_cpu1_dcache_port -->
<g id="node47" class="node">
<title>system_cpu1_dcache_port</title>
<path fill="#959ead" stroke="#000000" d="M2700.5,-171.5C2700.5,-171.5 2767.5,-171.5 2767.5,-171.5 2773.5,-171.5 2779.5,-177.5 2779.5,-183.5 2779.5,-183.5 2779.5,-195.5 2779.5,-195.5 2779.5,-201.5 2773.5,-207.5 2767.5,-207.5 2767.5,-207.5 2700.5,-207.5 2700.5,-207.5 2694.5,-207.5 2688.5,-201.5 2688.5,-195.5 2688.5,-195.5 2688.5,-183.5 2688.5,-183.5 2688.5,-177.5 2694.5,-171.5 2700.5,-171.5"/>
<text text-anchor="middle" x="2734" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">dcache_port</text>
</g>
<!-- system_cpu1_dcache_cpu_side -->
<g id="node53" class="node">
<title>system_cpu1_dcache_cpu_side</title>
<path fill="#94918b" stroke="#000000" d="M2854.5,-40.5C2854.5,-40.5 2901.5,-40.5 2901.5,-40.5 2907.5,-40.5 2913.5,-46.5 2913.5,-52.5 2913.5,-52.5 2913.5,-64.5 2913.5,-64.5 2913.5,-70.5 2907.5,-76.5 2901.5,-76.5 2901.5,-76.5 2854.5,-76.5 2854.5,-76.5 2848.5,-76.5 2842.5,-70.5 2842.5,-64.5 2842.5,-64.5 2842.5,-52.5 2842.5,-52.5 2842.5,-46.5 2848.5,-40.5 2854.5,-40.5"/>
<text text-anchor="middle" x="2878" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_cpu1_dcache_port&#45;&gt;system_cpu1_dcache_cpu_side -->
<g id="edge71" class="edge">
<title>system_cpu1_dcache_port&#45;&gt;system_cpu1_dcache_cpu_side</title>
<path fill="none" stroke="black" d="M2753.12,-171.37C2778.3,-148.82 2822.69,-109.04 2851.21,-83.5"/>
<polygon fill="black" stroke="black" points="2853.69,-85.98 2858.8,-76.7 2849.02,-80.77 2853.69,-85.98"/>
</g>
<!-- system_cpu2_icache_port -->
<g id="node54" class="node">
<title>system_cpu2_icache_port</title>
<path fill="#959ead" stroke="#000000" d="M3226,-171.5C3226,-171.5 3288,-171.5 3288,-171.5 3294,-171.5 3300,-177.5 3300,-183.5 3300,-183.5 3300,-195.5 3300,-195.5 3300,-201.5 3294,-207.5 3288,-207.5 3288,-207.5 3226,-207.5 3226,-207.5 3220,-207.5 3214,-201.5 3214,-195.5 3214,-195.5 3214,-183.5 3214,-183.5 3214,-177.5 3220,-171.5 3226,-171.5"/>
<text text-anchor="middle" x="3257" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">icache_port</text>
</g>
<!-- system_cpu2_icache_cpu_side -->
<g id="node57" class="node">
<title>system_cpu2_icache_cpu_side</title>
<path fill="#94918b" stroke="#000000" d="M3402.5,-40.5C3402.5,-40.5 3449.5,-40.5 3449.5,-40.5 3455.5,-40.5 3461.5,-46.5 3461.5,-52.5 3461.5,-52.5 3461.5,-64.5 3461.5,-64.5 3461.5,-70.5 3455.5,-76.5 3449.5,-76.5 3449.5,-76.5 3402.5,-76.5 3402.5,-76.5 3396.5,-76.5 3390.5,-70.5 3390.5,-64.5 3390.5,-64.5 3390.5,-52.5 3390.5,-52.5 3390.5,-46.5 3396.5,-40.5 3402.5,-40.5"/>
<text text-anchor="middle" x="3426" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_cpu2_icache_port&#45;&gt;system_cpu2_icache_cpu_side -->
<g id="edge72" class="edge">
<title>system_cpu2_icache_port&#45;&gt;system_cpu2_icache_cpu_side</title>
<path fill="none" stroke="black" d="M3279.44,-171.37C3309.24,-148.62 3361.99,-108.36 3395.41,-82.85"/>
<polygon fill="black" stroke="black" points="3397.64,-85.55 3403.47,-76.7 3393.39,-79.99 3397.64,-85.55"/>
</g>
<!-- system_cpu2_dcache_port -->
<g id="node55" class="node">
<title>system_cpu2_dcache_port</title>
<path fill="#959ead" stroke="#000000" d="M3116.5,-171.5C3116.5,-171.5 3183.5,-171.5 3183.5,-171.5 3189.5,-171.5 3195.5,-177.5 3195.5,-183.5 3195.5,-183.5 3195.5,-195.5 3195.5,-195.5 3195.5,-201.5 3189.5,-207.5 3183.5,-207.5 3183.5,-207.5 3116.5,-207.5 3116.5,-207.5 3110.5,-207.5 3104.5,-201.5 3104.5,-195.5 3104.5,-195.5 3104.5,-183.5 3104.5,-183.5 3104.5,-177.5 3110.5,-171.5 3116.5,-171.5"/>
<text text-anchor="middle" x="3150" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">dcache_port</text>
</g>
<!-- system_cpu2_dcache_cpu_side -->
<g id="node61" class="node">
<title>system_cpu2_dcache_cpu_side</title>
<path fill="#94918b" stroke="#000000" d="M3153.5,-40.5C3153.5,-40.5 3200.5,-40.5 3200.5,-40.5 3206.5,-40.5 3212.5,-46.5 3212.5,-52.5 3212.5,-52.5 3212.5,-64.5 3212.5,-64.5 3212.5,-70.5 3206.5,-76.5 3200.5,-76.5 3200.5,-76.5 3153.5,-76.5 3153.5,-76.5 3147.5,-76.5 3141.5,-70.5 3141.5,-64.5 3141.5,-64.5 3141.5,-52.5 3141.5,-52.5 3141.5,-46.5 3147.5,-40.5 3153.5,-40.5"/>
<text text-anchor="middle" x="3177" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_cpu2_dcache_port&#45;&gt;system_cpu2_dcache_cpu_side -->
<g id="edge73" class="edge">
<title>system_cpu2_dcache_port&#45;&gt;system_cpu2_dcache_cpu_side</title>
<path fill="none" stroke="black" d="M3153.59,-171.37C3158.12,-149.68 3166,-112.08 3171.35,-86.51"/>
<polygon fill="black" stroke="black" points="3174.78,-87.21 3173.4,-76.7 3167.93,-85.77 3174.78,-87.21"/>
</g>
<!-- system_cpu3_icache_port -->
<g id="node62" class="node">
<title>system_cpu3_icache_port</title>
<path fill="#959ead" stroke="#000000" d="M3676,-171.5C3676,-171.5 3738,-171.5 3738,-171.5 3744,-171.5 3750,-177.5 3750,-183.5 3750,-183.5 3750,-195.5 3750,-195.5 3750,-201.5 3744,-207.5 3738,-207.5 3738,-207.5 3676,-207.5 3676,-207.5 3670,-207.5 3664,-201.5 3664,-195.5 3664,-195.5 3664,-183.5 3664,-183.5 3664,-177.5 3670,-171.5 3676,-171.5"/>
<text text-anchor="middle" x="3707" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">icache_port</text>
</g>
<!-- system_cpu3_icache_cpu_side -->
<g id="node65" class="node">
<title>system_cpu3_icache_cpu_side</title>
<path fill="#94918b" stroke="#000000" d="M3782.5,-40.5C3782.5,-40.5 3829.5,-40.5 3829.5,-40.5 3835.5,-40.5 3841.5,-46.5 3841.5,-52.5 3841.5,-52.5 3841.5,-64.5 3841.5,-64.5 3841.5,-70.5 3835.5,-76.5 3829.5,-76.5 3829.5,-76.5 3782.5,-76.5 3782.5,-76.5 3776.5,-76.5 3770.5,-70.5 3770.5,-64.5 3770.5,-64.5 3770.5,-52.5 3770.5,-52.5 3770.5,-46.5 3776.5,-40.5 3782.5,-40.5"/>
<text text-anchor="middle" x="3806" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_cpu3_icache_port&#45;&gt;system_cpu3_icache_cpu_side -->
<g id="edge74" class="edge">
<title>system_cpu3_icache_port&#45;&gt;system_cpu3_icache_cpu_side</title>
<path fill="none" stroke="black" d="M3721.79,-171.26C3732.85,-158.22 3748.2,-139.74 3761,-123 3770.35,-110.77 3780.3,-96.85 3788.45,-85.16"/>
<polygon fill="black" stroke="black" points="3791.48,-86.94 3794.3,-76.72 3785.73,-82.95 3791.48,-86.94"/>
</g>
<!-- system_cpu3_dcache_port -->
<g id="node63" class="node">
<title>system_cpu3_dcache_port</title>
<path fill="#959ead" stroke="#000000" d="M3780.5,-171.5C3780.5,-171.5 3847.5,-171.5 3847.5,-171.5 3853.5,-171.5 3859.5,-177.5 3859.5,-183.5 3859.5,-183.5 3859.5,-195.5 3859.5,-195.5 3859.5,-201.5 3853.5,-207.5 3847.5,-207.5 3847.5,-207.5 3780.5,-207.5 3780.5,-207.5 3774.5,-207.5 3768.5,-201.5 3768.5,-195.5 3768.5,-195.5 3768.5,-183.5 3768.5,-183.5 3768.5,-177.5 3774.5,-171.5 3780.5,-171.5"/>
<text text-anchor="middle" x="3814" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">dcache_port</text>
</g>
<!-- system_cpu3_dcache_cpu_side -->
<g id="node69" class="node">
<title>system_cpu3_dcache_cpu_side</title>
<path fill="#94918b" stroke="#000000" d="M3934.5,-40.5C3934.5,-40.5 3981.5,-40.5 3981.5,-40.5 3987.5,-40.5 3993.5,-46.5 3993.5,-52.5 3993.5,-52.5 3993.5,-64.5 3993.5,-64.5 3993.5,-70.5 3987.5,-76.5 3981.5,-76.5 3981.5,-76.5 3934.5,-76.5 3934.5,-76.5 3928.5,-76.5 3922.5,-70.5 3922.5,-64.5 3922.5,-64.5 3922.5,-52.5 3922.5,-52.5 3922.5,-46.5 3928.5,-40.5 3934.5,-40.5"/>
<text text-anchor="middle" x="3958" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_cpu3_dcache_port&#45;&gt;system_cpu3_dcache_cpu_side -->
<g id="edge75" class="edge">
<title>system_cpu3_dcache_port&#45;&gt;system_cpu3_dcache_cpu_side</title>
<path fill="none" stroke="black" d="M3833.12,-171.37C3858.3,-148.82 3902.69,-109.04 3931.21,-83.5"/>
<polygon fill="black" stroke="black" points="3933.69,-85.98 3938.8,-76.7 3929.02,-80.77 3933.69,-85.98"/>
</g>
<!-- system_cpu4_icache_port -->
<g id="node70" class="node">
<title>system_cpu4_icache_port</title>
<path fill="#959ead" stroke="#000000" d="M4306,-171.5C4306,-171.5 4368,-171.5 4368,-171.5 4374,-171.5 4380,-177.5 4380,-183.5 4380,-183.5 4380,-195.5 4380,-195.5 4380,-201.5 4374,-207.5 4368,-207.5 4368,-207.5 4306,-207.5 4306,-207.5 4300,-207.5 4294,-201.5 4294,-195.5 4294,-195.5 4294,-183.5 4294,-183.5 4294,-177.5 4300,-171.5 4306,-171.5"/>
<text text-anchor="middle" x="4337" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">icache_port</text>
</g>
<!-- system_cpu4_icache_cpu_side -->
<g id="node73" class="node">
<title>system_cpu4_icache_cpu_side</title>
<path fill="#94918b" stroke="#000000" d="M4482.5,-40.5C4482.5,-40.5 4529.5,-40.5 4529.5,-40.5 4535.5,-40.5 4541.5,-46.5 4541.5,-52.5 4541.5,-52.5 4541.5,-64.5 4541.5,-64.5 4541.5,-70.5 4535.5,-76.5 4529.5,-76.5 4529.5,-76.5 4482.5,-76.5 4482.5,-76.5 4476.5,-76.5 4470.5,-70.5 4470.5,-64.5 4470.5,-64.5 4470.5,-52.5 4470.5,-52.5 4470.5,-46.5 4476.5,-40.5 4482.5,-40.5"/>
<text text-anchor="middle" x="4506" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_cpu4_icache_port&#45;&gt;system_cpu4_icache_cpu_side -->
<g id="edge76" class="edge">
<title>system_cpu4_icache_port&#45;&gt;system_cpu4_icache_cpu_side</title>
<path fill="none" stroke="black" d="M4359.44,-171.37C4389.24,-148.62 4441.99,-108.36 4475.41,-82.85"/>
<polygon fill="black" stroke="black" points="4477.64,-85.55 4483.47,-76.7 4473.39,-79.99 4477.64,-85.55"/>
</g>
<!-- system_cpu4_dcache_port -->
<g id="node71" class="node">
<title>system_cpu4_dcache_port</title>
<path fill="#959ead" stroke="#000000" d="M4196.5,-171.5C4196.5,-171.5 4263.5,-171.5 4263.5,-171.5 4269.5,-171.5 4275.5,-177.5 4275.5,-183.5 4275.5,-183.5 4275.5,-195.5 4275.5,-195.5 4275.5,-201.5 4269.5,-207.5 4263.5,-207.5 4263.5,-207.5 4196.5,-207.5 4196.5,-207.5 4190.5,-207.5 4184.5,-201.5 4184.5,-195.5 4184.5,-195.5 4184.5,-183.5 4184.5,-183.5 4184.5,-177.5 4190.5,-171.5 4196.5,-171.5"/>
<text text-anchor="middle" x="4230" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">dcache_port</text>
</g>
<!-- system_cpu4_dcache_cpu_side -->
<g id="node77" class="node">
<title>system_cpu4_dcache_cpu_side</title>
<path fill="#94918b" stroke="#000000" d="M4233.5,-40.5C4233.5,-40.5 4280.5,-40.5 4280.5,-40.5 4286.5,-40.5 4292.5,-46.5 4292.5,-52.5 4292.5,-52.5 4292.5,-64.5 4292.5,-64.5 4292.5,-70.5 4286.5,-76.5 4280.5,-76.5 4280.5,-76.5 4233.5,-76.5 4233.5,-76.5 4227.5,-76.5 4221.5,-70.5 4221.5,-64.5 4221.5,-64.5 4221.5,-52.5 4221.5,-52.5 4221.5,-46.5 4227.5,-40.5 4233.5,-40.5"/>
<text text-anchor="middle" x="4257" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_cpu4_dcache_port&#45;&gt;system_cpu4_dcache_cpu_side -->
<g id="edge77" class="edge">
<title>system_cpu4_dcache_port&#45;&gt;system_cpu4_dcache_cpu_side</title>
<path fill="none" stroke="black" d="M4233.59,-171.37C4238.12,-149.68 4246,-112.08 4251.35,-86.51"/>
<polygon fill="black" stroke="black" points="4254.78,-87.21 4253.4,-76.7 4247.93,-85.77 4254.78,-87.21"/>
</g>
<!-- system_cpu5_icache_port -->
<g id="node78" class="node">
<title>system_cpu5_icache_port</title>
<path fill="#959ead" stroke="#000000" d="M4756,-171.5C4756,-171.5 4818,-171.5 4818,-171.5 4824,-171.5 4830,-177.5 4830,-183.5 4830,-183.5 4830,-195.5 4830,-195.5 4830,-201.5 4824,-207.5 4818,-207.5 4818,-207.5 4756,-207.5 4756,-207.5 4750,-207.5 4744,-201.5 4744,-195.5 4744,-195.5 4744,-183.5 4744,-183.5 4744,-177.5 4750,-171.5 4756,-171.5"/>
<text text-anchor="middle" x="4787" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">icache_port</text>
</g>
<!-- system_cpu5_icache_cpu_side -->
<g id="node81" class="node">
<title>system_cpu5_icache_cpu_side</title>
<path fill="#94918b" stroke="#000000" d="M4862.5,-40.5C4862.5,-40.5 4909.5,-40.5 4909.5,-40.5 4915.5,-40.5 4921.5,-46.5 4921.5,-52.5 4921.5,-52.5 4921.5,-64.5 4921.5,-64.5 4921.5,-70.5 4915.5,-76.5 4909.5,-76.5 4909.5,-76.5 4862.5,-76.5 4862.5,-76.5 4856.5,-76.5 4850.5,-70.5 4850.5,-64.5 4850.5,-64.5 4850.5,-52.5 4850.5,-52.5 4850.5,-46.5 4856.5,-40.5 4862.5,-40.5"/>
<text text-anchor="middle" x="4886" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_cpu5_icache_port&#45;&gt;system_cpu5_icache_cpu_side -->
<g id="edge78" class="edge">
<title>system_cpu5_icache_port&#45;&gt;system_cpu5_icache_cpu_side</title>
<path fill="none" stroke="black" d="M4801.79,-171.26C4812.85,-158.22 4828.2,-139.74 4841,-123 4850.35,-110.77 4860.3,-96.85 4868.45,-85.16"/>
<polygon fill="black" stroke="black" points="4871.48,-86.94 4874.3,-76.72 4865.73,-82.95 4871.48,-86.94"/>
</g>
<!-- system_cpu5_dcache_port -->
<g id="node79" class="node">
<title>system_cpu5_dcache_port</title>
<path fill="#959ead" stroke="#000000" d="M4860.5,-171.5C4860.5,-171.5 4927.5,-171.5 4927.5,-171.5 4933.5,-171.5 4939.5,-177.5 4939.5,-183.5 4939.5,-183.5 4939.5,-195.5 4939.5,-195.5 4939.5,-201.5 4933.5,-207.5 4927.5,-207.5 4927.5,-207.5 4860.5,-207.5 4860.5,-207.5 4854.5,-207.5 4848.5,-201.5 4848.5,-195.5 4848.5,-195.5 4848.5,-183.5 4848.5,-183.5 4848.5,-177.5 4854.5,-171.5 4860.5,-171.5"/>
<text text-anchor="middle" x="4894" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">dcache_port</text>
</g>
<!-- system_cpu5_dcache_cpu_side -->
<g id="node85" class="node">
<title>system_cpu5_dcache_cpu_side</title>
<path fill="#94918b" stroke="#000000" d="M5014.5,-40.5C5014.5,-40.5 5061.5,-40.5 5061.5,-40.5 5067.5,-40.5 5073.5,-46.5 5073.5,-52.5 5073.5,-52.5 5073.5,-64.5 5073.5,-64.5 5073.5,-70.5 5067.5,-76.5 5061.5,-76.5 5061.5,-76.5 5014.5,-76.5 5014.5,-76.5 5008.5,-76.5 5002.5,-70.5 5002.5,-64.5 5002.5,-64.5 5002.5,-52.5 5002.5,-52.5 5002.5,-46.5 5008.5,-40.5 5014.5,-40.5"/>
<text text-anchor="middle" x="5038" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_cpu5_dcache_port&#45;&gt;system_cpu5_dcache_cpu_side -->
<g id="edge79" class="edge">
<title>system_cpu5_dcache_port&#45;&gt;system_cpu5_dcache_cpu_side</title>
<path fill="none" stroke="black" d="M4913.12,-171.37C4938.3,-148.82 4982.69,-109.04 5011.21,-83.5"/>
<polygon fill="black" stroke="black" points="5013.69,-85.98 5018.8,-76.7 5009.02,-80.77 5013.69,-85.98"/>
</g>
<!-- system_cpu6_icache_port -->
<g id="node86" class="node">
<title>system_cpu6_icache_port</title>
<path fill="#959ead" stroke="#000000" d="M1066,-171.5C1066,-171.5 1128,-171.5 1128,-171.5 1134,-171.5 1140,-177.5 1140,-183.5 1140,-183.5 1140,-195.5 1140,-195.5 1140,-201.5 1134,-207.5 1128,-207.5 1128,-207.5 1066,-207.5 1066,-207.5 1060,-207.5 1054,-201.5 1054,-195.5 1054,-195.5 1054,-183.5 1054,-183.5 1054,-177.5 1060,-171.5 1066,-171.5"/>
<text text-anchor="middle" x="1097" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">icache_port</text>
</g>
<!-- system_cpu6_icache_cpu_side -->
<g id="node89" class="node">
<title>system_cpu6_icache_cpu_side</title>
<path fill="#94918b" stroke="#000000" d="M1242.5,-40.5C1242.5,-40.5 1289.5,-40.5 1289.5,-40.5 1295.5,-40.5 1301.5,-46.5 1301.5,-52.5 1301.5,-52.5 1301.5,-64.5 1301.5,-64.5 1301.5,-70.5 1295.5,-76.5 1289.5,-76.5 1289.5,-76.5 1242.5,-76.5 1242.5,-76.5 1236.5,-76.5 1230.5,-70.5 1230.5,-64.5 1230.5,-64.5 1230.5,-52.5 1230.5,-52.5 1230.5,-46.5 1236.5,-40.5 1242.5,-40.5"/>
<text text-anchor="middle" x="1266" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_cpu6_icache_port&#45;&gt;system_cpu6_icache_cpu_side -->
<g id="edge80" class="edge">
<title>system_cpu6_icache_port&#45;&gt;system_cpu6_icache_cpu_side</title>
<path fill="none" stroke="black" d="M1119.44,-171.37C1149.24,-148.62 1201.99,-108.36 1235.41,-82.85"/>
<polygon fill="black" stroke="black" points="1237.64,-85.55 1243.47,-76.7 1233.39,-79.99 1237.64,-85.55"/>
</g>
<!-- system_cpu6_dcache_port -->
<g id="node87" class="node">
<title>system_cpu6_dcache_port</title>
<path fill="#959ead" stroke="#000000" d="M956.5,-171.5C956.5,-171.5 1023.5,-171.5 1023.5,-171.5 1029.5,-171.5 1035.5,-177.5 1035.5,-183.5 1035.5,-183.5 1035.5,-195.5 1035.5,-195.5 1035.5,-201.5 1029.5,-207.5 1023.5,-207.5 1023.5,-207.5 956.5,-207.5 956.5,-207.5 950.5,-207.5 944.5,-201.5 944.5,-195.5 944.5,-195.5 944.5,-183.5 944.5,-183.5 944.5,-177.5 950.5,-171.5 956.5,-171.5"/>
<text text-anchor="middle" x="990" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">dcache_port</text>
</g>
<!-- system_cpu6_dcache_cpu_side -->
<g id="node93" class="node">
<title>system_cpu6_dcache_cpu_side</title>
<path fill="#94918b" stroke="#000000" d="M993.5,-40.5C993.5,-40.5 1040.5,-40.5 1040.5,-40.5 1046.5,-40.5 1052.5,-46.5 1052.5,-52.5 1052.5,-52.5 1052.5,-64.5 1052.5,-64.5 1052.5,-70.5 1046.5,-76.5 1040.5,-76.5 1040.5,-76.5 993.5,-76.5 993.5,-76.5 987.5,-76.5 981.5,-70.5 981.5,-64.5 981.5,-64.5 981.5,-52.5 981.5,-52.5 981.5,-46.5 987.5,-40.5 993.5,-40.5"/>
<text text-anchor="middle" x="1017" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_cpu6_dcache_port&#45;&gt;system_cpu6_dcache_cpu_side -->
<g id="edge81" class="edge">
<title>system_cpu6_dcache_port&#45;&gt;system_cpu6_dcache_cpu_side</title>
<path fill="none" stroke="black" d="M993.59,-171.37C998.12,-149.68 1006,-112.08 1011.35,-86.51"/>
<polygon fill="black" stroke="black" points="1014.78,-87.21 1013.4,-76.7 1007.93,-85.77 1014.78,-87.21"/>
</g>
<!-- system_cpu7_icache_port -->
<g id="node94" class="node">
<title>system_cpu7_icache_port</title>
<path fill="#959ead" stroke="#000000" d="M1606,-171.5C1606,-171.5 1668,-171.5 1668,-171.5 1674,-171.5 1680,-177.5 1680,-183.5 1680,-183.5 1680,-195.5 1680,-195.5 1680,-201.5 1674,-207.5 1668,-207.5 1668,-207.5 1606,-207.5 1606,-207.5 1600,-207.5 1594,-201.5 1594,-195.5 1594,-195.5 1594,-183.5 1594,-183.5 1594,-177.5 1600,-171.5 1606,-171.5"/>
<text text-anchor="middle" x="1637" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">icache_port</text>
</g>
<!-- system_cpu7_icache_cpu_side -->
<g id="node97" class="node">
<title>system_cpu7_icache_cpu_side</title>
<path fill="#94918b" stroke="#000000" d="M1782.5,-40.5C1782.5,-40.5 1829.5,-40.5 1829.5,-40.5 1835.5,-40.5 1841.5,-46.5 1841.5,-52.5 1841.5,-52.5 1841.5,-64.5 1841.5,-64.5 1841.5,-70.5 1835.5,-76.5 1829.5,-76.5 1829.5,-76.5 1782.5,-76.5 1782.5,-76.5 1776.5,-76.5 1770.5,-70.5 1770.5,-64.5 1770.5,-64.5 1770.5,-52.5 1770.5,-52.5 1770.5,-46.5 1776.5,-40.5 1782.5,-40.5"/>
<text text-anchor="middle" x="1806" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_cpu7_icache_port&#45;&gt;system_cpu7_icache_cpu_side -->
<g id="edge82" class="edge">
<title>system_cpu7_icache_port&#45;&gt;system_cpu7_icache_cpu_side</title>
<path fill="none" stroke="black" d="M1659.44,-171.37C1689.24,-148.62 1741.99,-108.36 1775.41,-82.85"/>
<polygon fill="black" stroke="black" points="1777.64,-85.55 1783.47,-76.7 1773.39,-79.99 1777.64,-85.55"/>
</g>
<!-- system_cpu7_dcache_port -->
<g id="node95" class="node">
<title>system_cpu7_dcache_port</title>
<path fill="#959ead" stroke="#000000" d="M1496.5,-171.5C1496.5,-171.5 1563.5,-171.5 1563.5,-171.5 1569.5,-171.5 1575.5,-177.5 1575.5,-183.5 1575.5,-183.5 1575.5,-195.5 1575.5,-195.5 1575.5,-201.5 1569.5,-207.5 1563.5,-207.5 1563.5,-207.5 1496.5,-207.5 1496.5,-207.5 1490.5,-207.5 1484.5,-201.5 1484.5,-195.5 1484.5,-195.5 1484.5,-183.5 1484.5,-183.5 1484.5,-177.5 1490.5,-171.5 1496.5,-171.5"/>
<text text-anchor="middle" x="1530" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">dcache_port</text>
</g>
<!-- system_cpu7_dcache_cpu_side -->
<g id="node101" class="node">
<title>system_cpu7_dcache_cpu_side</title>
<path fill="#94918b" stroke="#000000" d="M1533.5,-40.5C1533.5,-40.5 1580.5,-40.5 1580.5,-40.5 1586.5,-40.5 1592.5,-46.5 1592.5,-52.5 1592.5,-52.5 1592.5,-64.5 1592.5,-64.5 1592.5,-70.5 1586.5,-76.5 1580.5,-76.5 1580.5,-76.5 1533.5,-76.5 1533.5,-76.5 1527.5,-76.5 1521.5,-70.5 1521.5,-64.5 1521.5,-64.5 1521.5,-52.5 1521.5,-52.5 1521.5,-46.5 1527.5,-40.5 1533.5,-40.5"/>
<text text-anchor="middle" x="1557" y="-54.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_cpu7_dcache_port&#45;&gt;system_cpu7_dcache_cpu_side -->
<g id="edge83" class="edge">
<title>system_cpu7_dcache_port&#45;&gt;system_cpu7_dcache_cpu_side</title>
<path fill="none" stroke="black" d="M1533.59,-171.37C1538.12,-149.68 1546,-112.08 1551.35,-86.51"/>
<polygon fill="black" stroke="black" points="1554.78,-87.21 1553.4,-76.7 1547.93,-85.77 1554.78,-87.21"/>
</g>
<!-- system_iobus_slave -->
<g id="node106" class="node">
<title>system_iobus_slave</title>
<path fill="#586070" stroke="#000000" d="M2226,-362.5C2226,-362.5 2256,-362.5 2256,-362.5 2262,-362.5 2268,-368.5 2268,-374.5 2268,-374.5 2268,-386.5 2268,-386.5 2268,-392.5 2262,-398.5 2256,-398.5 2256,-398.5 2226,-398.5 2226,-398.5 2220,-398.5 2214,-392.5 2214,-386.5 2214,-386.5 2214,-374.5 2214,-374.5 2214,-368.5 2220,-362.5 2226,-362.5"/>
<text text-anchor="middle" x="2241" y="-376.8" font-family="Arial" font-size="14.00" fill="#000000">slave</text>
</g>
<!-- system_iobus_slave&#45;&gt;system_bridge_master -->
<g id="edge84" class="edge">
<title>system_iobus_slave&#45;&gt;system_bridge_master</title>
<path fill="none" stroke="black" d="M2212.61,-357.17C2210.13,-355.91 2207.58,-354.83 2205,-354 2183.03,-346.95 562.28,-360.07 544,-346 501.01,-312.91 499.06,-240.67 500.63,-207.62"/>
<polygon fill="black" stroke="black" points="2210.86,-360.2 2221.24,-362.31 2214.44,-354.18 2210.86,-360.2"/>
</g>
<!-- system_pci_ide_dma -->
<g id="node107" class="node">
<title>system_pci_ide_dma</title>
<path fill="#9f8575" stroke="#000000" d="M3100,-493.5C3100,-493.5 3130,-493.5 3130,-493.5 3136,-493.5 3142,-499.5 3142,-505.5 3142,-505.5 3142,-517.5 3142,-517.5 3142,-523.5 3136,-529.5 3130,-529.5 3130,-529.5 3100,-529.5 3100,-529.5 3094,-529.5 3088,-523.5 3088,-517.5 3088,-517.5 3088,-505.5 3088,-505.5 3088,-499.5 3094,-493.5 3100,-493.5"/>
<text text-anchor="middle" x="3115" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">dma</text>
</g>
<!-- system_pci_ide_dma&#45;&gt;system_iobus_slave -->
<g id="edge85" class="edge">
<title>system_pci_ide_dma&#45;&gt;system_iobus_slave</title>
<path fill="none" stroke="black" d="M3104.52,-493.13C3098.26,-484.37 3089.49,-474.46 3079,-469 3042.89,-450.2 2435.79,-397.92 2278.15,-384.61"/>
<polygon fill="black" stroke="black" points="2278.27,-381.11 2268.01,-383.76 2277.68,-388.09 2278.27,-381.11"/>
</g>
<!-- system_pci_ide_pio -->
<g id="node108" class="node">
<title>system_pci_ide_pio</title>
<path fill="#9f8575" stroke="#000000" d="M3028,-493.5C3028,-493.5 3058,-493.5 3058,-493.5 3064,-493.5 3070,-499.5 3070,-505.5 3070,-505.5 3070,-517.5 3070,-517.5 3070,-523.5 3064,-529.5 3058,-529.5 3058,-529.5 3028,-529.5 3028,-529.5 3022,-529.5 3016,-523.5 3016,-517.5 3016,-517.5 3016,-505.5 3016,-505.5 3016,-499.5 3022,-493.5 3028,-493.5"/>
<text text-anchor="middle" x="3043" y="-507.8" font-family="Arial" font-size="14.00" fill="#000000">pio</text>
</g>
<!-- system_pci_ide_pio&#45;&gt;system_iobus_master -->
<g id="edge86" class="edge">
<title>system_pci_ide_pio&#45;&gt;system_iobus_master</title>
<path fill="none" stroke="black" d="M3021.44,-485.88C3014.1,-479.16 3005.37,-472.71 2996,-469 2914.24,-436.64 2281.08,-489.08 2205,-445 2187.65,-434.95 2177.01,-413.79 2171.32,-398.66"/>
<polygon fill="black" stroke="black" points="3019.24,-488.63 3028.82,-493.17 3024.16,-483.65 3019.24,-488.63"/>
</g>
<!-- system_iocache_cpu_side -->
<g id="node110" class="node">
<title>system_iocache_cpu_side</title>
<path fill="#94918b" stroke="#000000" d="M666.5,-171.5C666.5,-171.5 713.5,-171.5 713.5,-171.5 719.5,-171.5 725.5,-177.5 725.5,-183.5 725.5,-183.5 725.5,-195.5 725.5,-195.5 725.5,-201.5 719.5,-207.5 713.5,-207.5 713.5,-207.5 666.5,-207.5 666.5,-207.5 660.5,-207.5 654.5,-201.5 654.5,-195.5 654.5,-195.5 654.5,-183.5 654.5,-183.5 654.5,-177.5 660.5,-171.5 666.5,-171.5"/>
<text text-anchor="middle" x="690" y="-185.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_iocache_cpu_side&#45;&gt;system_iobus_master -->
<g id="edge87" class="edge">
<title>system_iocache_cpu_side&#45;&gt;system_iobus_master</title>
<path fill="none" stroke="black" d="M689.52,-217.89C690.54,-253.89 698.38,-316.04 738,-346 766.91,-367.86 1934.83,-377.74 2136.49,-379.28"/>
<polygon fill="black" stroke="black" points="693.01,-217.58 689.39,-207.63 686.01,-217.67 693.01,-217.58"/>
</g>
</g>
</svg>

## full_log_after_cpu1.txt
7306449500: Event: system.cpu1.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 111 executed @ 7306449500
7306449500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306449500
7306449500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306449500
7306449500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306450000
7306449500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306449500
7306449500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306450000
7306449500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306449500
7306449500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306450000
7306450000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306450000
7306450000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306450500
7306450000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306450000
7306450000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306450500
7306450000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306450000
7306450000: Cache: system.cpu1.icache: access for ReadReq [807371c0:807371ff] IF UC D=80a4acd38f550000d07a3fd5fd7f0000c4e07db301000000ace47db301000000150000000000000000f870d08f55000000000000000100000000000000000000 ptr=0x558fc9802480
7306450000: CachePort: system.cpu1.icache.mem_side: Scheduling send event at 7306451000
7306450000: Event: system.cpu1.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 113 scheduled @ 7306451000
7306450000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306450500
7306450500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306450500
7306450500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306451000
7306450500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306450500
7306450500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306451000
7306450500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306450500
7306450500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306451000
7306451000: Event: system.cpu1.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 113 executed @ 7306451000
7306451000: Cache: system.cpu1.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=80a4acd38f550000d07a3fd5fd7f0000c4e07db301000000ace47db301000000150000000000000000f870d08f55000000000000000100000000000000000000 ptr=0x558fc9802480
7306451000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[4] packet ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363435313030300a000000000001000090d4e9cd8f550000 ptr=0x558fc9802100
7306451000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[4] packet ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363435313030300a000000000001000090d4e9cd8f550000 ptr=0x558fc9802100
7306451000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[4] packet ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363435313030300a000000000001000090d4e9cd8f550000 ptr=0x558fc9802100 SF size: 0 lat: 0
7306451000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363435313030300a000000000001000090d4e9cd8f550000 ptr=0x558fc9802100
7306451000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363435313030300a000000000001000090d4e9cd8f550000 ptr=0x558fc9802100
7306451000: CachePort: system.l2.mem_side: Scheduling send event at 7306461500
7306451000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306451500
7306451000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306451000 to 7306451500
7306451000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306451000
7306451000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306451500
7306451000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306451000
7306451000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306451500
7306451000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306451000
7306451000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306451500
7306451500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306451500
7306451500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306451500
7306451500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306452000
7306451500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306451500
7306451500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306452000
7306451500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306451500
7306451500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306452000
7306451750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306451750
7306451750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306451750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 2
7306451750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306451750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600
7306451750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306456750
7306452000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306452000
7306452000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f980
7306452000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[28] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f980
7306452000: Event: system.tol2bus.slave[28]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1343 scheduled @ 7306452500
7306452000: Event: system.tol2bus.respLayer28.wrapped_function_event: EventFunctionWrapped 1344 scheduled @ 7306453500
7306452000: BaseXBar: system.tol2bus.respLayer28: The crossbar layer is now busy from tick 7306452000 to 7306453500
7306452000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306457000
7306452000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306452000
7306452000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306452500
7306452000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306452000
7306452000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306452500
7306452000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306452000
7306452000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306452500
7306452500: Event: system.tol2bus.slave[28]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1343 executed @ 7306452500
7306452500: Cache: system.cpu7.icache: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f980
7306452500: Event: system.cpu7.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 381 scheduled @ 7306454500
7306452500: CacheVerbose: system.cpu7.icache: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f980
7306452500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306452500
7306452500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306453000
7306452500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306452500
7306452500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306453000
7306452500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306452500
7306452500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306453000
7306453000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306453000
7306453000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306453500
7306453000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306453000
7306453000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306453500
7306453000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306453000
7306453000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306453500
7306453500: Event: system.tol2bus.respLayer28.wrapped_function_event: EventFunctionWrapped 1344 executed @ 7306453500
7306453500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306453500
7306449500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306449500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306449500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306453500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306454000
7306453500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306453500
7306453500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306454000
7306453500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306453500
7306453500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306454000
7306454000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306454000
7306454000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306454500
7306454000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306454000
7306454000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306454000
7306454000: Cache: system.cpu1.icache: access for ReadReq [80737180:807371bf] IF UC D=0024d4d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363435343030300a000000000001000090dbe9cd8f550000 ptr=0x558fd070f980
7306454000: CachePort: system.cpu1.icache.mem_side: Scheduling send event at 7306455000
7306454000: Event: system.cpu1.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 113 scheduled @ 7306455000
7306454000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306454500
7306454500: Event: system.cpu7.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 381 executed @ 7306454500
7306454500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306454500
7306454500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306455000
7306454500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306454500
7306454500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306455000
7306455000: Event: system.cpu1.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 113 executed @ 7306455000
7306455000: Cache: system.cpu1.icache: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=0024d4d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363435343030300a000000000001000090dbe9cd8f550000 ptr=0x558fd070f980
7306455000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[4] packet ReadReq [80737180:807371bf] IF UC D=4000d1d18f5500004100005421100091200000b9bf3f03d500fbd2d18f550000000003d28f550000a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80
7306455000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[4] packet ReadReq [80737180:807371bf] IF UC D=4000d1d18f5500004100005421100091200000b9bf3f03d500fbd2d18f550000000003d28f550000a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80
7306455000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[4] packet ReadReq [80737180:807371bf] IF UC D=4000d1d18f5500004100005421100091200000b9bf3f03d500fbd2d18f550000000003d28f550000a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80 SF size: 0 lat: 0
7306455000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=4000d1d18f5500004100005421100091200000b9bf3f03d500fbd2d18f550000000003d28f550000a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80
7306455000: Cache: system.l2: access for ReadReq [80737180:807371bf] IF UC D=4000d1d18f5500004100005421100091200000b9bf3f03d500fbd2d18f550000000003d28f550000a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80
7306455000: CachePort: system.l2.mem_side: Scheduling send event at 7306465500
7306455000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306455500
7306455000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306455000 to 7306455500
7306455000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306455000
7306455000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306455500
7306455000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306455000
7306455000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306455500
7306455500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306455500
7306455500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306455500
7306455500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306456000
7306455500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306455500
7306455500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306456000
7306456000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306456000
7306456000: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=c04bd2d18f5500000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fa00
7306456000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c00ad1d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070f280
7306456000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c00ad1d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070f280
7306456000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c00ad1d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070f280 SF size: 0 lat: 1
7306456000: CoherentXBar: system.membus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=c00ad1d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070f280
7306456000: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x80737180 size 64
7306456000: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306456000: DRAM: system.mem_ctrls: Address: 0x737180 Rank 1 Bank 3 Row 57
7306456000: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306456000: DRAM: system.mem_ctrls: Adding to read queue
7306456000: DRAM: system.mem_ctrls: Request scheduled immediately
7306456000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306456000
7306456000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306457000
7306456000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306456000 to 7306457000
7306456000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306461500
7306456000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306456000
7306456000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306456000: DRAM: system.mem_ctrls: Single request, going to a free rank
7306456000: DRAM: system.mem_ctrls: Timing access to addr 0x737180, rank/bank/row 1 3 57
7306456000: DRAM: system.mem_ctrls: Removing burstTick for 7306445000
7306456000: DRAM: system.mem_ctrls: Activate at tick 7306467250
7306456000: DRAM: system.mem_ctrls: Activate bank 3, rank 1 at tick 7306467250, now got 5 active
7306456000: Event: system.mem_ctrls_1.wrapped_function_event: EventFunctionWrapped 19 scheduled @ 7306467250
7306456000: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306481000
7306456000: DRAM: system.mem_ctrls: Access to 0x737180, ready at 7306499750 next burst at 7306486000.
7306456000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306458500
7306456000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306456000
7306456000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306456500
7306456000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306456000
7306456000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306456500
7306456500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306456500
7306456500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306457000
7306456500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306456500
7306456500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306457000
7306456750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306456750
7306456750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306456750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 2
7306456750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306456750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802900
7306456750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306464750
7306457000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306457000
7306457000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306457000
7306457000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737140:8073717f] IF UC D=218c60d3c10000b400f8779240111cd5df3f03d5e13f80d201121cd5a0caffd00000009100c01cd5a07880d200401cd53e401cd540c28152e0039fd6c11900b0 ptr=0x558fd070f480
7306457000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[28] packet ReadResp [80737140:8073717f] IF UC D=218c60d3c10000b400f8779240111cd5df3f03d5e13f80d201121cd5a0caffd00000009100c01cd5a07880d200401cd53e401cd540c28152e0039fd6c11900b0 ptr=0x558fd070f480
7306457000: Event: system.tol2bus.slave[28]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1343 scheduled @ 7306457500
7306457000: Event: system.tol2bus.respLayer28.wrapped_function_event: EventFunctionWrapped 1344 scheduled @ 7306458500
7306457000: BaseXBar: system.tol2bus.respLayer28: The crossbar layer is now busy from tick 7306457000 to 7306458500
7306457000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306457000
7306457000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306457500
7306457000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306457000
7306457000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306457500
7306457500: Event: system.tol2bus.slave[28]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1343 executed @ 7306457500
7306457500: Cache: system.cpu7.icache: recvTimingResp: Handling response ReadResp [80737140:8073717f] IF UC D=218c60d3c10000b400f8779240111cd5df3f03d5e13f80d201121cd5a0caffd00000009100c01cd5a07880d200401cd53e401cd540c28152e0039fd6c11900b0 ptr=0x558fd070f480
7306457500: Event: system.cpu7.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 381 scheduled @ 7306459500
7306457500: CacheVerbose: system.cpu7.icache: recvTimingResp: Leaving with ReadResp [80737140:8073717f] IF UC D=218c60d3c10000b400f8779240111cd5df3f03d5e13f80d201121cd5a0caffd00000009100c01cd5a07880d200401cd53e401cd540c28152e0039fd6c11900b0 ptr=0x558fd070f480
7306457500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306457500
7306457500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306458000
7306457500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306457500
7306457500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306458000
7306458000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306458000
7306458000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306458500
7306458000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306458000
7306458000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306458500
7306458500: Event: system.tol2bus.respLayer28.wrapped_function_event: EventFunctionWrapped 1344 executed @ 7306458500
7306458500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306458500
7306458500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306458500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306458500
7306458500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306459000
7306458500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306458500
7306458500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306459000
7306459000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306459000
7306459000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306459500
7306459000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306459000
7306459000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306459500
7306459500: Event: system.cpu7.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 381 executed @ 7306459500
7306459500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306459500
7306459500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306459500
7306459500: Cache: system.cpu7.icache: access for ReadReq [80737180:807371bf] IF UC D=0018d1d18f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363435393530300a00001cd540c28152e0039fd6c11900b0 ptr=0x558fc9802800
7306459500: CachePort: system.cpu7.icache.mem_side: Scheduling send event at 7306460500
7306459500: Event: system.cpu7.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 383 scheduled @ 7306460500
7306459500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306460000
7306459500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306459500
7306459500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306459500
7306459500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306460000
7306460000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306460000
7306460000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306460500
7306460000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306460000
7306460000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306460500
7306460500: Event: system.cpu7.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 383 executed @ 7306460500
7306460500: Cache: system.cpu7.icache: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=0018d1d18f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363435393530300a00001cd540c28152e0039fd6c11900b0 ptr=0x558fc9802800
7306460500: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[28] packet ReadReq [80737180:807371bf] IF UC D=0058d2d18f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363436303530300a00000000000000000000000000000000 ptr=0x558fd070f480
7306460500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[28] packet ReadReq [80737180:807371bf] IF UC D=0058d2d18f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363436303530300a00000000000000000000000000000000 ptr=0x558fd070f480
7306460500: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[28] packet ReadReq [80737180:807371bf] IF UC D=0058d2d18f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363436303530300a00000000000000000000000000000000 ptr=0x558fd070f480 SF size: 0 lat: 0
7306460500: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=0058d2d18f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363436303530300a00000000000000000000000000000000 ptr=0x558fd070f480
7306460500: Cache: system.l2: access for ReadReq [80737180:807371bf] IF UC D=0058d2d18f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363436303530300a00000000000000000000000000000000 ptr=0x558fd070f480
7306460500: CachePort: system.l2.mem_side: Scheduling send event at 7306471000
7306460500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306461000
7306460500: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306460500 to 7306461000
7306460500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306460500
7306460500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306461000
7306460500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306460500
7306460500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306461000
7306461000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306461000
7306461000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306461000
7306461000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306461500
7306461000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306461000
7306461000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306461500
7306461500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306461500
7306461500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363435313030300a000000000001000090d4e9cd8f550000 ptr=0x558fc9802100
7306461500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=00d382c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070f580
7306461500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=00d382c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070f580
7306461500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=00d382c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070f580 SF size: 0 lat: 1
7306461500: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=00d382c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070f580
7306461500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306461500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306461500: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306461500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306461500: DRAM: system.mem_ctrls: Adding to read queue
7306461500: DRAM: system.mem_ctrls: Request scheduled immediately
7306461500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306461500
7306461500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306463000
7306461500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306461500 to 7306463000
7306461500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306465500
7306461500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306461500
7306461500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306461500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306461500: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306461500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306486000
7306461500: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306504750 next burst at 7306491000.
7306461500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306463500
7306461500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306461500
7306461500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306462000
7306461500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306461500
7306461500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306462000
7306462000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306462000
7306462000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306462500
7306462000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306462000
7306462000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306462500
7306462500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306462500
7306462500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306463000
7306462500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306462500
7306462500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306463000
7306463000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306463000
7306463000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306463000
7306463000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306463500
7306463000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306463000
7306459500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375164    :   adrp   x1, #3379200      : IntAlu :  D=0x0000000080a70000  FetchSeq=168  CPSeq=34  flags=(IsInteger)
7306463000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306463500
7306463500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306463500
7306463500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306463500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306463500
7306463500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306464000
7306463500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306463500
7306463500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306464000
7306464000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306464000
7306464000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306464500
7306464000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306464000
7306464000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306464500
7306464500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306464500
7306464500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306465000
7306464500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306464500
7306464500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306465000
7306464750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306464750
7306464750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306464750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 2
7306464750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306464750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b00
7306464750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306499750
7306465000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306465000
7306465000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306465500
7306465000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306465000
7306465000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306465500
7306465500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306465500
7306465500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=4000d1d18f5500004100005421100091200000b9bf3f03d500fbd2d18f550000000003d28f550000a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80
7306465500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=0091d6d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802200
7306465500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=0091d6d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802200
7306465500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=0091d6d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802200 SF size: 0 lat: 1
7306465500: CoherentXBar: system.membus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=0091d6d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802200
7306465500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x80737180 size 64
7306465500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306465500: DRAM: system.mem_ctrls: Address: 0x737180 Rank 1 Bank 3 Row 57
7306465500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306465500: DRAM: system.mem_ctrls: Adding to read queue
7306465500: DRAM: system.mem_ctrls: Request scheduled immediately
7306465500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306465500
7306465500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306467000
7306465500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306465500 to 7306467000
7306465500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306471000
7306465500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306465500
7306465500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306465500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306465500: DRAM: system.mem_ctrls: Timing access to addr 0x737180, rank/bank/row 1 3 57
7306465500: DRAM: system.mem_ctrls: Removing burstTick for 7306465000
7306465500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306491000
7306465500: DRAM: system.mem_ctrls: Access to 0x737180, ready at 7306509750 next burst at 7306496000.
7306465500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306468500
7306465500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306465500
7306465500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306466000
7306465500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306465500
7306465500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306466000
7306466000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306466000
7306466000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306466500
7306466000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306466000
7306466000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306466500
7306466500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306466500
7306466500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306467000
7306466500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306466500
7306466500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306467000
7306467000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306467000
7306467000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306467000
7306467000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306467500
7306467000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306467000
7306467000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306467500
7306467250: Event: system.mem_ctrls_1.wrapped_function_event: EventFunctionWrapped 19 executed @ 7306467250
7306467250: Event: system.mem_ctrls_1.wrapped_function_event: EventFunctionWrapped 20 executed @ 7306467250
7306467250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306467250
7306467250: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadExResp [8ef8d000:8ef8d03f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9824000
7306467250: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadExResp [8ef8d000:8ef8d03f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9824000
7306467250: SnoopFilter: system.membus.snoop_filter: updateResponse:   old SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306467250: SnoopFilter: system.membus.snoop_filter: updateResponse:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306467250: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306470000
7306467250: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306473000
7306467250: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306467250 to 7306473000
7306467250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306474750
7306467500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306467500
7306467500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306468000
7306467500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306467500
7306467500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306468000
7306468000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306468000
7306468000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306468500
7306468000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306468000
7306468000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306468500
7306468500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306468500
7306468500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306468500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306468500
7306468500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306469000
7306468500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306468500
7306468500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306469000
7306469000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306469000
7306469000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306469500
7306469000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306469000
7306469500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306469500
7306469500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306470000
7306470000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306470000
7306470000: Cache: system.l2: recvTimingResp: Handling response ReadExResp [8ef8d000:8ef8d03f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9824000
7306470000: Cache: system.l2: Block for addr 0x8ef8d000 being updated in Cache
7306470000: CacheRepl: system.l2: Replacement victim: state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x23a2 set: 0x340 way: 0x1
7306470000: Cache: system.l2: Create Writeback WritebackDirty [8e88d000:8e88d03f] D= ptr=0x558fd070f800 writable: 1, dirty: 1
7306470000: Cache: system.l2: Block addr 0x8ef8d000 (ns) moving from state 0 (I) to state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x23be set: 0x340 way: 0x1
7306470000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306480000
7306470000: CoherentXBar: system.tol2bus: recvTimingSnoopReq: src system.tol2bus.master[0] packet WritebackDirty [8e88d000:8e88d03f] ES D= ptr=0x7ffdd53f7cd0
7306470000: SnoopFilter: system.tol2bus.snoop_filter: lookupSnoop: packet WritebackDirty [8e88d000:8e88d03f] ES D= ptr=0x7ffdd53f7cd0
7306470000: CoherentXBar: system.tol2bus: recvTimingSnoopReq: src system.tol2bus.master[0] packet WritebackDirty [8e88d000:8e88d03f] ES D= ptr=0x7ffdd53f7cd0 SF size: 0 lat: 0
7306470000: CoherentXBar: system.tol2bus: forwardTiming for WritebackDirty [8e88d000:8e88d03f] ES D= ptr=0x7ffdd53f7cd0
7306470000: CachePort: system.l2.mem_side: Scheduling send event at 7306480000
7306470000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadExResp [8ef8d000:8ef8d03f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9824000
7306470000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306470000
7306470000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306470500
7306470500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306470500
7306470500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306471000
7306471000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306471000
7306471000: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=0058d2d18f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363436303530300a00000000000000000000000000000000 ptr=0x558fd070f480
7306471000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=00ca82c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9824000
7306471000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=00ca82c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9824000
7306471000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=00ca82c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9824000 SF size: 0 lat: 1
7306471000: CoherentXBar: system.membus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=00ca82c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9824000
7306471000: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x80737180 size 64
7306471000: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306471000: DRAM: system.mem_ctrls: Address: 0x737180 Rank 1 Bank 3 Row 57
7306471000: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306471000: DRAM: system.mem_ctrls: Adding to read queue
7306471000: DRAM: system.mem_ctrls: Request scheduled immediately
7306471000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306471000
7306471000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306472000
7306471000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306471000 to 7306472000
7306471000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306480000
7306471000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306471000
7306471000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306471000: DRAM: system.mem_ctrls: Single request, going to a free rank
7306471000: DRAM: system.mem_ctrls: Timing access to addr 0x737180, rank/bank/row 1 3 57
7306471000: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306496000
7306471000: DRAM: system.mem_ctrls: Access to 0x737180, ready at 7306514750 next burst at 7306501000.
7306471000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306473500
7306471000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306471000
7306471000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306471500
7306471500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306471500
7306471500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306472000
7306472000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306472000
7306472000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306472000
7306472000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306472500
7306472500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306472500
7306472500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306473000
7306473000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306473000
7306473000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306473000
7306473000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306473500
7306473500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306473500
7306473500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306473500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306473500
7306473500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306474000
7306474000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306474000
7306474000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306474500
7306474500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306474500
7306474500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306475000
7306474750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306474750
7306474750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802300
7306474750: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802300
7306474750: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306477000
7306474750: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306480000
7306474750: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306474750 to 7306480000
7306474750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306479750
7306475000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306475000
7306475000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306475500
7306475500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306475500
7306475500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306476000
7306476000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306476000
7306476000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306476500
7306476500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306476500
7306476500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306477000
7306477000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306477000
7306477000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802300
7306477000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802300
7306477000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306477000
7306477000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306477500
7306477500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306477500
7306477500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306478000
7306478000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306478000
7306478000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306478500
7306478500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306478500
7306478500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306479000
7306479000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306479000
7306479000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306479500
7306479500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306479500
7306479500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306480000
7306479750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306479750
7306479750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600 BUSY
7306480000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306480000
7306480000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600
7306480000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600
7306480000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306482000
7306480000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306485000
7306480000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306480000 to 7306485000
7306480000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306484750
7306480000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306480000
7306480000: Cache: system.l2: sendWriteQueuePacket: write WritebackDirty [8e88d000:8e88d03f] D=000000000000000008d02800bfffffff08d02800bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f800
7306480000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WritebackDirty [8e88d000:8e88d03f] D=000000000000000008d02800bfffffff08d02800bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f800
7306480000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet WritebackDirty [8e88d000:8e88d03f] D=000000000000000008d02800bfffffff08d02800bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f800
7306480000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306480000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306480000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WritebackDirty [8e88d000:8e88d03f] D=000000000000000008d02800bfffffff08d02800bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f800 SF size: 0 lat: 1
7306480000: DRAM: system.mem_ctrls: recvTimingReq: request WritebackDirty addr 0x8e88d000 size 64
7306480000: DRAM: system.mem_ctrls: Write queue limit 64, current size 23, entries needed 1
7306480000: DRAM: system.mem_ctrls: Address: 0xe88d000 Rank 0 Bank 6 Row 1860
7306480000: DRAM: system.mem_ctrls: Adding to write queue
7306480000: DRAM: system.mem_ctrls: Responding to Address 0x8e88d000
7306480000: DRAM: system.mem_ctrls: Done: WritebackDirty [8e88d000:8e88d03f] D=000000000000000008d02800bfffffff08d02800bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f800
7306480000: DRAM: system.mem_ctrls: Request scheduled immediately
7306480000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306480000
7306480000: SnoopFilter: system.membus.snoop_filter: eraseIfNullEntry:   Removed SF entry.
7306480000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306485000
7306480000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306480000 to 7306485000
7306480000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306480000
7306480000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306480000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306480000
7306480000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadExResp [8ef8d000:8ef8d03f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f300
7306480000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[1] packet ReadExResp [8ef8d000:8ef8d03f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f300
7306480000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse:   old SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306480000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306480000: Event: system.tol2bus.slave[1]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1289 scheduled @ 7306480500
7306480000: Event: system.tol2bus.respLayer1.wrapped_function_event: EventFunctionWrapped 1290 scheduled @ 7306481500
7306480000: BaseXBar: system.tol2bus.respLayer1: The crossbar layer is now busy from tick 7306480000 to 7306481500
7306480000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306491000
7306480000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306480000
7306480000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306480500
7306480500: Event: system.tol2bus.slave[1]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1289 executed @ 7306480500
7306480500: Cache: system.cpu0.dcache: recvTimingResp: Handling response ReadExResp [8ef8d000:8ef8d03f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f300
7306480500: Cache: system.cpu0.dcache: Block for addr 0x8ef8d000 being updated in Cache
7306480500: CacheRepl: system.cpu0.dcache: Replacement victim: state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x140 way: 0x1
7306480500: Cache: system.cpu0.dcache: Create Writeback WritebackDirty [8d845000:8d84503f] D= ptr=0x558fc9802880 writable: 1, dirty: 1
7306480500: Cache: system.cpu0.dcache: Block addr 0x8ef8d000 (ns) moving from state 0 (I) to state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x11df1 set: 0x140 way: 0x1
7306480500: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8ef8d018:8ef8d01b] D=04000000 ptr=0x558fc9802180 (write)
7306480500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306481500
7306480500: CachePort: system.cpu0.dcache.mem_side: Scheduling send event at 7306481500
7306480500: Event: system.cpu0.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 55 scheduled @ 7306481500
7306480500: CacheVerbose: system.cpu0.dcache: recvTimingResp: Leaving with ReadExResp [8ef8d000:8ef8d03f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f300
7306480500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306480500
7306480500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306481000
7306481000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306481000
7306481000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306481500
7306481500: Event: system.cpu0.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 55 executed @ 7306481500
7306481500: Cache: system.cpu0.dcache: sendWriteQueuePacket: write WritebackDirty [8d845000:8d84503f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9802880
7306481500: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[1] packet WritebackDirty [8d845000:8d84503f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9802880
7306481500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[1] packet WritebackDirty [8d845000:8d84503f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9802880
7306481500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306481500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306481500: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[1] packet WritebackDirty [8d845000:8d84503f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9802880 SF size: 0 lat: 0
7306481500: Cache: system.l2: access for WritebackDirty [8d845000:8d84503f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9802880 miss
7306481500: CacheRepl: system.l2: Replacement victim: state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x23a0 set: 0x140 way: 0x4
7306481500: Cache: system.l2: Create Writeback WritebackDirty [8e805000:8e80503f] D= ptr=0x558fd070f300 writable: 1, dirty: 1
7306481500: Cache: system.l2: access new state is state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x2361 set: 0x140 way: 0x4
7306481500: CoherentXBar: system.tol2bus: recvTimingSnoopReq: src system.tol2bus.master[0] packet WritebackDirty [8e805000:8e80503f] ES D= ptr=0x7ffdd53f73a0
7306481500: SnoopFilter: system.tol2bus.snoop_filter: lookupSnoop: packet WritebackDirty [8e805000:8e80503f] ES D= ptr=0x7ffdd53f73a0
7306481500: CoherentXBar: system.tol2bus: recvTimingSnoopReq: src system.tol2bus.master[0] packet WritebackDirty [8e805000:8e80503f] ES D= ptr=0x7ffdd53f73a0 SF size: 0 lat: 0
7306481500: CoherentXBar: system.tol2bus: forwardTiming for WritebackDirty [8e805000:8e80503f] ES D= ptr=0x7ffdd53f73a0
7306481500: CachePort: system.l2.mem_side: Scheduling send event at 7306502000
7306481500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306502000
7306481500: Cache: system.l2: handleTimingReqHit satisfied WritebackDirty [8d845000:8d84503f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9802880, no response needed
7306481500: SnoopFilter: system.tol2bus.snoop_filter: eraseIfNullEntry:   Removed SF entry.
7306481500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306483000
7306481500: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306481500 to 7306483000
7306481500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306481500
7306481500: Event: system.tol2bus.respLayer1.wrapped_function_event: EventFunctionWrapped 1290 executed @ 7306481500
7306481500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306481500
7306481500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306482000
7306482000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306482000
7306482000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600
7306482000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600
7306482000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306482000
7306482000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306482500
7306482500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306482500
7306482500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306483000
7306483000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306483000
7306483000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306483000
7306483000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306483500
7306483500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306483500
7306483500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306484000
7306484000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306484000
7306484000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306484500
7306484500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306484500
7306484500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306485000
7306484750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306484750
7306484750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802900 BUSY
7306485000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306485000
7306485000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306485000
7306485000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802900
7306485000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802900
7306485000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306487000
7306485000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306490000
7306485000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306485000 to 7306490000
7306485000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306492750
7306485000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306485000
7306485000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306485500
7306485500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306485500
7306485500: Cache: system.cpu0.dcache: access for WriteReq [8d847dc0:8d847dc7] D=0400000000000000 ptr=0x558fd070f600 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306485500: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847dc0:8d847dc7] D=0400000000000000 ptr=0x558fd070f600 (write)
7306485500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306486500
7306485500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306486000
7306486000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306486000
7306486000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306486500
7306486500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306486500
7306486500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306486500
7306486500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306487000
7306487000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306487000
7306487000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802900
7306487000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802900
7306487000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306487000
7306487000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306487500
7306487500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306487500
7306487500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306488000
7306488000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306488000
7306488000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306488500
7306488500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306488500
7306488500: Cache: system.cpu0.dcache: access for ReadReq [8d860010:8d860013] D=802c6acf ptr=0x558fc9802900 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b0c set: 0 way: 0
7306488500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306489500
7306488500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306489000
7306489000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306489000
7306489000: Cache: system.cpu0.icache: access for ReadReq [80712540:8071257f] IF D=4010d1d18f5500000027d4d18f550000be40ca0000000000409d7dd08f550000000000000000000080b5eac88f55000020beeac88f5500000000000000000000 ptr=0x558fd070f600 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x201c4 set: 0x95 way: 0
7306489000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306490000
7306489000: Cache: system.cpu0.dcache: access for ReadReq [8ef31018:8ef3101b] D=48316acf ptr=0x558fc9802180 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11de6 set: 0x40 way: 0x1
7306489000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306489500
7306489500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306489500
7306489500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306490000
7306489500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306489500
7306489500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306490000
7306490000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306490000
7306490000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306490000
7306490000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306490000
7306490000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306490000
7306490000: Cache: system.cpu0.icache: access for ReadReq [80712580:807125bf] IF D=8055d2d18f550000205b38656638643031383a38656638643031625d20443d3034303030303030207074723d3078353538666339383032313830000000000000 ptr=0x558fd070f600 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x201c4 set: 0x96 way: 0
7306490000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306491000
7306490000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306490500
7306490500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306490500
7306490500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306491000
7306491000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306491000
7306491000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306491000
7306491000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f880
7306491000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[8] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f880
7306491000: Event: system.tol2bus.slave[8]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1303 scheduled @ 7306491500
7306491000: Event: system.tol2bus.respLayer8.wrapped_function_event: EventFunctionWrapped 1304 scheduled @ 7306492500
7306491000: BaseXBar: system.tol2bus.respLayer8: The crossbar layer is now busy from tick 7306491000 to 7306492500
7306491000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306496000
7306491000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306491000
7306491000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306491500
7306491500: Event: system.tol2bus.slave[8]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1303 executed @ 7306491500
7306491500: Cache: system.cpu2.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f880
7306491500: Event: system.cpu2.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 156 scheduled @ 7306493500
7306491500: CacheVerbose: system.cpu2.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f880
7306491500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306491500
7306491500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306492000
7306492000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306492000
7306492000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306492500
7306492500: Event: system.tol2bus.respLayer8.wrapped_function_event: EventFunctionWrapped 1304 executed @ 7306492500
7306492500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306492500
7306492500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306493000
7306492750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306492750
7306492750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b00
7306492750: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b00
7306492750: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306495000
7306492750: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306498000
7306492750: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306492750 to 7306498000
7306493000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306493000
7306493000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306493500
7306493500: Event: system.cpu2.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 156 executed @ 7306493500
7306493500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306493500
7306493500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306493500
7306493500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306494000
7306493500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306493500
7306493500: Cache: system.cpu0.icache: access for ReadReq [80994000:8099403f] IF D=400ad1d18f550000fd7bbda902008012fd030091f35301a9e0d01dd28f550000e07974d08f550000f50300aa1f2003d542040011012080d2e00315aa427c4093 ptr=0x558fc8fb7d00 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20265 set: 0 way: 0x1
7306493500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306494500
7306493500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306494000
7306494000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306494000
7306494000: Cache: system.cpu0.dcache: access for ReadReq [8d8602e0:8d8602e7] D=682d6acf8f550000 ptr=0x558fc9802180 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b0c set: 0xb way: 0
7306494000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306495000
7306494000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306494500
7306494000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306494000
7306494000: Cache: system.cpu2.icache: access for ReadReq [807371c0:807371ff] IF UC D=401b80c98f5500008014d1d18f5500001b41ca0000000000806d74d08f55000040cbd1d18f55000090b4eac88f55000090b7eac88f5500000000000000000000 ptr=0x558fd070f880
7306494000: CachePort: system.cpu2.icache.mem_side: Scheduling send event at 7306495000
7306494000: Event: system.cpu2.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 158 scheduled @ 7306495000
7306494000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306494500
7306494500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306494500
7306494500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306494500
7306494500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306495000
7306494500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306494500
7306494500: Cache: system.cpu0.icache: access for ReadReq [80993f80:80993fbf] IF D=00b2acd38f55000080b2acd38f5500001d41ca00000000002061d4d18f5500002093d0d18f55000028b0eac88f55000090b4eac88f550000001c0012fd7bc1a8 ptr=0x558fc8fb7d00 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20264 set: 0xfe way: 0
7306494500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306495500
7306494500: Cache: system.cpu0.dcache: access for ReadReq [807507f0:807507f7] D=78306acf8f550000 ptr=0x558fc9802900 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x100ea set: 0x1f way: 0x1
7306494500: Cache: system.cpu0.dcache: access for ReadReq [8d8602e8:8d8602ef] D=382e6acf8f550000 ptr=0x558fd070f600 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b0c set: 0xb way: 0
7306494500: Cache: system.cpu0.dcache: access for ReadReq [8d8602f0:8d8602f7] D=002f6acf8f550000 ptr=0x558fd070fd00 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b0c set: 0xb way: 0
7306494500: Cache: system.cpu0.dcache: access for ReadReq [8d8602f8:8d8602ff] D=30326acf8f550000 ptr=0x558fd070fe00 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b0c set: 0xb way: 0
7306494500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306495000
7306495000: Event: system.cpu2.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 158 executed @ 7306495000
7306495000: Cache: system.cpu2.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=401b80c98f5500008014d1d18f5500001b41ca0000000000806d74d08f55000040cbd1d18f55000090b4eac88f55000090b7eac88f5500000000000000000000 ptr=0x558fd070f880
7306495000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[8] packet ReadReq [807371c0:807371ff] IF UC D=c094d6d18f550000c01cd1d18f5500006d41ca0000000000000000000200ffff00000000f6ffff9798aceac88f550000b0afeac88f5500000000018ac31900d0 ptr=0x558fc9802d00
7306495000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[8] packet ReadReq [807371c0:807371ff] IF UC D=c094d6d18f550000c01cd1d18f5500006d41ca0000000000000000000200ffff00000000f6ffff9798aceac88f550000b0afeac88f5500000000018ac31900d0 ptr=0x558fc9802d00
7306495000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[8] packet ReadReq [807371c0:807371ff] IF UC D=c094d6d18f550000c01cd1d18f5500006d41ca0000000000000000000200ffff00000000f6ffff9798aceac88f550000b0afeac88f5500000000018ac31900d0 ptr=0x558fc9802d00 SF size: 0 lat: 0
7306495000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=c094d6d18f550000c01cd1d18f5500006d41ca0000000000000000000200ffff00000000f6ffff9798aceac88f550000b0afeac88f5500000000018ac31900d0 ptr=0x558fc9802d00
7306495000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=c094d6d18f550000c01cd1d18f5500006d41ca0000000000000000000200ffff00000000f6ffff9798aceac88f550000b0afeac88f5500000000018ac31900d0 ptr=0x558fc9802d00
7306495000: CachePort: system.l2.mem_side: Scheduling send event at 7306505500
7306495000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306495500
7306495000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306495000 to 7306495500
7306495000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306495000
7306495000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306495500
7306495000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306495000
7306495000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b00
7306495000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b00
7306495000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306495000
7306495000: Cache: system.cpu0.dcache: access for ReadReq [807507f8:807507ff] D=802d6acf8f550000 ptr=0x558fc9802b00 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x100ea set: 0x1f way: 0x1
7306495000: Cache: system.cpu0.dcache: access for ReadReq [80750800:80750807] D=102d6acf8f550000 ptr=0x558fd070fc80 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x100ea set: 0x20 way: 0x1
7306495000: Cache: system.cpu0.dcache: access for ReadReq [80750808:8075080f] D=782f6acf8f550000 ptr=0x558fc9824180 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x100ea set: 0x20 way: 0x1
7306495000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306495500
7306495000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306495000
7306495000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306495500
7306495500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306495500
7306495500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306495501
7306495500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306495500
7306495500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306495500
7306495500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306495500
7306495500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306496000
7306495500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306495500
7306495500: Cache: system.cpu0.icache: access for ReadReq [80714980:807149bf] IF D=80a6aed38f5500006374696f6e577261707065642031323835206578656375746564204020373330363439353530300a00b3eac88f55000010d8e9cd8f550000 ptr=0x558fc8fb7d00 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x201c5 set: 0x26 way: 0x1
7306495500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306496500
7306495500: Cache: system.cpu0.dcache: access for ReadReq [8d847dc0:8d847dc7] D=e02f6acf8f550000 ptr=0x558fc9802300 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306495500: Cache: system.cpu0.dcache: access for ReadReq [8d847db0:8d847dbf] D=d0f667d08f550000d0fa67d08f550000 ptr=0x558fd070f500 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f6 way: 0
7306495500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306496000
7306495501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306495501
7306495501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306495502
7306495502: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306495502
7306495502: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306495503
7306495503: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306495503
7306495503: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306496000
7306496000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306496000
7306496000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306496001
7306496000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306496000
7306496000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802700
7306496000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[12] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802700
7306496000: Event: system.tol2bus.slave[12]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1311 scheduled @ 7306496500
7306496000: Event: system.tol2bus.respLayer12.wrapped_function_event: EventFunctionWrapped 1312 scheduled @ 7306497500
7306496000: BaseXBar: system.tol2bus.respLayer12: The crossbar layer is now busy from tick 7306496000 to 7306497500
7306496000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306501000
7306496000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306496000
7306496000: Cache: system.cpu0.dcache: access for ReadReq [8d847df0:8d847dff] D=80fc67d08f550000b04d3ccd8f550000 ptr=0x558fc9802500 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306496000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306496500
7306496000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306496000
7306496000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306496500
7306496001: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306496001
7306496001: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306496002
7306496002: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306496002
7306496002: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306496500
7306496500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306496500
7306496500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306496501
7306496500: Event: system.tol2bus.slave[12]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1311 executed @ 7306496500
7306496500: Cache: system.cpu3.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802700
7306496500: Event: system.cpu3.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 201 scheduled @ 7306498500
7306496500: CacheVerbose: system.cpu3.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802700
7306496500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306496500
7306496500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306496500
7306496500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306497000
7306496500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306496500
7306496500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306497000
7306496501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306496501
7306496501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306497000
7306497000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306497000
7306497000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306497000
7306497000: Cache: system.cpu0.icache: access for ReadReq [803378c0:803378ff] IF D=0059d2d18f5500004021d4d18f5500007741ca0000000000000000000300ffff0000000020373330e0aceac88f55000080a9eac88f550000e0039fd6c11900b0 ptr=0x558fc9802180 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x200cd set: 0xe3 way: 0
7306497000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306498000
7306497000: Cache: system.cpu0.dcache: access for ReadReq [80934310:80934317] D=402f6acf8f550000 ptr=0x558fc8fb7d00 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x10126 set: 0x10c way: 0
7306497000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306498000
7306497000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306497500
7306497000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306497000
7306497000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306497500
7306497500: Event: system.tol2bus.respLayer12.wrapped_function_event: EventFunctionWrapped 1312 executed @ 7306497500
7306497500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306497500
7306493500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306493500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306493500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306497500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306498000
7306497500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306497500
7306497500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306498000
7306498000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306498000
7306498000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306498000
7306498000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306498000
7306498000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306498000
7306498000: Cache: system.cpu0.icache: access for ReadReq [80337900:8033793f] IF D=4006d1d18f550000c0df82c98f5500005141ca0000000000204a03d28f550000000000008f5500002834b2c98f55000080fab1c98f55000010d8e9cd8f550000 ptr=0x558fc9802180 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x200cd set: 0xe4 way: 0
7306498000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306499000
7306498000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306498500
7306498000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306498000
7306498000: Cache: system.cpu2.icache: access for ReadReq [80737180:807371bf] IF UC D=808dd6d18f5500009f0000ebc00000545f2003d5fcffff17e07074d08f550000a085d3d18f550000100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802b00
7306498000: CachePort: system.cpu2.icache.mem_side: Scheduling send event at 7306499000
7306498000: Event: system.cpu2.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 158 scheduled @ 7306499000
7306498000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306498500
7306498500: Event: system.cpu3.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 201 executed @ 7306498500
7306498500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306498500
7306498500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306498500
7306498500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306499000
7306498500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306498500
7306498500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306499000
7306498500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306498500
7306498500: Cache: system.cpu0.dcache: access for ReadReq [80743f88:80743f8f] D=48316acf8f550000 ptr=0x558fc8fb7c80 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x100e8 set: 0xfe way: 0
7306498500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306499500
7306498500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306499000
7306499000: Event: system.cpu2.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 158 executed @ 7306499000
7306499000: Cache: system.cpu2.icache: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=808dd6d18f5500009f0000ebc00000545f2003d5fcffff17e07074d08f550000a085d3d18f550000100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802b00
7306499000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[8] packet ReadReq [80737180:807371bf] IF UC D=40dd82c98f5500000018d1d18f5500001241ca000000000020aabfc98f550000000000008f55000030abeac88f55000030abeac88f5500000000000000000000 ptr=0x558fd070f600
7306499000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[8] packet ReadReq [80737180:807371bf] IF UC D=40dd82c98f5500000018d1d18f5500001241ca000000000020aabfc98f550000000000008f55000030abeac88f55000030abeac88f5500000000000000000000 ptr=0x558fd070f600
7306499000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[8] packet ReadReq [80737180:807371bf] IF UC D=40dd82c98f5500000018d1d18f5500001241ca000000000020aabfc98f550000000000008f55000030abeac88f55000030abeac88f5500000000000000000000 ptr=0x558fd070f600 SF size: 0 lat: 0
7306499000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=40dd82c98f5500000018d1d18f5500001241ca000000000020aabfc98f550000000000008f55000030abeac88f55000030abeac88f5500000000000000000000 ptr=0x558fd070f600
7306499000: Cache: system.l2: access for ReadReq [80737180:807371bf] IF UC D=40dd82c98f5500000018d1d18f5500001241ca000000000020aabfc98f550000000000008f55000030abeac88f55000030abeac88f5500000000000000000000 ptr=0x558fd070f600
7306499000: CachePort: system.l2.mem_side: Scheduling send event at 7306509500
7306499000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306499500
7306499000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306499000 to 7306499500
7306499000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306499000
7306499000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306499000
7306499000: Cache: system.cpu0.icache: access for ReadReq [80993f80:80993fbf] IF D=80abaed38f55000043fc46d3037863f8c30000b5420001913f0002eb68ffff54e00301aac0035fd66300c0da6310c0da6200028b3f0002eb2190829ae00301aa ptr=0x558fc9802180 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20264 set: 0xfe way: 0
7306499000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306500000
7306499000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306499500
7306499000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306499000
7306499000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306499500
7306499000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306499000
7306499000: Cache: system.cpu3.icache: access for ReadReq [807371c0:807371ff] IF UC D=801b80c98f5500000000000000000000000000000000000000f202d28f5500000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9802900
7306499000: CachePort: system.cpu3.icache.mem_side: Scheduling send event at 7306500000
7306499000: Event: system.cpu3.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 203 scheduled @ 7306500000
7306499000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306499500
7306499500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306499500
7306499500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306499500
7306499500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306499500
7306499500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306500000
7306499500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306499500
7306499500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306500000
7306499500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306499500
7306499500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306500000
7306499750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306499750
7306499750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306499750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 3
7306499750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306499750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306527750
7306499750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f280
7306499750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306504750
7306500000: Event: system.cpu3.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 203 executed @ 7306500000
7306500000: Cache: system.cpu3.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=801b80c98f5500000000000000000000000000000000000000f202d28f5500000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9802900
7306500000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[12] packet ReadReq [807371c0:807371ff] IF UC D=0053d2d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00cd8f550000 ptr=0x558fc9824180
7306500000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[12] packet ReadReq [807371c0:807371ff] IF UC D=0053d2d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00cd8f550000 ptr=0x558fc9824180
7306500000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[12] packet ReadReq [807371c0:807371ff] IF UC D=0053d2d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00cd8f550000 ptr=0x558fc9824180 SF size: 0 lat: 0
7306500000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=0053d2d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00cd8f550000 ptr=0x558fc9824180
7306500000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=0053d2d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00cd8f550000 ptr=0x558fc9824180
7306500000: CachePort: system.l2.mem_side: Scheduling send event at 7306510500
7306500000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306500500
7306500000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306500000 to 7306500500
7306500000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306500000
7306500000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306500000
7306500000: Cache: system.cpu0.icache: access for ReadReq [80714980:807149bf] IF D=c0b6acd38f550000c090d6d18f5500001e41ca000000000060acbfc98f55000000e0d4d18f550000f8b2eac88f55000078baeac88f5500000101010101010101 ptr=0x558fc9802180 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x201c5 set: 0x26 way: 0x1
7306500000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306501000
7306488500: ExecEnable: system.cpu0: A0 T0 : @smp_prepare_cpus+144    :   orr   w0, wzr, w19       : IntAlu :  D=0x0000000000000004  FetchSeq=13255061  CPSeq=11776595  flags=(IsInteger)
7306500000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306500500
7306500000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306500000
7306500000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306500500
7306500000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306500000
7306500000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306500500
7306500500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306500500
7306500500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306500500
7306500500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306501000
7306500500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306500500
7306500500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306501000
7306500500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306500500
7306500500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306501000
7306501000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306501000
7306501000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306501000
7306501000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fd80
7306501000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[16] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fd80
7306501000: Event: system.tol2bus.slave[16]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1319 scheduled @ 7306501500
7306501000: Event: system.tol2bus.respLayer16.wrapped_function_event: EventFunctionWrapped 1320 scheduled @ 7306502500
7306501000: BaseXBar: system.tol2bus.respLayer16: The crossbar layer is now busy from tick 7306501000 to 7306502500
7306501000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306509000
7306501000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306501000
7306501000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306501500
7306501000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306501000
7306501000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306501500
7306501000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306501000
7306501000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306501500
7306501500: Event: system.tol2bus.slave[16]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1319 executed @ 7306501500
7306501500: Cache: system.cpu4.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fd80
7306501500: Event: system.cpu4.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 246 scheduled @ 7306503500
7306501500: CacheVerbose: system.cpu4.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fd80
7306501500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306501500
7306501500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306502000
7306501500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306501500
7306501500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306502000
7306501500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306501500
7306501500: Cache: system.cpu0.icache: access for ReadReq [800932c0:800932ff] IF D=8019d1d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363530323030300a001fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fd80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20024 set: 0xcb way: 0x1
7306501500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306502500
7306488500: ExecEnable: system.cpu0: A0 T0 : @smp_prepare_cpus+148    :   cbz   x1, <smp_prepare_cpus+72> : IntAlu :   FetchSeq=13255062  CPSeq=11776596  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7306488500: ExecEnable: system.cpu0: A0 T0 : @smp_prepare_cpus+152    :   ldr   x1, [x1, #16]      : MemRead :  D=0xffffff80080932c0 A=0xffffff8008743f88  FetchSeq=13255063  CPSeq=11776597  flags=(IsInteger|IsMemRef|IsLoad)
7306488500: ExecEnable: system.cpu0: A0 T0 : @smp_prepare_cpus+156    :   blr   x1                 : IntAlu :  D=0xffffff8008993fec  FetchSeq=13255064  CPSeq=11776598  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsCall)
7306501500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306502000
7306502000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306502000
7306502000: Cache: system.l2: sendWriteQueuePacket: write WritebackDirty [8e805000:8e80503f] D=000000000000000008502000bfffffff08502000bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f300
7306502000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WritebackDirty [8e805000:8e80503f] D=000000000000000008502000bfffffff08502000bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f300
7306502000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet WritebackDirty [8e805000:8e80503f] D=000000000000000008502000bfffffff08502000bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f300
7306502000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306502000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306502000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WritebackDirty [8e805000:8e80503f] D=000000000000000008502000bfffffff08502000bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f300 SF size: 0 lat: 1
7306502000: DRAM: system.mem_ctrls: recvTimingReq: request WritebackDirty addr 0x8e805000 size 64
7306502000: DRAM: system.mem_ctrls: Write queue limit 64, current size 24, entries needed 1
7306502000: DRAM: system.mem_ctrls: Address: 0xe805000 Rank 0 Bank 2 Row 1856
7306502000: DRAM: system.mem_ctrls: Adding to write queue
7306502000: DRAM: system.mem_ctrls: Responding to Address 0x8e805000
7306502000: DRAM: system.mem_ctrls: Done: WritebackDirty [8e805000:8e80503f] D=000000000000000008502000bfffffff08502000bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f300
7306502000: DRAM: system.mem_ctrls: Request scheduled immediately
7306502000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306502000
7306502000: SnoopFilter: system.membus.snoop_filter: eraseIfNullEntry:   Removed SF entry.
7306502000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306507000
7306502000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306502000 to 7306507000
7306502000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306505500
7306502000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306502000
7306502000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306502000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306502000
7306502000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306502500
7306502000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306502000
7306502000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306502500
7306502000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306502000
7306502000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306502500
7306502500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306502500
7306502500: Event: system.tol2bus.respLayer16.wrapped_function_event: EventFunctionWrapped 1320 executed @ 7306502500
7306502500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306502500
7306498500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306498500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306498500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306502500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306503000
7306502500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306502500
7306502500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306503000
7306502500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306502500
7306502500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306503000
7306503000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306503000
7306503000: Cache: system.cpu0.icache: access for ReadReq [8009b800:8009b83f] IF D=404bd2d18f550000602febc88f5500009841ca0000000000000000002100ffff0000000000000000a0b3eac88f55000078b4eac88f5500000000000000000000 ptr=0x558fd070fd80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20026 set: 0xe0 way: 0
7306503000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306504000
7306503000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306503500
7306503000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306503000
7306503000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306503500
7306503000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306503000
7306503000: Cache: system.cpu3.icache: access for ReadReq [80737180:807371bf] IF UC D=0098d6d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363530333530300a000314aa3f00176b69020054417877f8 ptr=0x558fc8fb7c80
7306503000: CachePort: system.cpu3.icache.mem_side: Scheduling send event at 7306504000
7306503000: Event: system.cpu3.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 203 scheduled @ 7306504000
7306503000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306503500
7306503500: Event: system.cpu4.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 246 executed @ 7306503500
7306503500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306503500
7306503500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306503500
7306503500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306504000
7306503500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306503500
7306503500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306504000
7306503500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306503500
7306503500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306503500
7306503500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306504000
7306504000: Event: system.cpu3.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 203 executed @ 7306504000
7306504000: Cache: system.cpu3.icache: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=0098d6d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363530333530300a000314aa3f00176b69020054417877f8 ptr=0x558fc8fb7c80
7306504000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[12] packet ReadReq [80737180:807371bf] IF UC D=0033d4d18f5500006374696f6e5772617070656420343632203c03d28f5500006564204020373330363438303030300a002035370a0000000000000000000000 ptr=0x558fc8fb7f80
7306504000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[12] packet ReadReq [80737180:807371bf] IF UC D=0033d4d18f5500006374696f6e5772617070656420343632203c03d28f5500006564204020373330363438303030300a002035370a0000000000000000000000 ptr=0x558fc8fb7f80
7306504000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[12] packet ReadReq [80737180:807371bf] IF UC D=0033d4d18f5500006374696f6e5772617070656420343632203c03d28f5500006564204020373330363438303030300a002035370a0000000000000000000000 ptr=0x558fc8fb7f80 SF size: 0 lat: 0
7306504000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=0033d4d18f5500006374696f6e5772617070656420343632203c03d28f5500006564204020373330363438303030300a002035370a0000000000000000000000 ptr=0x558fc8fb7f80
7306504000: Cache: system.l2: access for ReadReq [80737180:807371bf] IF UC D=0033d4d18f5500006374696f6e5772617070656420343632203c03d28f5500006564204020373330363438303030300a002035370a0000000000000000000000 ptr=0x558fc8fb7f80
7306504000: CachePort: system.l2.mem_side: Scheduling send event at 7306514500
7306504000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306504500
7306504000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306504000 to 7306504500
7306504000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306504000
7306504000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306504000
7306504000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306504500
7306504000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306504000
7306504000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306504500
7306504000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306504000
7306504000: Cache: system.cpu4.icache: access for ReadReq [807371c0:807371ff] IF UC D=c08fd6d18f5500006374696f6e5772617070656420323436207363686564756c6564204020373330363530333530300a0000b1c98f5500000000000000000000 ptr=0x558fd070fd80
7306504000: CachePort: system.cpu4.icache.mem_side: Scheduling send event at 7306505000
7306504000: Event: system.cpu4.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 248 scheduled @ 7306505000
7306504000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306504500
7306504500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306504500
7306504500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306504500
7306504500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306505000
7306504500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306504500
7306504500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306505000
7306504500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306504500
7306504500: Cache: system.cpu0.icache: access for ReadReq [8009b1c0:8009b1ff] IF D=001f80c98f550000401780c98f5500009041ca0000000000050000000200ffff000000008f5500009035b2c98f55000018f0b1c98f55000090bbb9cd8f550000 ptr=0x558fd070f800 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20026 set: 0xc7 way: 0
7306504500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306505500
7306504500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306505000
7306504750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306504750
7306504750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306504750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 2
7306504750: DRAM: system.mem_ctrls: Responding to Address 0x807371c0
7306504750: DRAM: system.mem_ctrls: Done: ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f580
7306504750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306509750
7306505000: Event: system.cpu4.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 248 executed @ 7306505000
7306505000: Cache: system.cpu4.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c08fd6d18f5500006374696f6e5772617070656420323436207363686564756c6564204020373330363530333530300a0000b1c98f5500000000000000000000 ptr=0x558fd070fd80
7306505000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[16] packet ReadReq [807371c0:807371ff] IF UC D=800ed1d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00d18f550000 ptr=0x558fc9802180
7306505000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[16] packet ReadReq [807371c0:807371ff] IF UC D=800ed1d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00d18f550000 ptr=0x558fc9802180
7306505000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[16] packet ReadReq [807371c0:807371ff] IF UC D=800ed1d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00d18f550000 ptr=0x558fc9802180 SF size: 0 lat: 0
7306505000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=800ed1d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00d18f550000 ptr=0x558fc9802180
7306505000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=800ed1d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00d18f550000 ptr=0x558fc9802180
7306505000: CachePort: system.l2.mem_side: Scheduling send event at 7306515500
7306505000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306505500
7306505000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306505000 to 7306505500
7306505000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306505000
7306505000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306505500
7306505000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306505000
7306505000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306505500
7306505000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306505000
7306505000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306505500
7306505500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306505500
7306505500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306505500
7306505500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306505500
7306505500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c094d6d18f550000c01cd1d18f5500006d41ca0000000000000000000200ffff00000000f6ffff9798aceac88f550000b0afeac88f5500000000018ac31900d0 ptr=0x558fc9802d00
7306505500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=001780c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070f800 BUSY
7306505500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306505500
7306505500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306506000
7306505500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306505500
7306505500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306506000
7306505500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306505500
7306505500: Cache: system.cpu0.icache: access for ReadReq [801ae300:801ae33f] IF D=c020d4d18f5500004045d2d18f5500008d41ca0000000000000000002000ffff000000008f55000048b4eac88f550000f8b8eac88f5500000000000000000000 ptr=0x558fd070f800 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x2006b set: 0x8c way: 0
7306505500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306506500
7306505500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306506000
7306506000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306506000
7306506000: Cache: system.cpu0.dcache: access for ReadReq [80a75798:80a7579f] D=f82f6acf8f550000 ptr=0x558fc8fb7d00 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x1014e set: 0x15e way: 0
7306506000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306507000
7306502500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare    :   adrp   x1, #10362880     : IntAlu :  D=0xffffff8008a75000  FetchSeq=13255106  CPSeq=11776599  flags=(IsInteger)
7306506000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306506500
7306506000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306506000
7306506000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306506500
7306506000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306506000
7306506000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306506500
7306506500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306506500
7306506500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306506500
7306506500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306507000
7306506500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306506500
7306506500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306507000
7306506500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306506500
7306506500: Cache: system.cpu0.icache: access for ReadReq [801ae340:801ae37f] IF D=400ad1d18f550000409bd6d18f5500008541ca0000000000050000000200ffff000000008f55000018f0b1c98f55000080d6b1c98f550000c0035fd61f2003d5 ptr=0x558fd070f800 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x2006b set: 0x8d way: 0x1
7306506500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306507500
7306502500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+4    :   add   x1, x1, #1912      : IntAlu :  D=0xffffff8008a75778  FetchSeq=13255107  CPSeq=11776600  flags=(IsInteger)
7306506500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306507000
7306507000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306507000
7306507000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306507000
7306507000: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c094d6d18f550000c01cd1d18f5500006d41ca0000000000000000000200ffff00000000f6ffff9798aceac88f550000b0afeac88f5500000000018ac31900d0 ptr=0x558fc9802d00
7306507000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=0021d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802500
7306507000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=0021d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802500
7306507000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=0021d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802500 SF size: 0 lat: 1
7306507000: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=0021d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802500
7306507000: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306507000: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306507000: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306507000: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306507000: DRAM: system.mem_ctrls: Adding to read queue
7306507000: DRAM: system.mem_ctrls: Request scheduled immediately
7306507000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306507000
7306507000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306508000
7306507000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306507000 to 7306508000
7306507000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306509500
7306507000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306507000
7306507000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306507000: DRAM: system.mem_ctrls: Single request, going to a free rank
7306507000: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306507000: DRAM: system.mem_ctrls: Removing burstTick for 7306495000
7306507000: DRAM: system.mem_ctrls: Removing burstTick for 7306490000
7306507000: DRAM: system.mem_ctrls: Removing burstTick for 7306485000
7306507000: DRAM: system.mem_ctrls: Removing burstTick for 7306480000
7306507000: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306507000
7306507000: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306525750 next burst at 7306512000.
7306507000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306507000
7306507000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306507000
7306507000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306507000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306507000
7306507000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306507500
7306507000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306507000
7306507000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306507500
7306507000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306507000
7306507000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306507500
7306507500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306507500
7306507500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306507500
7306503500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306503500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306503500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306507500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306508000
7306507500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306507500
7306507500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306508000
7306507500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306507500
7306507500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306508000
7306508000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306508000
7306508000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306508000
7306508000: Cache: system.cpu0.icache: access for ReadReq [801ae380:801ae3bf] IF D=00a6aed38f550000636365737320746f20616464722030783733373163302c2072616e6b2f62616e6b2f726f77203120332035370a0000000000000000000000 ptr=0x558fd070f800 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x2006b set: 0x8e way: 0x1
7306508000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306509000
7306502500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+8    :   ldr   x0, [x1, x0, UXTW #3] : MemRead :  D=0x000000008000fff8 A=0xffffff8008a75798  FetchSeq=13255108  CPSeq=11776601  flags=(IsInteger|IsMemRef|IsLoad)
7306508000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306508500
7306508000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306508000
7306508000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306508500
7306508000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306508000
7306508000: Cache: system.cpu4.icache: access for ReadReq [80737180:807371bf] IF UC D=00a6aed38f5500006374696f6e5772617070656420313834207363686564756c6564204020373330363530383530300a0098a3cc8f550000f35301a9452cf297 ptr=0x558fd070f500
7306508000: CachePort: system.cpu4.icache.mem_side: Scheduling send event at 7306509000
7306508000: Event: system.cpu4.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 248 scheduled @ 7306509000
7306508000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306508500
7306508500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306508500
7306508500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306509000
7306508500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306508500
7306508500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306508500
7306502500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+12    :   cbz   x0, <smp_spin_table_cpu_prepare+104> : IntAlu :   FetchSeq=13255109  CPSeq=11776602  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7306502500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+16    : stp
7306502500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+16. 0 :   addxi_uop   ureg0, sp, #-32 : IntAlu :  D=0xffffff8008043de0  FetchSeq=13255110  CPSeq=11776603  flags=(IsInteger|IsMicroop|IsDelayedCommit|IsFirstMicroop)
7306502500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+16. 1 :   strxi_uop   x29, [ureg0] : MemWrite :  D=0xffffff8008043e00 A=0xffffff8008043de0  FetchSeq=13255111  CPSeq=11776604  flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit)
7306502500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+16. 2 :   strxi_uop   x30, [ureg0, #8] : MemWrite :  D=0xffffff8008993fec A=0xffffff8008043de8  FetchSeq=13255112  CPSeq=11776605  flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit)
7306502500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+16. 3 :   addxi_uop   sp, ureg0, #0 : IntAlu :  D=0xffffff8008043de0  FetchSeq=13255113  CPSeq=11776606  flags=(IsInteger|IsMicroop|IsLastMicroop)
7306503000: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+20    :   movz   x1, #8, #0        : IntAlu :  D=0x0000000000000008  FetchSeq=13255114  CPSeq=11776607  flags=(IsInteger)
7306503000: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+24    :   add   x29, sp, #0        : IntAlu :  D=0xffffff8008043de0  FetchSeq=13255115  CPSeq=11776608  flags=(IsInteger)
7306503000: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+28    :   str   x19, [sp, #16]     : MemWrite :  D=0x0000000000000004 A=0xffffff8008043df0  FetchSeq=13255116  CPSeq=11776609  flags=(IsInteger|IsMemRef|IsStore)
7306508500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306509000
7306509000: Event: system.cpu4.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 248 executed @ 7306509000
7306509000: Cache: system.cpu4.icache: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=00a6aed38f5500006374696f6e5772617070656420313834207363686564756c6564204020373330363530383530300a0098a3cc8f550000f35301a9452cf297 ptr=0x558fd070f500
7306509000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[16] packet ReadReq [80737180:807371bf] IF UC D=c034d4d18f5500000091d6d18f550000c441ca0000000000000000000000ffff0000000020373330f0a8eac88f550000d0b3eac88f55000010d8e9cd8f550000 ptr=0x558fc8fb7d00
7306509000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[16] packet ReadReq [80737180:807371bf] IF UC D=c034d4d18f5500000091d6d18f550000c441ca0000000000000000000000ffff0000000020373330f0a8eac88f550000d0b3eac88f55000010d8e9cd8f550000 ptr=0x558fc8fb7d00
7306509000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[16] packet ReadReq [80737180:807371bf] IF UC D=c034d4d18f5500000091d6d18f550000c441ca0000000000000000000000ffff0000000020373330f0a8eac88f550000d0b3eac88f55000010d8e9cd8f550000 ptr=0x558fc8fb7d00 SF size: 0 lat: 0
7306509000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=c034d4d18f5500000091d6d18f550000c441ca0000000000000000000000ffff0000000020373330f0a8eac88f550000d0b3eac88f55000010d8e9cd8f550000 ptr=0x558fc8fb7d00
7306509000: Cache: system.l2: access for ReadReq [80737180:807371bf] IF UC D=c034d4d18f5500000091d6d18f550000c441ca0000000000000000000000ffff0000000020373330f0a8eac88f550000d0b3eac88f55000010d8e9cd8f550000 ptr=0x558fc8fb7d00
7306509000: CachePort: system.l2.mem_side: Scheduling send event at 7306519500
7306509000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306509500
7306509000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306509000 to 7306509500
7306509000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306509000
7306509000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306509000
7306509000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400
7306509000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[20] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400
7306509000: Event: system.tol2bus.slave[20]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1327 scheduled @ 7306509500
7306509000: Event: system.tol2bus.respLayer20.wrapped_function_event: EventFunctionWrapped 1328 scheduled @ 7306510500
7306509000: BaseXBar: system.tol2bus.respLayer20: The crossbar layer is now busy from tick 7306509000 to 7306510500
7306509000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306509000
7306509000: Cache: system.cpu0.icache: access for ReadReq [801ae340:801ae37f] IF D=0027d4d18f5500006374696f6e577261707065642031333238207363686564756c6564204020373330363531303530300a0004cd8f5500000000000000000000 ptr=0x558fd070f800 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x2006b set: 0x8d way: 0x1
7306509000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306510000
7306503000: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+32    :   bl   <ioremap_cache>     : IntAlu :  D=0xffffff80080932e4  FetchSeq=13255117  CPSeq=11776610  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache    : stp
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache. 0 :   addxi_uop   ureg0, sp, #-48 : IntAlu :  D=0xffffff8008043db0  FetchSeq=13255118  CPSeq=11776611  flags=(IsInteger|IsMicroop|IsDelayedCommit|IsFirstMicroop)
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache. 1 :   strxi_uop   x29, [ureg0] : MemWrite :  D=0xffffff8008043de0 A=0xffffff8008043db0  FetchSeq=13255119  CPSeq=11776612  flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit)
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache. 2 :   strxi_uop   x30, [ureg0, #8] : MemWrite :  D=0xffffff80080932e4 A=0xffffff8008043db8  FetchSeq=13255120  CPSeq=11776613  flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit)
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache. 3 :   addxi_uop   sp, ureg0, #0 : IntAlu :  D=0xffffff8008043db0  FetchSeq=13255121  CPSeq=11776614  flags=(IsInteger|IsMicroop|IsLastMicroop)
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+4    :   add   x29, sp, #0        : IntAlu :  D=0xffffff8008043db0  FetchSeq=13255122  CPSeq=11776615  flags=(IsInteger)
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+8    : stp
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+8. 0 :   addxi_uop   ureg0, sp, #16 : IntAlu :  D=0xffffff8008043dc0  FetchSeq=13255123  CPSeq=11776616  flags=(IsInteger|IsMicroop|IsDelayedCommit|IsFirstMicroop)
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+8. 1 :   strxi_uop   x19, [ureg0] : MemWrite :  D=0x0000000000000004 A=0xffffff8008043dc0  FetchSeq=13255124  CPSeq=11776617  flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit)
7306509000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306509500
7306509000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306509000
7306509000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306509500
7306509500: Event: system.tol2bus.slave[20]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1327 executed @ 7306509500
7306509500: Cache: system.cpu5.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400
7306509500: Event: system.cpu5.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 291 scheduled @ 7306511500
7306509500: CacheVerbose: system.cpu5.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400
7306509500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306509500
7306509500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306509500
7306509500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=40dd82c98f5500000018d1d18f5500001241ca000000000020aabfc98f550000000000008f55000030abeac88f55000030abeac88f5500000000000000000000 ptr=0x558fd070f600
7306509500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c00f80c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802400
7306509500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c00f80c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802400
7306509500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c00f80c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802400 SF size: 0 lat: 1
7306509500: CoherentXBar: system.membus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=c00f80c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802400
7306509500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x80737180 size 64
7306509500: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306509500: DRAM: system.mem_ctrls: Address: 0x737180 Rank 1 Bank 3 Row 57
7306509500: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306509500: DRAM: system.mem_ctrls: Adding to read queue
7306509500: DRAM: system.mem_ctrls: Request scheduled immediately
7306509500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306509500
7306509500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306511000
7306509500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306509500 to 7306511000
7306509500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306510500
7306509500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306509500
7306509500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306509500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306509500: DRAM: system.mem_ctrls: Timing access to addr 0x737180, rank/bank/row 1 3 57
7306509500: DRAM: system.mem_ctrls: Removing burstTick for 7306505000
7306509500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306512000
7306509500: DRAM: system.mem_ctrls: Access to 0x737180, ready at 7306530750 next burst at 7306517000.
7306509500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306509500
7306509500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306509500
7306509500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306509500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306509500
7306509500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306510000
7306509500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306509500
7306509500: Cache: system.cpu0.dcache: access for WriteReq [8d847de0:8d847de7] D=003e040880ffffff ptr=0x558fc9802300 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306509500: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847de0:8d847de7] D=003e040880ffffff ptr=0x558fc9802300 (write)
7306509500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306510500
7306509500: Cache: system.cpu0.dcache: access for WriteReq [8d847de8:8d847def] D=ec3f990880ffffff ptr=0x558fd070fe00 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306509500: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847de8:8d847def] D=ec3f990880ffffff ptr=0x558fd070fe00 (write)
7306509500: Cache: system.cpu0.dcache: access for WriteReq [8d847df0:8d847df7] D=0400000000000000 ptr=0x558fd070fc80 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306509500: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847df0:8d847df7] D=0400000000000000 ptr=0x558fd070fc80 (write)
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+8. 2 :   strxi_uop   x20, [ureg0, #8] : MemWrite :  D=0xffffff80089e9018 A=0xffffff8008043dc8  FetchSeq=13255125  CPSeq=11776618  flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsLastMicroop)
7306504500: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+12    :   orr   x19, xzr, x0       : IntAlu :  D=0x000000008000fff8  FetchSeq=13255126  CPSeq=11776619  flags=(IsInteger)
7306504500: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+16    :   str   x21, [sp, #32]     : MemWrite :  D=0xffffff8008a08724 A=0xffffff8008043dd0  FetchSeq=13255127  CPSeq=11776620  flags=(IsInteger|IsMemRef|IsStore)
7306504500: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+20    :   orr   x20, xzr, x1       : IntAlu :  D=0x0000000000000008  FetchSeq=13255128  CPSeq=11776621  flags=(IsInteger)
7306504500: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+24    :   ubfm   x0, x0, #12, #63  : IntAlu :  D=0x000000000008000f  FetchSeq=13255129  CPSeq=11776622  flags=(IsInteger)
7306504500: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+28    :   orr   x21, xzr, x30      : IntAlu :  D=0xffffff80080932e4  FetchSeq=13255130  CPSeq=11776623  flags=(IsInteger)
7306504500: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+32    :   bl   <pfn_valid>         : IntAlu :  D=0xffffff800809b82c  FetchSeq=13255131  CPSeq=11776624  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306505500: ExecEnable: system.cpu0: A0 T0 : @pfn_valid    : stp
7306505500: ExecEnable: system.cpu0: A0 T0 : @pfn_valid. 0 :   addxi_uop   ureg0, sp, #-16 : IntAlu :  D=0xffffff8008043da0  FetchSeq=13255132  CPSeq=11776625  flags=(IsInteger|IsMicroop|IsDelayedCommit|IsFirstMicroop)
7306509500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306510000
7306509750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306509750
7306509750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306509750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 3
7306509750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306509750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802200
7306509750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306514750
7306510000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306510000
7306510000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306510000
7306510000: Cache: system.cpu0.icache: access for ReadReq [801ae380:801ae3bf] IF D=4053d2d18f550000c020d4d18f550000d341ca0000000000000000002300ffff000000008f550000f0b1eac88f55000000b1eac88f550000ca8bf097fd7bc1a8 ptr=0x558fd070f800 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x2006b set: 0x8e way: 0x1
7306510000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306511000
7306510000: Cache: system.cpu0.dcache: access for ReadReq [80a26470:80a26473] D=18316acf ptr=0x558fd070fd00 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x10144 set: 0x191 way: 0x1
7306510000: Cache: system.cpu0.dcache: access for ReadReq [80a26488:80a2648f] D=e02f6acf8f550000 ptr=0x558fc9802700 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x10144 set: 0x192 way: 0x1
7306510000: Cache: system.cpu0.dcache: access for WriteReq [8d847db0:8d847db7] D=e03d040880ffffff ptr=0x558fc9802780 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f6 way: 0
7306510000: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847db0:8d847db7] D=e03d040880ffffff ptr=0x558fc9802780 (write)
7306510000: Cache: system.cpu0.dcache: access for WriteReq [8d847db8:8d847dbf] D=e432090880ffffff ptr=0x558fc9802000 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f6 way: 0
7306510000: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847db8:8d847dbf] D=e432090880ffffff ptr=0x558fc9802000 (write)
7306510000: Cache: system.cpu0.dcache: access for WriteReq [8d847dc0:8d847dc7] D=0400000000000000 ptr=0x558fd070ff80 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306510000: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847dc0:8d847dc7] D=0400000000000000 ptr=0x558fd070ff80 (write)
7306505500: ExecEnable: system.cpu0: A0 T0 : @pfn_valid. 1 :   strxi_uop   x29, [ureg0] : MemWrite :  D=0xffffff8008043db0 A=0xffffff8008043da0  FetchSeq=13255133  CPSeq=11776626  flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit)
7306505500: ExecEnable: system.cpu0: A0 T0 : @pfn_valid. 2 :   strxi_uop   x30, [ureg0, #8] : MemWrite :  D=0xffffff800809b82c A=0xffffff8008043da8  FetchSeq=13255134  CPSeq=11776627  flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit)
7306505500: ExecEnable: system.cpu0: A0 T0 : @pfn_valid. 3 :   addxi_uop   sp, ureg0, #0 : IntAlu :  D=0xffffff8008043da0  FetchSeq=13255135  CPSeq=11776628  flags=(IsInteger|IsMicroop|IsLastMicroop)
7306505500: ExecEnable: system.cpu0: A0 T0 : @pfn_valid+4    :   ubfm   x0, x0, #52, #51  : IntAlu :  D=0x000000008000f000  FetchSeq=13255136  CPSeq=11776629  flags=(IsInteger)
7306505500: ExecEnable: system.cpu0: A0 T0 : @pfn_valid+8    :   add   x29, sp, #0        : IntAlu :  D=0xffffff8008043da0  FetchSeq=13255137  CPSeq=11776630  flags=(IsInteger)
7306505500: ExecEnable: system.cpu0: A0 T0 : @pfn_valid+12    :   bl   <memblock_is_map_memory> : IntAlu :  D=0xffffff800809b1f8  FetchSeq=13255138  CPSeq=11776631  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306506500: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory    :   adrp   x1, #8880128      : IntAlu :  D=0xffffff8008a26000  FetchSeq=13255139  CPSeq=11776632  flags=(IsInteger)
7306510000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306510500
7306510000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306510000
7306510000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306510500
7306510500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306510500
7306510500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306510501
7306510500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306510500
7306510500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=0053d2d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00cd8f550000 ptr=0x558fc9824180
7306510500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=8043d2d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802300 BUSY
7306510500: Event: system.tol2bus.respLayer20.wrapped_function_event: EventFunctionWrapped 1328 executed @ 7306510500
7306510500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306510500
7306510500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306511000
7306510500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306510500
7306510500: Cache: system.cpu0.dcache: access for WriteReq [8d847dc8:8d847dcf] D=18909e0880ffffff ptr=0x558fc9802300 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306510500: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847dc8:8d847dcf] D=18909e0880ffffff ptr=0x558fc9802300 (write)
7306510500: Cache: system.cpu0.dcache: access for WriteReq [8d847dd0:8d847dd7] D=2487a00880ffffff ptr=0x558fc9802c00 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306510500: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847dd0:8d847dd7] D=2487a00880ffffff ptr=0x558fc9802c00 (write)
7306506500: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+4    :   add   x1, x1, #1120      : IntAlu :  D=0xffffff8008a26460  FetchSeq=13255140  CPSeq=11776633  flags=(IsInteger)
7306506500: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+8    :   movz   w4, #0, #0        : IntAlu :  D=0x0000000000000000  FetchSeq=13255141  CPSeq=11776634  flags=(IsInteger)
7306506500: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+12    :   movz   w7, #24, #0       : IntAlu :  D=0x0000000000000018  FetchSeq=13255142  CPSeq=11776635  flags=(IsInteger)
7306510500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306511000
7306510501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306510501
7306510501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306510502
7306510502: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306510502
7306510502: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306511000
7306511000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306511000
7306511000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306511001
7306511000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306511000
7306511000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306511000
7306511000: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=0053d2d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00cd8f550000 ptr=0x558fc9824180
7306511000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=0029d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070f800
7306511000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=0029d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070f800
7306511000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=0029d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070f800 SF size: 0 lat: 1
7306511000: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=0029d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070f800
7306511000: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306511000: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306511000: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306511000: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306511000: DRAM: system.mem_ctrls: Adding to read queue
7306511000: DRAM: system.mem_ctrls: Request scheduled immediately
7306511000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306511000
7306511000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306512000
7306511000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306511000 to 7306512000
7306511000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306514500
7306511000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306511000
7306511000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306511000: DRAM: system.mem_ctrls: Single request, going to a free rank
7306511000: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306511000: DRAM: system.mem_ctrls: Removing burstTick for 7306510000
7306511000: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306517000
7306511000: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306535750 next burst at 7306522000.
7306511000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306511000
7306511000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306511000
7306511000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306511000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306511000
7306511000: Cache: system.cpu0.icache: access for ReadReq [8009b1c0:8009b1ff] IF D=4008d1d18f550000c0bcacd38f550000e341ca0000000000000000000100ffff000000008f55000060bdeac88f55000040bceac88f550000ca8bf097fd7bc1a8 ptr=0x558fd070fc80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20026 set: 0xc7 way: 0
7306511000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306512000
7306511000: Cache: system.cpu0.dcache: access for WriteReq [8d847da0:8d847da7] D=b03d040880ffffff ptr=0x558fd070fe00 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f6 way: 0
7306511000: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847da0:8d847da7] D=b03d040880ffffff ptr=0x558fd070fe00 (write)
7306511000: Cache: system.cpu0.dcache: access for WriteReq [8d847da8:8d847daf] D=2cb8090880ffffff ptr=0x558fc9824080 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f6 way: 0
7306511000: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847da8:8d847daf] D=2cb8090880ffffff ptr=0x558fc9824080 (write)
7306511000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306511500
7306511000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306511000
7306511000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306511500
7306511001: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306511001
7306511001: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306511002
7306511002: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306511002
7306511002: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306511003
7306511003: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306511003
7306511003: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306511004
7306511004: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306511004
7306511004: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306511500
7306511500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306511500
7306511500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306511501
7306511500: Event: system.cpu5.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 291 executed @ 7306511500
7306511500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306511500
7306511500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306511500
7306511500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306512000
7306511500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306511500
7306511500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306512000
7306511500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306511500
7306511500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306512000
7306511501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306511501
7306511501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306512000
7306512000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306512000
7306512000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306512001
7306512000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306512000
7306512000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306512000
7306512000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306512000
7306512000: Cache: system.cpu0.icache: access for ReadReq [8009b200:8009b23f] IF D=00b2acd38f55000000a9acd38f5500004541ca000000000080f6d2d18f55000080d619d28f55000030abeac88f55000030abeac88f550000909fc7cd8f550000 ptr=0x558fd070fc80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20026 set: 0xc8 way: 0x1
7306512000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306513000
7306512000: Event: Event_102332: Functional unit completion 102332 scheduled @ 7306513000
7306507500: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+16    :   ldr   x3, [x1, #16]      : MemRead :  D=0x0000000000000001 A=0xffffff8008a26470  FetchSeq=13255143  CPSeq=11776636  flags=(IsInteger|IsMemRef|IsLoad)
7306512000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306512500
7306512000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306512000
7306512000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306512500
7306512000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306512000
7306512000: Cache: system.cpu5.icache: access for ReadReq [807371c0:807371ff] IF UC D=c03cd4d18f5500006374696f6e5772617070656420323239a0f7d6d18f550000403403d28f550000363530353030300a00bfeac88f55000010c3e9cd8f550000 ptr=0x558fd070fe00
7306512000: CachePort: system.cpu5.icache.mem_side: Scheduling send event at 7306513000
7306512000: Event: system.cpu5.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 293 scheduled @ 7306513000
7306512000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306512500
7306512001: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306512001
7306512500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306512500
7306512500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306513000
7306512500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306512500
7306512500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306513000
7306512500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306512500
7306507500: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+20    :   ldr   x5, [x1, #40]      : MemRead :  D=0xffffff8008a8c570 A=0xffffff8008a26488  FetchSeq=13255144  CPSeq=11776637  flags=(IsInteger|IsMemRef|IsLoad)
7306507500: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+24    :   b   <memblock_is_map_memory+56> : IntAlu :   FetchSeq=13255145  CPSeq=11776638  flags=(IsControl|IsDirectControl|IsUncondControl)
7306508000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+56    :   add   w1, w4, w3         : IntAlu :  D=0x0000000000000001  FetchSeq=13255146  CPSeq=11776639  flags=(IsInteger)
7306512500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306513000
7306513000: Event: system.cpu5.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 293 executed @ 7306513000
7306513000: Cache: system.cpu5.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c03cd4d18f5500006374696f6e5772617070656420323239a0f7d6d18f550000403403d28f550000363530353030300a00bfeac88f55000010c3e9cd8f550000 ptr=0x558fd070fe00
7306513000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[20] packet ReadReq [807371c0:807371ff] IF UC D=c020d4d18f5500000012d1d18f550000e741ca0000000000000000000300ffff000000002037333000b7eac88f55000030b1eac88f5500000000018ac31900d0 ptr=0x558fd070fd00
7306513000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[20] packet ReadReq [807371c0:807371ff] IF UC D=c020d4d18f5500000012d1d18f550000e741ca0000000000000000000300ffff000000002037333000b7eac88f55000030b1eac88f5500000000018ac31900d0 ptr=0x558fd070fd00
7306513000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[20] packet ReadReq [807371c0:807371ff] IF UC D=c020d4d18f5500000012d1d18f550000e741ca0000000000000000000300ffff000000002037333000b7eac88f55000030b1eac88f5500000000018ac31900d0 ptr=0x558fd070fd00 SF size: 0 lat: 0
7306513000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=c020d4d18f5500000012d1d18f550000e741ca0000000000000000000300ffff000000002037333000b7eac88f55000030b1eac88f5500000000018ac31900d0 ptr=0x558fd070fd00
7306513000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=c020d4d18f5500000012d1d18f550000e741ca0000000000000000000300ffff000000002037333000b7eac88f55000030b1eac88f5500000000018ac31900d0 ptr=0x558fd070fd00
7306513000: CachePort: system.l2.mem_side: Scheduling send event at 7306523500
7306513000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306513500
7306513000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306513000 to 7306513500
7306513000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306513000
7306513000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306513000
7306513000: Cache: system.cpu0.icache: access for ReadReq [8009b800:8009b83f] IF D=c00880c98f5500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e740090aeeac88f550000c0035fd61f2003d5 ptr=0x558fd070fc80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20026 set: 0xe0 way: 0
7306513000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306514000
7306508000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+60    :   ubfm   w1, w1, #1, #31   : IntAlu :  D=0x0000000000000000  FetchSeq=13255147  CPSeq=11776640  flags=(IsInteger)
7306513000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306513500
7306513000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306513000
7306513000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306513500
7306513000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306513000
7306513000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306513500
7306513000: Event: Event_102332: Functional unit completion 102332 executed @ 7306513000
7306513500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306513500
7306513500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306513500
7306513500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306514000
7306513500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306513500
7306513500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306513500
7306513500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306514000
7306514000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306514000
7306514000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306514000
7306514000: Cache: system.cpu0.icache: access for ReadReq [8009b880:8009b8bf] IF D=c093d6d18f5500006374696f6e5772617070656420313834203c03d28f550000608cd3d18f550000363530383030300a0000b2c98f55000090b4b9cd8f550000 ptr=0x558fd070fc80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20026 set: 0xe2 way: 0
7306514000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306515000
7306514000: Cache: system.cpu0.dcache: access for ReadReq [80a8c570:80a8c577] D=18316acf8f550000 ptr=0x558fc9802700 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x10151 set: 0x115 way: 0
7306514000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306515000
7306514000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306514500
7306514000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306514000
7306514000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306514500
7306514500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306514500
7306514500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=0033d4d18f5500006374696f6e5772617070656420343632203c03d28f5500006564204020373330363438303030300a002035370a0000000000000000000000 ptr=0x558fc8fb7f80
7306514500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c017d1d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9824080
7306514500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c017d1d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9824080
7306514500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c017d1d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9824080 SF size: 0 lat: 1
7306514500: CoherentXBar: system.membus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=c017d1d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9824080
7306514500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x80737180 size 64
7306514500: DRAM: system.mem_ctrls: Read queue limit 32, current size 4, entries needed 1
7306514500: DRAM: system.mem_ctrls: Address: 0x737180 Rank 1 Bank 3 Row 57
7306514500: DRAM: system.mem_ctrls: Read queue limit 32, current size 4, entries needed 1
7306514500: DRAM: system.mem_ctrls: Adding to read queue
7306514500: DRAM: system.mem_ctrls: Request scheduled immediately
7306514500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306514500
7306514500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306516000
7306514500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306514500 to 7306516000
7306514500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306515500
7306514500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306514500
7306514500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306514500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306514500: DRAM: system.mem_ctrls: Timing access to addr 0x737180, rank/bank/row 1 3 57
7306514500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306522000
7306514500: DRAM: system.mem_ctrls: Access to 0x737180, ready at 7306540750 next burst at 7306527000.
7306514500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306514500
7306514500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306514500
7306514500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306514500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306514500
7306514500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306515000
7306514500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306514500
7306514500: Cache: system.cpu0.dcache: access for ReadReq [80a8c578:80a8c57f] D=30326acf8f550000 ptr=0x558fc9802c00 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x10151 set: 0x115 way: 0
7306514500: Cache: system.cpu0.dcache: access for ReadReq [80a8c580:80a8c587] D=902d6acf8f550000 ptr=0x558fd070fe80 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x10151 set: 0x116 way: 0x1
7306514500: Cache: system.cpu0.dcache: access for ReadReq [8d847da0:8d847daf] D=b0f767d08f550000c0f867d08f550000 ptr=0x558fc9802300 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f6 way: 0
7306508000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+64    :   umaddl   x2, xzr, x1, x7 : IntMult :  D=0x0000000000000000  FetchSeq=13255148  CPSeq=11776641  flags=(IsInteger)
7306514500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306515000
7306514750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306514750
7306514750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306514750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 4
7306514750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306514750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824000
7306514750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306525750
7306515000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306515000
7306515000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306515500
7306515000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306515000
7306515000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306515000
7306508000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+68    :   add   x6, x5, x2         : IntAlu :  D=0xffffff8008a8c570  FetchSeq=13255149  CPSeq=11776642  flags=(IsInteger)
7306515000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306515500
7306515000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306515000
7306515000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306515500
7306515500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306515500
7306515500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306515501
7306515500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306515500
7306515500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=800ed1d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00d18f550000 ptr=0x558fc9802180
7306515500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=80abaed38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070fc80 BUSY
7306515500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306515500
7306511500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306511500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306511500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306515500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306516000
7306515500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306515500
7306515500: Cache: system.cpu0.icache: access for ReadReq [800932c0:800932ff] IF D=00bcacd38f5500006374696f6e5772617070656420323239c02fd6d18f5500006564204020373330363531323530300a00bceac88f5500000000000000000000 ptr=0x558fd070fc80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20024 set: 0xcb way: 0x1
7306515500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306516500
7306515500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306516000
7306515501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306515501
7306515501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306515502
7306515502: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306515502
7306516000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306516000
7306516000: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=800ed1d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00d18f550000 ptr=0x558fc9802180
7306516000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=00bcacd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070ff80
7306516000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=00bcacd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070ff80
7306516000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=00bcacd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070ff80 SF size: 0 lat: 1
7306516000: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=00bcacd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070ff80
7306516000: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306516000: DRAM: system.mem_ctrls: Read queue limit 32, current size 4, entries needed 1
7306516000: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306516000: DRAM: system.mem_ctrls: Read queue limit 32, current size 4, entries needed 1
7306516000: DRAM: system.mem_ctrls: Adding to read queue
7306516000: DRAM: system.mem_ctrls: Request scheduled immediately
7306516000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306516000
7306516000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306517000
7306516000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306516000 to 7306517000
7306516000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306519500
7306516000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306516000
7306516000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306516000: DRAM: system.mem_ctrls: Single request, going to a free rank
7306516000: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306516000: DRAM: system.mem_ctrls: Removing burstTick for 7306515000
7306516000: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306527000
7306516000: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306545750 next burst at 7306532000.
7306516000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306516000
7306516000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306516000
7306516000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306516000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306516000
7306508000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+72    :   ldr   x2, [x5, x2]       : MemRead :  D=0x0000000080000000 A=0xffffff8008a8c570  FetchSeq=13255150  CPSeq=11776643  flags=(IsInteger|IsMemRef|IsLoad)
7306516000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306516500
7306516000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306516000
7306516000: Cache: system.cpu5.icache: access for ReadReq [80737180:807371bf] IF UC D=0000d1d18f55000060cff8cc8f550000ac0000000000000040ddd1d18f550000c0c6d1d18f5500008878f2cc8f5500007078f2cc8f5500000000018ac31900d0 ptr=0x558fc9802000
7306516000: CachePort: system.cpu5.icache.mem_side: Scheduling send event at 7306517000
7306516000: Event: system.cpu5.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 293 scheduled @ 7306517000
7306516000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306516500
7306516500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306516500
7306516500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306516500
7306516500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306517000
7306516500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306516500
7306516500: Cache: system.cpu0.icache: access for ReadReq [80093300:8009333f] IF D=0095d6d18f550000400ad1d18f550000a900000000000000000000000100ffff000000006374696f70482acd8f55000058482acd8f5500000000000000000000 ptr=0x558fd070fc80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20024 set: 0xcc way: 0x1
7306516500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306517500
7306508000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+76    :   subs   x0, x2            : IntAlu :  D=0x0000000000000001  FetchSeq=13255151  CPSeq=11776644  flags=(IsInteger)
7306516500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306517000
7306517000: Event: system.cpu5.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 293 executed @ 7306517000
7306517000: Cache: system.cpu5.icache: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=0000d1d18f55000060cff8cc8f550000ac0000000000000040ddd1d18f550000c0c6d1d18f5500008878f2cc8f5500007078f2cc8f5500000000018ac31900d0 ptr=0x558fc9802000
7306517000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[20] packet ReadReq [80737180:807371bf] IF UC D=808fd6d18f55000008000014c80440f9240400114200088ba08ed3d18f550000203c03d28f5500008100030b217c0153227ca79ba600028ba26862f81f0002eb ptr=0x558fc9802700
7306517000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[20] packet ReadReq [80737180:807371bf] IF UC D=808fd6d18f55000008000014c80440f9240400114200088ba08ed3d18f550000203c03d28f5500008100030b217c0153227ca79ba600028ba26862f81f0002eb ptr=0x558fc9802700
7306517000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[20] packet ReadReq [80737180:807371bf] IF UC D=808fd6d18f55000008000014c80440f9240400114200088ba08ed3d18f550000203c03d28f5500008100030b217c0153227ca79ba600028ba26862f81f0002eb ptr=0x558fc9802700 SF size: 0 lat: 0
7306517000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=808fd6d18f55000008000014c80440f9240400114200088ba08ed3d18f550000203c03d28f5500008100030b217c0153227ca79ba600028ba26862f81f0002eb ptr=0x558fc9802700
7306517000: Cache: system.l2: access for ReadReq [80737180:807371bf] IF UC D=808fd6d18f55000008000014c80440f9240400114200088ba08ed3d18f550000203c03d28f5500008100030b217c0153227ca79ba600028ba26862f81f0002eb ptr=0x558fc9802700
7306517000: CachePort: system.l2.mem_side: Scheduling send event at 7306527500
7306517000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306517500
7306517000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306517000 to 7306517500
7306517000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306517000
7306517000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306517000
7306509000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+80    :   b.cs   <memblock_is_map_memory+28> : IntAlu :   FetchSeq=13255152  CPSeq=11776645  flags=(IsControl|IsDirectControl|IsCondControl)
7306510000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+28    :   ldr   x8, [x6, #8]       : MemRead :  D=0x0000000010000000 A=0xffffff8008a8c578  FetchSeq=13255153  CPSeq=11776646  flags=(IsInteger|IsMemRef|IsLoad)
7306510000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+32    :   add   w4, w1, #1         : IntAlu :  D=0x0000000000000001  FetchSeq=13255154  CPSeq=11776647  flags=(IsInteger)
7306510000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+36    :   add   x2, x2, x8         : IntAlu :  D=0x0000000090000000  FetchSeq=13255155  CPSeq=11776648  flags=(IsInteger)
7306517000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306517500
7306517000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306517000
7306517000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306517500
7306517500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306517500
7306517500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306517500
7306517500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306517500
7306517500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306518000
7306517500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306517500
7306517500: Cache: system.cpu0.icache: access for ReadReq [8009b380:8009b3bf] IF D=4094d6d18f5500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e740000000000000000000000000000000000 ptr=0x558fd070fc80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20026 set: 0xce way: 0x1
7306517500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306518500
7306517500: Cache: system.cpu0.dcache: access for ReadReq [8d847dd0:8d847dd7] D=782f6acf8f550000 ptr=0x558fc9802780 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306517500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306518500
7306517500: Cache: system.cpu0.dcache: access for ReadReq [8d847db0:8d847dbf] D=b0f267d08f5500000000000000000000 ptr=0x558fc9802600 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f6 way: 0
7306510000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+40    :   subs   x0, x2            : IntAlu :  D=0x0000000000000000  FetchSeq=13255156  CPSeq=11776649  flags=(IsInteger)
7306517500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306518000
7306518000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306518000
7306518000: Cache: system.cpu0.dcache: access for ReadReq [80934b00:80934b07] D=30326acf8f550000 ptr=0x558fc9802c00 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x10126 set: 0x12c way: 0x1
7306518000: Cache: system.cpu0.dcache: access for ReadReq [8d847dc0:8d847dcf] D=b0f267d08f5500000000000000000000 ptr=0x558fc9824100 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306510000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+44    :   b.cc   <memblock_is_map_memory+104> : IntAlu :   FetchSeq=13255157  CPSeq=11776650  flags=(IsControl|IsDirectControl|IsCondControl)
7306511000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+104    :   ldr   x0, [x6, #16]      : MemRead :  D=0x0000000000000000 A=0xffffff8008a8c580  FetchSeq=13255158  CPSeq=11776651  flags=(IsInteger|IsMemRef|IsLoad)
7306511000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+108    :   ubfm   x0, x0, #2, #63   : IntAlu :  D=0x0000000000000000  FetchSeq=13255159  CPSeq=11776652  flags=(IsInteger)
7306511000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+112    :   eor   x0, x0, #1         : IntAlu :  D=0x0000000000000001  FetchSeq=13255160  CPSeq=11776653  flags=(IsInteger)
7306518000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306518500
7306518000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306518000
7306518000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306518500
7306518500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306518500
7306518500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306518501
7306518500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306518500
7306518500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306518500
7306518500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306519000
7306518500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306518500
7306518500: Cache: system.cpu0.icache: access for ReadReq [8009b3c0:8009b3ff] IF D=8089d6d18f5500006573706f6e644576656e7428293a20534022d6d18f550000806474d08f5500006865642069747320726561647954696d650a009000003d91 ptr=0x558fd070fc80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20026 set: 0xcf way: 0x1
7306518500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306519500
7306511000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+116    :   and   w0, w0, #1         : IntAlu :  D=0x0000000000000001  FetchSeq=13255161  CPSeq=11776654  flags=(IsInteger)
7306511000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+120    :   ret                      : IntAlu :   FetchSeq=13255162  CPSeq=11776655  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306518500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306519000
7306518501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306518501
7306518501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306519000
7306519000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306519000
7306519000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306519001
7306519000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306519000
7306512000: ExecEnable: system.cpu0: A0 T0 : @pfn_valid+16    :   and   w0, w0, #255       : IntAlu :  D=0x0000000000000001  FetchSeq=13255163  CPSeq=11776656  flags=(IsInteger)
7306512000: ExecEnable: system.cpu0: A0 T0 : @pfn_valid+20    : ldp
7306512000: ExecEnable: system.cpu0: A0 T0 : @pfn_valid+20. 0 :   ldp_uop   x29, x30, [sp] : MemRead :  D=0xffffff800809b82c A=0xffffff8008043da0  FetchSeq=13255164  CPSeq=11776657  flags=(IsInteger|IsMemRef|IsLoad|IsMicroop|IsDelayedCommit|IsFirstMicroop)
7306512000: ExecEnable: system.cpu0: A0 T0 : @pfn_valid+20. 1 :   addxi_uop   sp, sp, #16  : IntAlu :  D=0xffffff8008043db0  FetchSeq=13255165  CPSeq=11776658  flags=(IsInteger|IsMicroop|IsLastMicroop)
7306513000: ExecEnable: system.cpu0: A0 T0 : @pfn_valid+24    :   ret                      : IntAlu :   FetchSeq=13255166  CPSeq=11776659  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306519000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306519500
7306519000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306519000
7306519000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306519500
7306519001: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306519001
7306519500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306519500
7306519500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306519500
7306519500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=c034d4d18f5500000091d6d18f550000c441ca0000000000000000000000ffff0000000020373330f0a8eac88f550000d0b3eac88f55000010d8e9cd8f550000 ptr=0x558fc8fb7d00
7306519500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=801f80c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070fc80
7306519500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=801f80c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070fc80
7306519500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=801f80c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070fc80 SF size: 0 lat: 1
7306519500: CoherentXBar: system.membus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=801f80c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070fc80
7306519500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x80737180 size 64
7306519500: DRAM: system.mem_ctrls: Read queue limit 32, current size 5, entries needed 1
7306519500: DRAM: system.mem_ctrls: Address: 0x737180 Rank 1 Bank 3 Row 57
7306519500: DRAM: system.mem_ctrls: Read queue limit 32, current size 5, entries needed 1
7306519500: DRAM: system.mem_ctrls: Adding to read queue
7306519500: DRAM: system.mem_ctrls: Request scheduled immediately
7306519500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306519500
7306519500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306521000
7306519500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306519500 to 7306521000
7306519500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306523500
7306519500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306519500
7306519500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306519500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306519500: DRAM: system.mem_ctrls: Timing access to addr 0x737180, rank/bank/row 1 3 57
7306519500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306532000
7306519500: DRAM: system.mem_ctrls: Access to 0x737180, ready at 7306550750 next burst at 7306537000.
7306519500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306519500
7306519500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306519500
7306519500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306519500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306519500
7306519500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306520000
7306519500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306519500
7306519500: Cache: system.cpu0.icache: access for ReadReq [80093300:8009333f] IF D=803dd4d18f550000c0bcacd38f550000f841ca0000000000000000000000ffff000000008f55000098b2eac88f55000080afeac88f550000c0035fd6e04000f0 ptr=0x558fd070fe80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20024 set: 0xcc way: 0x1
7306519500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306520500
7306519500: Cache: system.cpu0.dcache: access for ReadReq [80934b10:80934b17] D=902d6acf8f550000 ptr=0x558fc9802a00 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x10126 set: 0x12c way: 0x1
7306519500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306520500
7306514000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+36    :   cbnz   w0, <ioremap_cache+124> : IntAlu :   FetchSeq=13255167  CPSeq=11776660  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+124    :   adrp   x0, #9015296      : IntAlu :  D=0xffffff8008934000  FetchSeq=13255168  CPSeq=11776661  flags=(IsInteger)
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+128    :   ldr   x21, [sp, #32]     : MemRead :  D=0xffffff8008a08724 A=0xffffff8008043dd0  FetchSeq=13255169  CPSeq=11776662  flags=(IsInteger|IsMemRef|IsLoad)
7306519500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306520000
7306520000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306520000
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+132    :   ldr   x0, [x0, #2816]    : MemRead :  D=0x0000000080000000 A=0xffffff8008934b00  FetchSeq=13255170  CPSeq=11776663  flags=(IsInteger|IsMemRef|IsLoad)
7306520000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306520500
7306520000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306520000
7306520000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306520500
7306520500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306520500
7306520500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306520500
7306520500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306520500
7306520500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306521000
7306520500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306520500
7306520500: Cache: system.cpu0.icache: access for ReadReq [8009b7c0:8009b7ff] IF D=00bcacd38f55000000dd82c98f5500000142ca0000000000000000001500ffff000000002f62616eb8b9eac88f55000060baeac88f5500000000000000000000 ptr=0x558fd070fe80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20026 set: 0xdf way: 0x1
7306520500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306521500
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+136    :   sub   x0, x19, x0        : IntAlu :  D=0x000000000000fff8  FetchSeq=13255171  CPSeq=11776664  flags=(IsInteger)
7306520500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306521000
7306521000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306521000
7306521000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306521000
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+140    :   orr   x0, x0, #18446743798831644672 : IntAlu :  D=0xffffffc00000fff8  FetchSeq=13255172  CPSeq=11776665  flags=(IsInteger)
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+144    : ldp
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+144. 0 :   addxi_uop   ureg0, sp, #16 : IntAlu :  D=0xffffff8008043dc0  FetchSeq=13255173  CPSeq=11776666  flags=(IsInteger|IsMicroop|IsDelayedCommit|IsFirstMicroop)
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+144. 1 :   ldp_uop   x19, x20, [ureg0] : MemRead :  D=0xffffff80089e9018 A=0xffffff8008043dc0  FetchSeq=13255174  CPSeq=11776667  flags=(IsInteger|IsMemRef|IsLoad|IsMicroop|IsLastMicroop)
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+148    : ldp
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+148. 0 :   ldp_uop   x29, x30, [sp] : MemRead :  D=0xffffff80080932e4 A=0xffffff8008043db0  FetchSeq=13255175  CPSeq=11776668  flags=(IsInteger|IsMemRef|IsLoad|IsMicroop|IsDelayedCommit|IsFirstMicroop)
7306515500: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+148. 1 :   addxi_uop   sp, sp, #48  : IntAlu :  D=0xffffff8008043de0  FetchSeq=13255176  CPSeq=11776669  flags=(IsInteger|IsMicroop|IsLastMicroop)
7306515500: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+152    :   ret                      : IntAlu :   FetchSeq=13255177  CPSeq=11776670  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306521000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306521500
7306521000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306521000
7306521000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306521500
7306521500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306521500
7306521500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306521500
7306521500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306521500
7306521500: Cache: system.cpu0.icache: access for ReadReq [80093300:8009333f] IF D=40d282c98f5500006374696f6e5772617070656420343232009bd3d18f550000203c03d28f550000363531343530300a007c74d08f550000009bd3d18f550000 ptr=0x558fd070fe80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20024 set: 0xcc way: 0x1
7306521500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306522500
7306516500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+36    :   orr   x19, xzr, x0       : IntAlu :  D=0xffffffc00000fff8  FetchSeq=13255178  CPSeq=11776671  flags=(IsInteger)
7306516500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+40    :   cbz   x0, <smp_spin_table_cpu_prepare+112> : IntAlu :   FetchSeq=13255179  CPSeq=11776672  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7306516500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+44    :   adrp   x2, #9048064      : IntAlu :  D=0xffffff8008934000  FetchSeq=13255180  CPSeq=11776673  flags=(IsInteger)
7306516500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+48    :   adrp   x1, #6963200      : IntAlu :  D=0xffffff8008737000  FetchSeq=13255181  CPSeq=11776674  flags=(IsInteger)
7306516500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+52    :   add   x1, x1, #416       : IntAlu :  D=0xffffff80087371a0  FetchSeq=13255182  CPSeq=11776675  flags=(IsInteger)
7306516500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+56    :   ldr   x2, [x2, #2832]    : MemRead :  D=0xffffff7f88000000 A=0xffffff8008934b10  FetchSeq=13255183  CPSeq=11776676  flags=(IsInteger|IsMemRef|IsLoad)
7306521500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306522000
7306522000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306522000
7306516500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+60    :   sub   x1, x1, x2         : IntAlu :  D=0x00000000807371a0  FetchSeq=13255184  CPSeq=11776677  flags=(IsInteger)
7306522000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306522500
7306522500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306522500
7306522500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306522500
7306522500: Cache: system.cpu0.icache: access for ReadReq [80993fc0:80993fff] IF D=c0b6acd38f5500006374696f6e5772617070656420323734c0c6d1d18f550000208185c98f550000363531363530300a00012bcd8f5500000000000000000000 ptr=0x558fd070fe80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20264 set: 0xff way: 0
7306522500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306523500
7306517500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+64    :   str   x1, [x0]           : MemWrite :  D=0x00000000807371a0 A=0xffffffc00000fff8  FetchSeq=13255185  CPSeq=11776678  flags=(IsInteger|IsMemRef|IsStore)
7306517500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+68    :   movz   x1, #8, #0        : IntAlu :  D=0x0000000000000008  FetchSeq=13255186  CPSeq=11776679  flags=(IsInteger)
7306517500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+72    :   bl   <__flush_dcache_area> : IntAlu :  D=0xffffff800809330c  FetchSeq=13255187  CPSeq=11776680  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306522500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306523000
7306523000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306523000
7306523000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306523500
7306523500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306523500
7306523500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306523500
7306523500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c020d4d18f5500000012d1d18f550000e741ca0000000000000000000300ffff000000002037333000b7eac88f55000030b1eac88f5500000000018ac31900d0 ptr=0x558fd070fd00
7306523500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=00b7acd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070fe80
7306523500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=00b7acd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070fe80
7306523500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=00b7acd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070fe80 SF size: 0 lat: 1
7306523500: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=00b7acd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070fe80
7306523500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306523500: DRAM: system.mem_ctrls: Read queue limit 32, current size 6, entries needed 1
7306523500: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306523500: DRAM: system.mem_ctrls: Read queue limit 32, current size 6, entries needed 1
7306523500: DRAM: system.mem_ctrls: Adding to read queue
7306523500: DRAM: system.mem_ctrls: Request scheduled immediately
7306523500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306523500
7306523500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306525000
7306523500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306523500 to 7306525000
7306523500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306527500
7306523500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306523500
7306523500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306523500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306523500: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306523500: DRAM: system.mem_ctrls: Removing burstTick for 7306520000
7306523500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306537000
7306523500: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306555750 next burst at 7306542000.
7306523500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306523500
7306523500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306523500
7306523500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306523500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306523500
7306523500: Cache: system.cpu0.icache: access for ReadReq [80712540:8071257f] IF D=8089d6d18f550000602febc88f5500001342ca0000000000000000002100ffff000000008f55000088aaeac88f55000050a9eac88f550000a04503d28f550000 ptr=0x558fc9802a00 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x201c4 set: 0x95 way: 0
7306523500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306524500
7306523500: Cache: system.cpu0.dcache: access for WriteReq [8000fff8:8000ffff] D=a071738000000000 ptr=0x558fc9802600 miss
7306523500: CachePort: system.cpu0.dcache.mem_side: Scheduling send event at 7306524500
7306523500: Event: system.cpu0.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 55 scheduled @ 7306524500
7306523500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306524000
7306524000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306524000
7306524000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306524500
7306524500: Event: system.cpu0.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 55 executed @ 7306524500
7306524500: Cache: system.cpu0.dcache: sendMSHRQueuePacket: MSHR WriteReq [8000fff8:8000ffff] D=a071738000000000 ptr=0x558fc9802600
7306524500: Cache: system.cpu0.dcache: createMissPacket: created ReadExReq [8000ffc0:8000ffff] D=808cd6d18f55000000b7acd38f550000aa00000000000000e070d4d18f55000080f6d2d18f55000030432acd8f55000030432acd8f550000a500209105c018d5 ptr=0x558fc9824100 from WriteReq [8000fff8:8000ffff] D=a071738000000000 ptr=0x558fc9802600
7306524500: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[1] packet ReadExReq [8000ffc0:8000ffff] D=808cd6d18f55000000b7acd38f550000aa00000000000000e070d4d18f55000080f6d2d18f55000030432acd8f55000030432acd8f550000a500209105c018d5 ptr=0x558fc9824100
7306524500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[1] packet ReadExReq [8000ffc0:8000ffff] D=808cd6d18f55000000b7acd38f550000aa00000000000000e070d4d18f55000080f6d2d18f55000030432acd8f55000030432acd8f550000a500209105c018d5 ptr=0x558fc9824100
7306524500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306524500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306524500: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[1] packet ReadExReq [8000ffc0:8000ffff] D=808cd6d18f55000000b7acd38f550000aa00000000000000e070d4d18f55000080f6d2d18f55000030432acd8f55000030432acd8f550000a500209105c018d5 ptr=0x558fc9824100 SF size: 0 lat: 0
7306524500: CoherentXBar: system.tol2bus: forwardTiming for ReadExReq [8000ffc0:8000ffff] D=808cd6d18f55000000b7acd38f550000aa00000000000000e070d4d18f55000080f6d2d18f55000030432acd8f55000030432acd8f550000a500209105c018d5 ptr=0x558fc9824100
7306524500: Cache: system.l2: access for ReadExReq [8000ffc0:8000ffff] D=808cd6d18f55000000b7acd38f550000aa00000000000000e070d4d18f55000080f6d2d18f55000030432acd8f55000030432acd8f550000a500209105c018d5 ptr=0x558fc9824100 miss
7306524500: CachePort: system.l2.mem_side: Scheduling send event at 7306535000
7306524500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306525000
7306524500: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306524500 to 7306525000
7306524500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306524500
7306524500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306524500
7306524500: Cache: system.cpu0.icache: access for ReadReq [80712580:807125bf] IF D=8090d6d18f5500004059d2d18f5500000e42ca0000000000000000000100ffff000000002037333008b8eac88f55000098b5eac88f550000c2ffff3520008052 ptr=0x558fc9802a00 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x201c4 set: 0x96 way: 0
7306524500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306525500
7306524500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306525000
7306525000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306525000
7306525000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306525000
7306525000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306525000
7306525000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306525500
7306525500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306525500
7306525500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306525500
7306525500: Cache: system.cpu0.icache: access for ReadReq [80994000:8099403f] IF D=0095d6d18f5500006f6c326275732e7265714c61796572308084d0d18f550000403d03d28f5500006e5f6576656e7400363531333030300a0000000000000000 ptr=0x558fc9802a00 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20265 set: 0 way: 0x1
7306525500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306526500
7306525500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306526000
7306525750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306525750
7306525750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306525750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 6
7306525750: DRAM: system.mem_ctrls: Responding to Address 0x807371c0
7306525750: DRAM: system.mem_ctrls: Done: ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802500
7306525750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306530750
7306526000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306526000
7306526000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306526500
7306526500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306526500
7306526500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306526500
7306526500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306527000
7306527000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306527000
7306527000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306527500
7306527500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306527500
7306527500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=808fd6d18f55000008000014c80440f9240400114200088ba08ed3d18f550000203c03d28f5500008100030b217c0153227ca79ba600028ba26862f81f0002eb ptr=0x558fc9802700
7306527500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=0095d6d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802a00
7306527500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=0095d6d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802a00
7306527500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=0095d6d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802a00 SF size: 0 lat: 1
7306527500: CoherentXBar: system.membus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=0095d6d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802a00
7306527500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x80737180 size 64
7306527500: DRAM: system.mem_ctrls: Read queue limit 32, current size 6, entries needed 1
7306527500: DRAM: system.mem_ctrls: Address: 0x737180 Rank 1 Bank 3 Row 57
7306527500: DRAM: system.mem_ctrls: Read queue limit 32, current size 6, entries needed 1
7306527500: DRAM: system.mem_ctrls: Adding to read queue
7306527500: DRAM: system.mem_ctrls: Request scheduled immediately
7306527500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306527500
7306527500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306529000
7306527500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306527500 to 7306529000
7306527500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306535000
7306527500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306527500
7306527500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306527500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306527500: DRAM: system.mem_ctrls: Timing access to addr 0x737180, rank/bank/row 1 3 57
7306527500: DRAM: system.mem_ctrls: Removing burstTick for 7306525000
7306527500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306542000
7306527500: DRAM: system.mem_ctrls: Access to 0x737180, ready at 7306560750 next burst at 7306547000.
7306527500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306527500
7306527500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306527500
7306527500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306527500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306527500
7306527500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306528000
7306527750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306527750
7306527750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f280
7306527750: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f280
7306527750: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306530000
7306527750: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306533000
7306527750: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306527750 to 7306533000
7306527750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306533250
7306528000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306528000
7306528000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306528500
7306528500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306528500
7306528500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306529000
7306529000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306529000
7306529000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306529000
7306529000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306529500
7306529500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306529500
7306529500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306530000
7306530000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306530000
7306530000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f280
7306530000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306544000
7306530000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f280
7306530000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306530000
7306530000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306530500
7306530500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306530500
7306530500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306531000
7306530750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306530750
7306530750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306530750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 6
7306530750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306530750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400
7306530750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306535750
7306531000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306531000
7306531000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306531500
7306531500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306531500
7306531500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306532000
7306532000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306532000
7306532000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306532500
7306532500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306532500
7306532500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306533000
7306533000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306533000
7306533000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306533000
7306533000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306533500
7306533250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306533250
7306533250: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f580
7306533250: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f580
7306533250: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306536000
7306533250: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306539000
7306533250: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306533250 to 7306539000
7306533250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306538250
7306533500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306533500
7306533500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306534000
7306534000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306534000
7306534000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306534500
7306534500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306534500
7306534500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306535000
7306535000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306535000
7306535000: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadExReq [8000ffc0:8000ffff] D=808cd6d18f55000000b7acd38f550000aa00000000000000e070d4d18f55000080f6d2d18f55000030432acd8f55000030432acd8f550000a500209105c018d5 ptr=0x558fc9824100
7306535000: Cache: system.l2: createMissPacket: created ReadExReq [8000ffc0:8000ffff] D=c04bd2d18f550000f09cc7cd8f550000609dc7cd8f550000d09dc7cd8f550000409ec7cd8f550000b09ec7cd8f550000209fc7cd8f550000909fc7cd8f550000 ptr=0x558fd070f280 from ReadExReq [8000ffc0:8000ffff] D=808cd6d18f55000000b7acd38f550000aa00000000000000e070d4d18f55000080f6d2d18f55000030432acd8f55000030432acd8f550000a500209105c018d5 ptr=0x558fc9824100
7306535000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadExReq [8000ffc0:8000ffff] D=c04bd2d18f550000f09cc7cd8f550000609dc7cd8f550000d09dc7cd8f550000409ec7cd8f550000b09ec7cd8f550000209fc7cd8f550000909fc7cd8f550000 ptr=0x558fd070f280
7306535000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadExReq [8000ffc0:8000ffff] D=c04bd2d18f550000f09cc7cd8f550000609dc7cd8f550000d09dc7cd8f550000409ec7cd8f550000b09ec7cd8f550000209fc7cd8f550000909fc7cd8f550000 ptr=0x558fd070f280
7306535000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306535000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306535000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadExReq [8000ffc0:8000ffff] D=c04bd2d18f550000f09cc7cd8f550000609dc7cd8f550000d09dc7cd8f550000409ec7cd8f550000b09ec7cd8f550000209fc7cd8f550000909fc7cd8f550000 ptr=0x558fd070f280 SF size: 0 lat: 1
7306535000: CoherentXBar: system.membus: forwardTiming for ReadExReq [8000ffc0:8000ffff] D=c04bd2d18f550000f09cc7cd8f550000609dc7cd8f550000d09dc7cd8f550000409ec7cd8f550000b09ec7cd8f550000209fc7cd8f550000909fc7cd8f550000 ptr=0x558fd070f280
7306535000: DRAM: system.mem_ctrls: recvTimingReq: request ReadExReq addr 0x8000ffc0 size 64
7306535000: DRAM: system.mem_ctrls: Read queue limit 32, current size 6, entries needed 1
7306535000: DRAM: system.mem_ctrls: Read to addr 0xffc0 with size 64 serviced by write queue
7306535000: DRAM: system.mem_ctrls: Responding to Address 0x8000ffc0
7306535000: DRAM: system.mem_ctrls: Done: ReadExResp [8000ffc0:8000ffff] D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fd070f280
7306535000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306536000
7306535000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306535000 to 7306536000
7306535000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306535000
7306535000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306535500
7306535500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306535500
7306535500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306536000
7306535750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306535750
7306535750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306535750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 5
7306535750: DRAM: system.mem_ctrls: Responding to Address 0x807371c0
7306535750: DRAM: system.mem_ctrls: Done: ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f800
7306535750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306540750
7306536000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306536000
7306536000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306536000
7306536000: Cache: system.l2: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f580
7306536000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f580
7306536000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306536000
7306536000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306536500
7306536500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306536500
7306536500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306537000
7306537000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306537000
7306537000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306537500
7306537500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306537500
7306537500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306538000
7306538000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306538000
7306538000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306538500
7306538250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306538250
7306538250: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802200 BUSY
7306538500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306538500
7306538500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306539000
7306539000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306539000
7306539000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802200
7306539000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802200
7306539000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306541000
7306539000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306544000
7306539000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306539000 to 7306544000
7306539000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306542750
7306539000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306539000
7306539000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306539500
7306539500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306539500
7306539500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306540000
7306540000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306540000
7306540000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306540500
7306540500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306540500
7306540500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306541000
7306540750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306540750
7306540750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306540750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 4
7306540750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306540750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824080
7306540750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306545750
7306541000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306541000
7306541000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802200
7306541000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802200
7306541000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306541000
7306541000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306541500
7306541500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306541500
7306541500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306542000
7306542000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306542000
7306542000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306542500
7306542500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306542500
7306542500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306543000
7306542750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306542750
7306542750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824000 BUSY
7306543000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306543000
7306543000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306543500
7306543500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306543500
7306543500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306544000
7306544000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306544000
7306544000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824000
7306544000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824000
7306544000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306546000
7306544000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306549000
7306544000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306544000 to 7306549000
7306544000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306553000
7306544000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306544000
7306544000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00
7306544000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[24] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00
7306544000: Event: system.tol2bus.slave[24]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1335 scheduled @ 7306544500
7306544000: Event: system.tol2bus.respLayer24.wrapped_function_event: EventFunctionWrapped 1336 scheduled @ 7306545500
7306544000: BaseXBar: system.tol2bus.respLayer24: The crossbar layer is now busy from tick 7306544000 to 7306545500
7306544000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306550000
7306544000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306544000
7306544000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306544500
7306544500: Event: system.tol2bus.slave[24]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1335 executed @ 7306544500
7306544500: Cache: system.cpu6.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00
7306544500: Event: system.cpu6.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 336 scheduled @ 7306546500
7306544500: CacheVerbose: system.cpu6.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00
7306544500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306544500
7306544500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306545000
7306545000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306545000
7306545000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306545500
7306545500: Event: system.tol2bus.respLayer24.wrapped_function_event: EventFunctionWrapped 1336 executed @ 7306545500
7306545500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306545500
7306545500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306546000
7306545750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306545750
7306545750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306545750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 3
7306545750: DRAM: system.mem_ctrls: Responding to Address 0x807371c0
7306545750: DRAM: system.mem_ctrls: Done: ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070ff80
7306545750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306550750
7306546000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306546000
7306546000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824000
7306546000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824000
7306546000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306546000
7306546000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306546500
7306546500: Event: system.cpu6.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 336 executed @ 7306546500
7306546500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306546500
7306546500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306546500
7306546500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306547000
7306546500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306546500
7306546500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306547000
7306547000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306547000
7306547000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306547500
7306547000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306547000
7306547000: Cache: system.cpu6.icache: access for ReadReq [807371c0:807371ff] IF UC D=00c582c98f55000080abaed38f5500000642ca0000000000000000001000ffff000000008f55000000b4eac88f550000d0bceac88f55000090dbe9cd8f550000 ptr=0x558fc8fb7e00
7306547000: CachePort: system.cpu6.icache.mem_side: Scheduling send event at 7306548000
7306547000: Event: system.cpu6.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 338 scheduled @ 7306548000
7306547000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306547500
7306547500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306547500
7306547500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306548000
7306547500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306547500
7306547500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306548000
7306548000: Event: system.cpu6.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 338 executed @ 7306548000
7306548000: Cache: system.cpu6.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=00c582c98f55000080abaed38f5500000642ca0000000000000000001000ffff000000008f55000000b4eac88f550000d0bceac88f55000090dbe9cd8f550000 ptr=0x558fc8fb7e00
7306548000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[24] packet ReadReq [807371c0:807371ff] IF UC D=c00880c98f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363534383030300a00bfeac88f5500000000018ac31900d0 ptr=0x558fc9824000
7306548000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[24] packet ReadReq [807371c0:807371ff] IF UC D=c00880c98f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363534383030300a00bfeac88f5500000000018ac31900d0 ptr=0x558fc9824000
7306548000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[24] packet ReadReq [807371c0:807371ff] IF UC D=c00880c98f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363534383030300a00bfeac88f5500000000018ac31900d0 ptr=0x558fc9824000 SF size: 0 lat: 0
7306548000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=c00880c98f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363534383030300a00bfeac88f5500000000018ac31900d0 ptr=0x558fc9824000
7306548000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=c00880c98f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363534383030300a00bfeac88f5500000000018ac31900d0 ptr=0x558fc9824000
7306548000: CachePort: system.l2.mem_side: Scheduling send event at 7306558500
7306548000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306558500
7306548000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306548500
7306548000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306548000 to 7306548500
7306548000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306548000
7306548000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306548500
7306548000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306548000
7306548000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306548500
7306548500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306548500
7306548500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306548500
7306548500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306549000
7306548500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306548500
7306548500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306549000
7306549000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306549000
7306549000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306549000
7306549000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306549500
7306549000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306549000
7306549000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306549500
7306549500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306549500
7306549500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306550000
7306549500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306549500
7306549500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306550000
7306550000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306550000
7306550000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802100
7306550000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[4] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802100
7306550000: Event: system.tol2bus.slave[4]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1295 scheduled @ 7306550500
7306550000: Event: system.tol2bus.respLayer4.wrapped_function_event: EventFunctionWrapped 1296 scheduled @ 7306551500
7306550000: BaseXBar: system.tol2bus.respLayer4: The crossbar layer is now busy from tick 7306550000 to 7306551500
7306550000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306555000
7306550000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306550000
7306550000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306550500
7306550000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306550000
7306550000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306550500
7306550500: Event: system.tol2bus.slave[4]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1295 executed @ 7306550500
7306550500: Cache: system.cpu1.icache: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802100
7306550500: Event: system.cpu1.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 111 scheduled @ 7306552500
7306550500: CacheVerbose: system.cpu1.icache: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802100
7306550500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306550500
7306546500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306546500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306546500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306550500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306551000
7306550500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306550500
7306550500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306551000
7306550750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306550750
7306550750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306550750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 2
7306550750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306550750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fc80
7306550750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306555750
7306551000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306551000
7306551000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306551500
7306551000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306551000
7306551000: Cache: system.cpu6.icache: access for ReadReq [80737180:807371bf] IF UC D=4001d1d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00cd8f550000 ptr=0x558fc9802100
7306551000: CachePort: system.cpu6.icache.mem_side: Scheduling send event at 7306552000
7306551000: Event: system.cpu6.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 338 scheduled @ 7306552000
7306551000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306551500
7306551500: Event: system.tol2bus.respLayer4.wrapped_function_event: EventFunctionWrapped 1296 executed @ 7306551500
7306551500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306551500
7306551500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306552000
7306551500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306551500
7306551500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306552000
7306552000: Event: system.cpu6.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 338 executed @ 7306552000
7306552000: Cache: system.cpu6.icache: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=4001d1d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00cd8f550000 ptr=0x558fc9802100
7306552000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[24] packet ReadReq [80737180:807371bf] IF UC D=4097d6d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363535323030300a001fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00
7306552000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[24] packet ReadReq [80737180:807371bf] IF UC D=4097d6d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363535323030300a001fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00
7306552000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[24] packet ReadReq [80737180:807371bf] IF UC D=4097d6d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363535323030300a001fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00 SF size: 0 lat: 0
7306552000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=4097d6d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363535323030300a001fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00
7306552000: Cache: system.l2: access for ReadReq [80737180:807371bf] IF UC D=4097d6d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363535323030300a001fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00
7306552000: CachePort: system.l2.mem_side: Scheduling send event at 7306562500
7306552000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306552500
7306552000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306552000 to 7306552500
7306552000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306552000
7306552000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306552500
7306552000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306552000
7306552000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306552500
7306552500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306552500
7306552500: Event: system.cpu1.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 111 executed @ 7306552500
7306552500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306552500
7306552500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306553000
7306552500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306552500
7306552500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306553000
7306553000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306553000
7306553000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadExResp [8000ffc0:8000ffff] D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fd070f280
7306553000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadExResp [8000ffc0:8000ffff] D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fd070f280
7306553000: SnoopFilter: system.membus.snoop_filter: updateResponse:   old SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306553000: SnoopFilter: system.membus.snoop_filter: updateResponse:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306553000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306555000
7306553000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306558000
7306553000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306553000 to 7306558000
7306553000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306553750
7306553000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306553000
7306553000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306553500
7306553000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306553000
7306553000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306553500
7306553500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306553500
7306553500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306554000
7306553500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306553500
7306553500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306554000
7306553750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306553750
7306553750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802500 BUSY
7306554000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306554000
7306554000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306554500
7306554000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306554000
7306554000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306554500
7306554500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306554500
7306554500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306555000
7306554500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306554500
7306554500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306555000
7306555000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306555000
7306555000: Cache: system.l2: recvTimingResp: Handling response ReadExResp [8000ffc0:8000ffff] D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fd070f280
7306555000: Cache: system.l2: Block for addr 0x8000ffc0 being updated in Cache
7306555000: CacheRepl: system.l2: Replacement victim: state: 0 (I) valid: 0 writable: 0 readable: 0 dirty: 0 | tag: 0xffffffffffffffff set: 0x3ff way: 0x1
7306555000: Cache: system.l2: Block addr 0x8000ffc0 (ns) moving from state 0 (I) to state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x2000 set: 0x3ff way: 0x1
7306555000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadExResp [8000ffc0:8000ffff] D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fd070f280
7306555000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306555000
7306555000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80
7306555000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[4] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80
7306555000: Event: system.tol2bus.slave[4]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1295 scheduled @ 7306555500
7306555000: Event: system.tol2bus.respLayer4.wrapped_function_event: EventFunctionWrapped 1296 scheduled @ 7306556500
7306555000: BaseXBar: system.tol2bus.respLayer4: The crossbar layer is now busy from tick 7306555000 to 7306556500
7306555000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306560000
7306555000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306555000
7306555000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306555500
7306555000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306555000
7306555000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306555500
7306555500: Event: system.tol2bus.slave[4]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1295 executed @ 7306555500
7306555500: Cache: system.cpu1.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80
7306555500: Event: system.cpu1.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 111 scheduled @ 7306557500
7306555500: CacheVerbose: system.cpu1.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80
7306555500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306555500
7306555500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306556000
7306555500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306555500
7306555500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306556000
7306555750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306555750
7306555750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306555750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 1
7306555750: DRAM: system.mem_ctrls: Responding to Address 0x807371c0
7306555750: DRAM: system.mem_ctrls: Done: ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fe80
7306555750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306560750
7306556000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306556000
7306556000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306556500
7306556000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306556000
7306556000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306556500
7306556500: Event: system.tol2bus.respLayer4.wrapped_function_event: EventFunctionWrapped 1296 executed @ 7306556500
7306556500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306556500
7306556500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306556500
7306556500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306557000
7306557000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306557000
7306557000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306557500
7306557500: Event: system.cpu1.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 111 executed @ 7306557500
7306557500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306557500
7306557500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306557500
7306557500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306558000
7306557500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306557500
7306557500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306558000
7306558000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306558000
7306558000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802500
7306558000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802500
7306558000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306560000
7306558000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306563000
7306558000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306558000 to 7306563000
7306558000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306559250
7306558000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306558000
7306558000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306558500
7306558000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306558000
7306558000: Cache: system.cpu1.icache: access for ReadReq [807371c0:807371ff] IF UC D=803cd4d18f5500006374696f6e577261707065642031323835207363686564756c6564204020373330363535323530300a0052cd8f55000090dbe9cd8f550000 ptr=0x558fd070f980
7306558000: CachePort: system.cpu1.icache.mem_side: Scheduling send event at 7306559000
7306558000: Event: system.cpu1.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 113 scheduled @ 7306559000
7306558000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306558500
7306558500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306558500
7306558500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c00880c98f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363534383030300a00bfeac88f5500000000018ac31900d0 ptr=0x558fc9824000
7306558500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=400080c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802b80
7306558500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=400080c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802b80
7306558500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=400080c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802b80 SF size: 0 lat: 1
7306558500: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=400080c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802b80
7306558500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306558500: DRAM: system.mem_ctrls: Read queue limit 32, current size 1, entries needed 1
7306558500: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306558500: DRAM: system.mem_ctrls: Read queue limit 32, current size 1, entries needed 1
7306558500: DRAM: system.mem_ctrls: Adding to read queue
7306558500: DRAM: system.mem_ctrls: Request scheduled immediately
7306558500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306558500
7306558500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306560000
7306558500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306558500 to 7306560000
7306558500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306562500
7306558500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306558500
7306558500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306558500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306558500: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306558500: DRAM: system.mem_ctrls: Removing burstTick for 7306540000
7306558500: DRAM: system.mem_ctrls: Removing burstTick for 7306535000
7306558500: DRAM: system.mem_ctrls: Removing burstTick for 7306530000
7306558500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306558500
7306558500: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306577250 next burst at 7306563500.
7306558500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306558500
7306558500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306558500
7306558500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306558500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306558500
7306558500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306559000
7306558500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306558500
7306558500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306559000
7306559000: Event: system.cpu1.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 113 executed @ 7306559000
7306559000: Cache: system.cpu1.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=803cd4d18f5500006374696f6e577261707065642031323835207363686564756c6564204020373330363535323530300a0052cd8f55000090dbe9cd8f550000 ptr=0x558fd070f980
7306559000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[4] packet ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500007565206c696d69742033322c206375720050aad38f5500006520312c20656e7472696573206e656564656420310a00000000000000000000 ptr=0x558fd070f280
7306559000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[4] packet ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500007565206c696d69742033322c206375720050aad38f5500006520312c20656e7472696573206e656564656420310a00000000000000000000 ptr=0x558fd070f280
7306559000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[4] packet ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500007565206c696d69742033322c206375720050aad38f5500006520312c20656e7472696573206e656564656420310a00000000000000000000 ptr=0x558fd070f280 SF size: 0 lat: 0
7306559000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500007565206c696d69742033322c206375720050aad38f5500006520312c20656e7472696573206e656564656420310a00000000000000000000 ptr=0x558fd070f280
7306559000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500007565206c696d69742033322c206375720050aad38f5500006520312c20656e7472696573206e656564656420310a00000000000000000000 ptr=0x558fd070f280
7306559000: CachePort: system.l2.mem_side: Scheduling send event at 7306569500
7306559000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306559500
7306559000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306559000 to 7306559500
7306559000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306559000
7306559000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306559500
7306559000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306559000
7306559000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306559500
7306559250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306559250
7306559250: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400 BUSY
7306559500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306559500
7306559500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306559500
7306559500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306560000
7306559500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306559500
7306559500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306560000
7306560000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306560000
7306560000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306560000
7306560000: Cache: system.l2: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802500
7306560000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802500
7306560000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306560000
7306560000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f480
7306560000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[28] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f480
7306560000: Event: system.tol2bus.slave[28]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1343 scheduled @ 7306560500
7306560000: Event: system.tol2bus.respLayer28.wrapped_function_event: EventFunctionWrapped 1344 scheduled @ 7306561500
7306560000: BaseXBar: system.tol2bus.respLayer28: The crossbar layer is now busy from tick 7306560000 to 7306561500
7306560000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306565000
7306560000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306560000
7306560000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306560500
7306560000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306560000
7306560000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306560500
7306560500: Event: system.tol2bus.slave[28]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1343 executed @ 7306560500
7306560500: Cache: system.cpu7.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f480
7306560500: Event: system.cpu7.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 381 scheduled @ 7306562500
7306560500: CacheVerbose: system.cpu7.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f480
7306560500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306560500
7306560500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306561000
7306560500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306560500
7306560500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306561000
7306560750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306560750
7306560750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306560750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 1
7306560750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306560750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802a00
7306560750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306577250
7306561000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306561000
7306561000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306561500
7306561000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306561000
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306561000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306561500
7306561500: Event: system.tol2bus.respLayer28.wrapped_function_event: EventFunctionWrapped 1344 executed @ 7306561500
7306561500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306561500
7306561500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306562000
7306561500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306561500
7306561500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306562000
7306562000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306562000
7306562000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306562500
7306562000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306562000
7306562000: Cache: system.cpu1.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306562000: CachePort: system.cpu1.dcache.mem_side: Scheduling send event at 7306563000
7306562000: Event: system.cpu1.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 100 scheduled @ 7306563000
7306562000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306562500
7306562500: Event: system.cpu7.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 381 executed @ 7306562500
7306562500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306562500
7306562500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306562500
7306562500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=4097d6d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363535323030300a001fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00
7306562500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c0cf82c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802800
7306562500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c0cf82c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802800
7306562500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c0cf82c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802800 SF size: 0 lat: 1
7306562500: CoherentXBar: system.membus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=c0cf82c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802800
7306562500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x80737180 size 64
7306562500: DRAM: system.mem_ctrls: Read queue limit 32, current size 1, entries needed 1
7306562500: DRAM: system.mem_ctrls: Address: 0x737180 Rank 1 Bank 3 Row 57
7306562500: DRAM: system.mem_ctrls: Read queue limit 32, current size 1, entries needed 1
7306562500: DRAM: system.mem_ctrls: Adding to read queue
7306562500: DRAM: system.mem_ctrls: Request scheduled immediately
7306562500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306562500
7306562500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306564000
7306562500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306562500 to 7306564000
7306562500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306569500
7306562500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306562500
7306562500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306562500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306562500: DRAM: system.mem_ctrls: Timing access to addr 0x737180, rank/bank/row 1 3 57
7306562500: DRAM: system.mem_ctrls: Removing burstTick for 7306555000
7306562500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306563500
7306562500: DRAM: system.mem_ctrls: Access to 0x737180, ready at 7306582250 next burst at 7306568500.
7306562500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306562500
7306562500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306562500
7306562500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306562500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306562500
7306562500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306563000
7306562500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306562500
7306562500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306563000
7306562500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306562500
7306562500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306563000
7306563000: Event: system.cpu1.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 100 executed @ 7306563000
7306563000: Cache: system.cpu1.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306563000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[5] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306563000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[5] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306563000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[5] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480 SF size: 0 lat: 0
7306563000: CoherentXBar: system.tol2bus: forwardTiming for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306563000: Cache: system.l2: access for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306563000: Cache: system.l2: Create CleanEvict CleanEvict [80a70800:80a7083f] D= ptr=0x558fc9802500
7306563000: CoherentXBar: system.tol2bus: recvTimingSnoopReq: src system.tol2bus.master[0] packet CleanEvict [80a70800:80a7083f] ES D= ptr=0x7ffdd53f73a0
7306563000: SnoopFilter: system.tol2bus.snoop_filter: lookupSnoop: packet CleanEvict [80a70800:80a7083f] ES D= ptr=0x7ffdd53f73a0
7306563000: CoherentXBar: system.tol2bus: recvTimingSnoopReq: src system.tol2bus.master[0] packet CleanEvict [80a70800:80a7083f] ES D= ptr=0x7ffdd53f73a0 SF size: 0 lat: 0
7306563000: CoherentXBar: system.tol2bus: forwardTiming for CleanEvict [80a70800:80a7083f] ES D= ptr=0x7ffdd53f73a0
7306563000: CachePort: system.l2.mem_side: Scheduling send event at 7306583000
7306563000: Cache: system.l2: Potential to merge writeback WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306563000: CachePort: system.l2.mem_side: Scheduling send event at 7306573500
7306563000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306564000
7306563000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306563000 to 7306564000
7306563000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306563000
7306563000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400
7306563000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400
7306563000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306565000
7306563000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306568000
7306563000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306563000 to 7306568000
7306563000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306563750
7306563000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306563000
7306563000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306563500
7306563000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306563000
7306563000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306563500
7306563000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306563000
7306563000: Cache: system.cpu7.icache: access for ReadReq [807371c0:807371ff] IF UC D=4008d1d18f5500006374696f6e577261707065642031323835206578656375746564204020373330363534383530300a0000eac88f5500000400805207038052 ptr=0x558fc9802480
7306563000: CachePort: system.cpu7.icache.mem_side: Scheduling send event at 7306564000
7306563000: Event: system.cpu7.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 383 scheduled @ 7306564000
7306563000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306563500
7306563500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306563500
7306563500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306564000
7306563500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306563500
7306563500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306564000
7306563500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306563500
7306563500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306564000
7306563750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306563750
7306563750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f800 BUSY
7306564000: Event: system.cpu7.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 383 executed @ 7306564000
7306564000: Cache: system.cpu7.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=4008d1d18f5500006374696f6e577261707065642031323835206578656375746564204020373330363534383530300a0000eac88f5500000400805207038052 ptr=0x558fc9802480
7306564000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[28] packet ReadReq [807371c0:807371ff] IF UC D=800880c98f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363536343030300a00bbeac88f5500000000000000000000 ptr=0x558fc9802200 BUSY
7306564000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306564000
7306564000: Cache: system.cpu7.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=4008d1d18f5500006374696f6e577261707065642031323835206578656375746564204020373330363534383530300a0000eac88f5500000400805207038052 ptr=0x558fc9802480
7306564000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[28] packet ReadReq [807371c0:807371ff] IF UC D=800880c98f5500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e740000bbeac88f5500000000000000000000 ptr=0x558fc9802200
7306564000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[28] packet ReadReq [807371c0:807371ff] IF UC D=800880c98f5500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e740000bbeac88f5500000000000000000000 ptr=0x558fc9802200
7306564000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[28] packet ReadReq [807371c0:807371ff] IF UC D=800880c98f5500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e740000bbeac88f5500000000000000000000 ptr=0x558fc9802200 SF size: 0 lat: 0
7306564000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=800880c98f5500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e740000bbeac88f5500000000000000000000 ptr=0x558fc9802200
7306564000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=800880c98f5500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e740000bbeac88f5500000000000000000000 ptr=0x558fc9802200
7306564000: CachePort: system.l2.mem_side: Scheduling send event at 7306574500
7306564000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306564500
7306564000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306564000 to 7306564500
7306564000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306564000
7306564000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306564000
7306564000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306564500
7306564000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306564000
7306564000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306564500
7306564000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306564000
7306564000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306564500
7306564500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306564500
7306564500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306564500
7306564500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306565000
7306564500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306564500
7306564500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306565000
7306564500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306564500
7306564500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306565000
7306565000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306565000
7306565000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400
7306565000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400
7306565000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306565000
7306565000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadExResp [8000ffc0:8000ffff] D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9824100
7306565000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[1] packet ReadExResp [8000ffc0:8000ffff] D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9824100
7306565000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse:   old SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306565000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306565000: Event: system.tol2bus.slave[1]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1289 scheduled @ 7306565500
7306565000: Event: system.tol2bus.respLayer1.wrapped_function_event: EventFunctionWrapped 1290 scheduled @ 7306566500
7306565000: BaseXBar: system.tol2bus.respLayer1: The crossbar layer is now busy from tick 7306565000 to 7306566500
7306565000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306574000
7306565000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306565000
7306565000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306565500
7306565000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306565000
7306565000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306565500
7306565000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306565000
7306565000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306565500
7306565500: Event: system.tol2bus.slave[1]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1289 executed @ 7306565500
7306565500: Cache: system.cpu0.dcache: recvTimingResp: Handling response ReadExResp [8000ffc0:8000ffff] D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9824100
7306565500: Cache: system.cpu0.dcache: Block for addr 0x8000ffc0 being updated in Cache
7306565500: CacheRepl: system.cpu0.dcache: Replacement victim: state: 0 (I) valid: 0 writable: 0 readable: 0 dirty: 0 | tag: 0xffffffffffffffff set: 0x1ff way: 0
7306565500: Cache: system.cpu0.dcache: Block addr 0x8000ffc0 (ns) moving from state 0 (I) to state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x10001 set: 0x1ff way: 0
7306565500: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8000fff8:8000ffff] D=a071738000000000 ptr=0x558fc9802600 (write)
7306565500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306566500
7306565500: CacheVerbose: system.cpu0.dcache: recvTimingResp: Leaving with ReadExResp [8000ffc0:8000ffff] D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9824100
7306565500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306565500
7306565500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306566000
7306565500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306565500
7306565500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306566000
7306565500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306565500
7306565500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306566000
7306566000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306566000
7306566000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306566500
7306566000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306566000
7306566000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306566500
7306566000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306566000
7306566000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306566500
7306566500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306566500
7306566500: Event: system.tol2bus.respLayer1.wrapped_function_event: EventFunctionWrapped 1290 executed @ 7306566500
7306566500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306566500
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306566500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306567000
7306566500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306566500
7306566500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306567000
7306566500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306566500
7306566500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306567000
7306567000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306567000
7306567000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306567500
7306567000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306567000
7306567000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306567500
7306567000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306567000
7306567000: Cache: system.cpu7.icache: access for ReadReq [80737180:807371bf] IF UC D=40db82c98f5500006374696f6e577261707065642031313180f602d28f5500006564204020373330363535323530300a0000656e740000000400805207038052 ptr=0x558fc9802600
7306567000: CachePort: system.cpu7.icache.mem_side: Scheduling send event at 7306568000
7306567000: Event: system.cpu7.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 383 scheduled @ 7306568000
7306567000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306567500
7306567500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306567500
7306567500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306568000
7306567500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306567500
7306567500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306568000
7306567500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306567500
7306567500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306568000
7306568000: Event: system.cpu7.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 383 executed @ 7306568000
7306568000: Cache: system.cpu7.icache: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=40db82c98f5500006374696f6e577261707065642031313180f602d28f5500006564204020373330363535323530300a0000656e740000000400805207038052 ptr=0x558fc9802600
7306568000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[28] packet ReadReq [80737180:807371bf] IF UC D=c00f80c98f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363536383030300a00656420310a000030663438300000d0 ptr=0x558fc9824100
7306568000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[28] packet ReadReq [80737180:807371bf] IF UC D=c00f80c98f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363536383030300a00656420310a000030663438300000d0 ptr=0x558fc9824100
7306568000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[28] packet ReadReq [80737180:807371bf] IF UC D=c00f80c98f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363536383030300a00656420310a000030663438300000d0 ptr=0x558fc9824100 SF size: 0 lat: 0
7306568000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=c00f80c98f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363536383030300a00656420310a000030663438300000d0 ptr=0x558fc9824100
7306568000: Cache: system.l2: access for ReadReq [80737180:807371bf] IF UC D=c00f80c98f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363536383030300a00656420310a000030663438300000d0 ptr=0x558fc9824100
7306568000: CachePort: system.l2.mem_side: Scheduling send event at 7306578500
7306568000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306568500
7306568000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306568000 to 7306568500
7306568000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306568000
7306568000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f800
7306568000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f800
7306568000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306570000
7306568000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306573000
7306568000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306568000 to 7306573000
7306568000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306569250
7306568000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306568000
7306568000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306568500
7306568000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306568000
7306568000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306568500
7306568000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306568000
7306568000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306568500
7306568500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306568500
7306568500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306568500
7306568500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306569000
7306568500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306568500
7306568500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306569000
7306568500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306568500
7306568500: Cache: system.cpu0.icache: access for ReadReq [80993f80:80993fbf] IF D=c094d6d18f5500006374696f6e5772617070656420343232403d03d28f5500006564204020373330363536393530300a00000000000000000000000000000000 ptr=0x558fc9802400 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20264 set: 0xfe way: 0
7306568500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306569500
7306568500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306569000
7306569000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306569000
7306569000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306569500
7306569000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306569000
7306569000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306569500
7306569000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306569000
7306569000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306569500
7306569250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306569250
7306569250: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824080 BUSY
7306569500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306569500
7306569500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306569500
7306569500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500007565206c696d69742033322c206375720050aad38f5500006520312c20656e7472696573206e656564656420310a00000000000000000000 ptr=0x558fd070f280
7306569500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=809ad6d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802400
7306569500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=809ad6d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802400
7306569500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=809ad6d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802400 SF size: 0 lat: 1
7306569500: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=809ad6d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802400
7306569500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306569500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306569500: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306569500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306569500: DRAM: system.mem_ctrls: Adding to read queue
7306569500: DRAM: system.mem_ctrls: Request scheduled immediately
7306569500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306569500
7306569500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306571000
7306569500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306569500 to 7306571000
7306569500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306573500
7306569500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306569500
7306569500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306569500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306569500: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306569500: DRAM: system.mem_ctrls: Removing burstTick for 7306560000
7306569500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306569500
7306569500: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306588250 next burst at 7306574500.
7306569500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306569500
7306569500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306569500
7306569500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306569500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306569500
7306569500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306570000
7306569500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306569500
7306569500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306570000
7306569500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306569500
7306569500: Cache: system.cpu0.icache: access for ReadReq [80714980:807149bf] IF D=8089d6d18f5500006374696f6e577261707065642031323930206578656375746564204020373330363536363530300a0000000000000000a071738000000000 ptr=0x558fd070f580 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x201c5 set: 0x26 way: 0x1
7306569500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306570500
7306518500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area    :   mrs   x3, ctr_el0        : IntAlu :  D=0x000000008444c004  FetchSeq=13255188  CPSeq=11776681  flags=(IsInteger|IsSerializeBefore)
7306518500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+4    :   nop                      : IntAlu :   FetchSeq=13255189  CPSeq=11776681  flags=(IsNop)
7306569500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306570000
7306570000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306570000
7306570000: Cache: system.l2: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f800
7306570000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f800
7306570000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306570000
7306518500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+8    :   ubfm   x3, x3, #16, #19  : IntAlu :  D=0x0000000000000004  FetchSeq=13255190  CPSeq=11776682  flags=(IsInteger)
7306518500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+12    :   movz   x2, #4, #0        : IntAlu :  D=0x0000000000000004  FetchSeq=13255191  CPSeq=11776683  flags=(IsInteger)
7306570000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306570500
7306570000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306570000
7306570000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306570500
7306570000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306570000
7306570000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306570500
7306570500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306570500
7306570500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306570500
7306570500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306571000
7306570500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306570500
7306570500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306571000
7306570500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306570500
7306518500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+16    :   lslv   x2, x2, x3        : IntAlu :  D=0x0000000000000040  FetchSeq=13255192  CPSeq=11776684  flags=(IsInteger)
7306518500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+20    :   add   x1, x0, x1         : IntAlu :  D=0xffffffc000010000  FetchSeq=13255193  CPSeq=11776685  flags=(IsInteger)
7306570500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306571000
7306571000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306571000
7306571000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306571000
7306571000: Cache: system.cpu0.icache: access for ReadReq [803378c0:803378ff] IF D=c032d4d18f5500000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f580 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x200cd set: 0xe3 way: 0
7306571000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306572000
7306518500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+24    :   sub   x3, x2, #1         : IntAlu :  D=0x000000000000003f  FetchSeq=13255194  CPSeq=11776686  flags=(IsInteger)
7306571000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306571500
7306571000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306571000
7306571000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306571500
7306571000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306571000
7306571000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306571500
7306571500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306571500
7306571500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306572000
7306571500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306571500
7306571500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306572000
7306571500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306571500
7306518500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+28    :   bic   x0, x0, x3         : IntAlu :  D=0xffffffc00000ffc0  FetchSeq=13255195  CPSeq=11776687  flags=(IsInteger)
7306571500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306572000
7306572000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306572000
7306572000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306572000
7306519500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+32    :   dc civac   , x0          : MemWrite :  A=0xffffffc00000ffc0  FetchSeq=13255196  CPSeq=11776688  flags=(IsInteger|IsMemRef|IsStore)
7306519500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+36    :   add   x0, x0, x2         : IntAlu :  D=0xffffffc000010000  FetchSeq=13255197  CPSeq=11776689  flags=(IsInteger)
7306572000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306572500
7306572000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306572000
7306572000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306572500
7306572000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306572000
7306572000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306572500
7306572500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306572500
7306572500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306572500
7306572500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306573000
7306572500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306572500
7306519500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+40    :   subs   x0, x1            : IntAlu :  D=0x0000000000000001  FetchSeq=13255198  CPSeq=11776690  flags=(IsInteger)
7306572500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306573000
7306573000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306573000
7306573000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824080
7306573000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824080
7306573000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306575000
7306573000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306578000
7306573000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306573000 to 7306578000
7306573000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306573750
7306573000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306573000
7306573000: Cache: system.cpu0.dcache: access for CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f580 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x10001 set: 0x1ff way: 0
7306573000: CachePort: system.cpu0.dcache.mem_side: Scheduling send event at 7306574000
7306573000: Event: system.cpu0.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 55 scheduled @ 7306574000
7306519500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+44    :   b.cc   <__flush_dcache_area+32> : IntAlu :   FetchSeq=13255199  CPSeq=11776691  flags=(IsControl|IsDirectControl|IsCondControl)
7306573000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306573500
7306573000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306573000
7306573000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306573500
7306573500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306573500
7306573500: Cache: system.l2: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306573500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306573500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306573500: SnoopFilter: system.membus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306573500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480 SF size: 0 lat: 1
7306573500: CoherentXBar: system.membus: forwardTiming for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306573500: DRAM: system.mem_ctrls: recvTimingReq: request WriteReq addr 0x80a70800 size 4
7306573500: DRAM: system.mem_ctrls: Write queue limit 64, current size 25, entries needed 1
7306573500: DRAM: system.mem_ctrls: Address: 0xa70800 Rank 1 Bank 0 Row 83
7306573500: DRAM: system.mem_ctrls: Adding to write queue
7306573500: DRAM: system.mem_ctrls: Responding to Address 0x80a70800
7306573500: DRAM: system.mem_ctrls: Done: WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306573500: DRAM: system.mem_ctrls: Request scheduled immediately
7306573500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306573500
7306573500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306576000
7306573500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306573500 to 7306576000
7306573500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306574500
7306573500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306573500
7306573500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306573500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306573500
7306573500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306574000
7306573500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306573500
7306573500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306574000
7306573750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306573750
7306573750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070ff80 BUSY
7306574000: Event: system.cpu0.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 55 executed @ 7306574000
7306574000: Cache: system.cpu0.dcache: sendMSHRQueuePacket: MSHR CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f580
7306574000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[1] packet CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800
7306574000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[1] packet CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800
7306574000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306574000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306574000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[1] packet CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800 SF size: 0 lat: 0
7306574000: CoherentXBar: system.tol2bus: forwardTiming for CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800
7306574000: Cache: system.l2: access for CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x2000 set: 0x3ff way: 0x1
7306574000: CachePort: system.l2.mem_side: Scheduling send event at 7306584500
7306574000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306574500
7306574000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306574000 to 7306574500
7306574000: CacheVerbose: system.cpu0.dcache: sendMSHRQueuePacket: packet CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800 found block: state: b (M) valid: 1 writable: 1 readable: 0 dirty: 1 | tag: 0x10001 set: 0x1ff way: 0
7306574000: Cache: system.cpu0.dcache: Create WriteClean [8000ffc0:8000ffff] PoC D= ptr=0x558fc9802c00 writable: 1, dirty: 1
7306574000: CachePort: system.cpu0.dcache.mem_side: Scheduling send event at 0
7306574000: Event: system.cpu0.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 55 scheduled @ 7306574001
7306574000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306574000
7306574000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802d00
7306574000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[8] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802d00
7306574000: Event: system.tol2bus.slave[8]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1303 scheduled @ 7306574500
7306574000: Event: system.tol2bus.respLayer8.wrapped_function_event: EventFunctionWrapped 1304 scheduled @ 7306575500
7306574000: BaseXBar: system.tol2bus.respLayer8: The crossbar layer is now busy from tick 7306574000 to 7306575500
7306574000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306579000
7306574000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306574000
7306574000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306574500
7306574000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306574000
7306574000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306574500
7306574001: Event: system.cpu0.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 55 executed @ 7306574001
7306574001: Cache: system.cpu0.dcache: sendWriteQueuePacket: write WriteClean [8000ffc0:8000ffff] PoC D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9802c00
7306574001: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[1] packet WriteClean [8000ffc0:8000ffff] PoC D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9802c00 BUSY
7306574500: Event: system.tol2bus.slave[8]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1303 executed @ 7306574500
7306574500: Cache: system.cpu2.icache: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802d00
7306574500: Event: system.cpu2.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 156 scheduled @ 7306576500
7306574500: CacheVerbose: system.cpu2.icache: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802d00
7306574500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306574500
7306574500: Cache: system.cpu0.dcache: sendWriteQueuePacket: write WriteClean [8000ffc0:8000ffff] PoC D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9802c00
7306574500: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[1] packet WriteClean [8000ffc0:8000ffff] PoC D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9802c00
7306574500: Cache: system.l2: access for WriteClean [8000ffc0:8000ffff] PoC D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9802c00 hit state: 3 (E) valid: 1 writable: 1 readable: 0 dirty: 0 | tag: 0x2000 set: 0x3ff way: 0x1
7306574500: Cache: system.l2: access new state is state: 3 (E) valid: 1 writable: 1 readable: 0 dirty: 0 | tag: 0x2000 set: 0x3ff way: 0x1
7306574500: CachePort: system.l2.mem_side: Scheduling send event at 7306585000
7306574500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306576000
7306574500: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306574500 to 7306576000
7306574500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306574500
7306574500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=800880c98f5500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e740000bbeac88f5500000000000000000000 ptr=0x558fc9802200
7306574500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=401b80c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802d00 BUSY
7306574500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306574500
7306574500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306575000
7306574500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306574500
7306574500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306575000
7306575000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306575000
7306575000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824080
7306575000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824080
7306575000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306575000
7306575000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306575500
7306575000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306575000
7306575000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306575500
7306575500: Event: system.tol2bus.respLayer8.wrapped_function_event: EventFunctionWrapped 1304 executed @ 7306575500
7306575500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306575500
7306575500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306576000
7306575500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306575500
7306575500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306576000
7306576000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306576000
7306576000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306576000
7306576000: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=800880c98f5500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e740000bbeac88f5500000000000000000000 ptr=0x558fc9802200
7306576000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=0033d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9824080
7306576000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=0033d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9824080
7306576000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=0033d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9824080 SF size: 0 lat: 1
7306576000: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=0033d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9824080
7306576000: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306576000: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306576000: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306576000: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306576000: DRAM: system.mem_ctrls: Adding to read queue
7306576000: DRAM: system.mem_ctrls: Request scheduled immediately
7306576000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306576000
7306576000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306577000
7306576000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306576000 to 7306577000
7306576000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306578500
7306576000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306576000
7306576000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306576000: DRAM: system.mem_ctrls: Single request, going to a free rank
7306576000: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306576000: DRAM: system.mem_ctrls: Removing burstTick for 7306565000
7306576000: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306576000
7306576000: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306594750 next burst at 7306581000.
7306576000: DRAM: system.mem_ctrls: Precharging bank 3, rank 1 at tick 7306583500, now got 4 active
7306576000: Event: system.mem_ctrls_1.wrapped_function_event: EventFunctionWrapped 20 scheduled @ 7306597250
7306576000: DRAM: system.mem_ctrls: Auto-precharged bank: 11
7306576000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306576000
7306576000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306576000
7306576000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306576000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306576000
7306576000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306576500
7306576000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306576000
7306576000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306576500
7306576500: Event: system.cpu2.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 156 executed @ 7306576500
7306576500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306576500
7306576500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306577000
7306576500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306576500
7306576500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306577000
7306577000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306577000
7306577000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306577000
7306577000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306577500
7306577000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306577000
7306577000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306577500
7306577250: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306577250
7306577250: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306577250: DRAM: system.mem_ctrls: number of read entries for rank 1 is 3
7306577250: DRAM: system.mem_ctrls: Responding to Address 0x807371c0
7306577250: DRAM: system.mem_ctrls: Done: ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802b80
7306577250: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306582250
7306577500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306577500
7306577500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306578000
7306577500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306577500
7306577500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306578000
7306578000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306578000
7306578000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070ff80
7306578000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070ff80
7306578000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306580000
7306578000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306583000
7306578000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306578000 to 7306583000
7306578000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306579250
7306578000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306578000
7306578000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306578500
7306578000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306578000
7306578000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306578500
7306578500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306578500
7306578500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=c00f80c98f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363536383030300a00656420310a000030663438300000d0 ptr=0x558fc9824100
7306578500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=0033d4d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070f880
7306578500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=0033d4d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070f880
7306578500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=0033d4d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070f880 SF size: 0 lat: 1
7306578500: CoherentXBar: system.membus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=0033d4d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070f880
7306578500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x80737180 size 64
7306578500: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306578500: DRAM: system.mem_ctrls: Address: 0x737180 Rank 1 Bank 3 Row 57
7306578500: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306578500: DRAM: system.mem_ctrls: Adding to read queue
7306578500: DRAM: system.mem_ctrls: Request scheduled immediately
7306578500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306578500
7306578500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306580000
7306578500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306578500 to 7306580000
7306578500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306583000
7306578500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306578500
7306578500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306578500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306578500: DRAM: system.mem_ctrls: Timing access to addr 0x737180, rank/bank/row 1 3 57
7306578500: DRAM: system.mem_ctrls: Removing burstTick for 7306575000
7306578500: DRAM: system.mem_ctrls: Activate at tick 7306597250
7306578500: DRAM: system.mem_ctrls: Activate bank 3, rank 1 at tick 7306597250, now got 5 active
7306578500: Event: system.mem_ctrls_1.wrapped_function_event: EventFunctionWrapped 19 scheduled @ 7306597250
7306578500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306611000
7306578500: DRAM: system.mem_ctrls: Access to 0x737180, ready at 7306629750 next burst at 7306616000.
7306578500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306588500
7306578500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306578500
7306578500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306579000
7306578500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306578500
7306578500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306579000
7306579000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306579000
7306579000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600
7306579000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[8] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600
7306579000: Event: system.tol2bus.slave[8]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1303 scheduled @ 7306579500
7306579000: Event: system.tol2bus.respLayer8.wrapped_function_event: EventFunctionWrapped 1304 scheduled @ 7306580500
7306579000: BaseXBar: system.tol2bus.respLayer8: The crossbar layer is now busy from tick 7306579000 to 7306580500
7306579000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306584000
7306579000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306579000
7306579000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306579500
7306579000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306579000
7306579000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306579500
7306579250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306579250
7306579250: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fc80 BUSY
7306579500: Event: system.tol2bus.slave[8]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1303 executed @ 7306579500
7306579500: Cache: system.cpu2.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600
7306579500: Event: system.cpu2.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 156 scheduled @ 7306581500
7306579500: CacheVerbose: system.cpu2.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600
7306579500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306579500
7306579500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306580000
7306579500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306579500
7306579500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306580000
7306580000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306580000
7306580000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306580000
7306580000: Cache: system.l2: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070ff80
7306580000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070ff80
7306580000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306580000
7306580000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306580500
7306580000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306580000
7306580000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306580500
7306580500: Event: system.tol2bus.respLayer8.wrapped_function_event: EventFunctionWrapped 1304 executed @ 7306580500
7306580500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306580500
7306580500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306581000
7306580500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306580500
7306580500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306581000
7306581000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306581000
7306581000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306581500
7306581000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306581000
7306581000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306581500
7306581500: Event: system.cpu2.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 156 executed @ 7306581500
7306581500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306581500
7306581500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306581500
7306581500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306582000
7306581500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306581500
7306581500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306582000
7306581500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306581500
7306581500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306582000
7306582000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306582000
7306582000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306582500
7306582000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306582000
7306582000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306582500
7306582000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306582000
7306582000: Cache: system.cpu2.icache: access for ReadReq [807371c0:807371ff] IF UC D=c02dd4d18f5500006374696f6e5772617070656420313536207363686564756c6564204020373330363537363530300a0000eac88f55000060ded1d18f550000 ptr=0x558fc9802b00
7306582000: CachePort: system.cpu2.icache.mem_side: Scheduling send event at 7306583000
7306582000: Event: system.cpu2.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 158 scheduled @ 7306583000
7306582000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306582500
7306582250: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306582250
7306582250: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306582250: DRAM: system.mem_ctrls: number of read entries for rank 1 is 3
7306582250: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306582250: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802800
7306582250: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306588250
7306582500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306582500
7306582500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306583000
7306582500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306582500
7306582500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306583000
7306582500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306582500
7306582500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306583000
7306583000: Event: system.cpu2.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 158 executed @ 7306583000
7306583000: Cache: system.cpu2.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c02dd4d18f5500006374696f6e5772617070656420313536207363686564756c6564204020373330363537363530300a0000eac88f55000060ded1d18f550000 ptr=0x558fc9802b00
7306583000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[8] packet ReadReq [807371c0:807371ff] IF UC D=80b7acd38f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363538333030300a006561647954696d650a000000000000 ptr=0x558fd070ff80
7306583000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[8] packet ReadReq [807371c0:807371ff] IF UC D=80b7acd38f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363538333030300a006561647954696d650a000000000000 ptr=0x558fd070ff80
7306583000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[8] packet ReadReq [807371c0:807371ff] IF UC D=80b7acd38f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363538333030300a006561647954696d650a000000000000 ptr=0x558fd070ff80 SF size: 0 lat: 0
7306583000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=80b7acd38f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363538333030300a006561647954696d650a000000000000 ptr=0x558fd070ff80
7306583000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=80b7acd38f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363538333030300a006561647954696d650a000000000000 ptr=0x558fd070ff80
7306583000: CachePort: system.l2.mem_side: Scheduling send event at 7306593500
7306583000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306583500
7306583000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306583000 to 7306583500
7306583000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306583000
7306583000: Cache: system.l2: sendWriteQueuePacket: write CleanEvict [80a70800:80a7083f] D= ptr=0x558fc9802500
7306583000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet CleanEvict [80a70800:80a7083f] D= ptr=0x558fc9802500
7306583000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet CleanEvict [80a70800:80a7083f] D= ptr=0x558fc9802500
7306583000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306583000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306583000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet CleanEvict [80a70800:80a7083f] D= ptr=0x558fc9802500 SF size: 0 lat: 1
7306583000: CoherentXBar: system.membus: recvTimingReq: Not forwarding CleanEvict [80a70800:80a7083f] D= ptr=0x558fc9802500
7306583000: SnoopFilter: system.membus.snoop_filter: eraseIfNullEntry:   Removed SF entry.
7306583000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306584000
7306583000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306583000 to 7306584000
7306583000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306584500
7306583000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306583000
7306583000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fc80
7306583000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fc80
7306583000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306585000
7306583000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306588000
7306583000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306583000 to 7306588000
7306583000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306584250
7306583000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306583000
7306583000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306583500
7306583000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306583000
7306583000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306583500
7306583000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306583000
7306583000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306583500
7306583500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306583500
7306583500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306583500
7306583500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306584000
7306583500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306583500
7306583500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306584000
7306583500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306583500
7306583500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306584000
7306584000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306584000
7306584000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306584000
7306584000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9824180
7306584000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[12] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9824180
7306584000: Event: system.tol2bus.slave[12]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1311 scheduled @ 7306584500
7306584000: Event: system.tol2bus.respLayer12.wrapped_function_event: EventFunctionWrapped 1312 scheduled @ 7306585500
7306584000: BaseXBar: system.tol2bus.respLayer12: The crossbar layer is now busy from tick 7306584000 to 7306585500
7306584000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306589000
7306584000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306584000
7306584000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306584500
7306584000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306584000
7306584000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306584500
7306584000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306584000
7306584000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306584500
7306584250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306584250
7306584250: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fe80 BUSY
7306584500: Event: system.tol2bus.slave[12]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1311 executed @ 7306584500
7306584500: Cache: system.cpu3.icache: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9824180
7306584500: Event: system.cpu3.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 201 scheduled @ 7306586500
7306584500: CacheVerbose: system.cpu3.icache: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9824180
7306584500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306584500
7306584500: Cache: system.l2: sendWriteQueuePacket: write WriteClean [8000ffc0:8000ffff] PoC D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9802c00
7306584500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WriteClean [8000ffc0:8000ffff] PoC D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9802c00
7306584500: DRAM: system.mem_ctrls: recvTimingReq: request WriteClean addr 0x8000ffc0 size 64
7306584500: DRAM: system.mem_ctrls: Write queue limit 64, current size 26, entries needed 1
7306584500: DRAM: system.mem_ctrls: Merging write burst with existing queue entry
7306584500: DRAM: system.mem_ctrls: Responding to Address 0x8000ffc0
7306584500: DRAM: system.mem_ctrls: Done: WriteClean [8000ffc0:8000ffff] PoC D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9802c00
7306584500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306590000
7306584500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306584500 to 7306590000
7306584500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306584501
7306584500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306584500
7306584500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306585000
7306584500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306584500
7306584500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306585000
7306584500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306584500
7306584500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306585000
7306584501: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306584501
7306584501: Cache: system.l2: sendMSHRQueuePacket: MSHR CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800
7306584501: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f300 BUSY
7306585000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306585000
7306585000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fc80
7306585000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fc80
7306585000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306585000
7306585000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306585500
7306585000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306585000
7306585000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306585500
7306585000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306585000
7306581500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306585000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306585500
7306585500: Event: system.tol2bus.respLayer12.wrapped_function_event: EventFunctionWrapped 1312 executed @ 7306585500
7306585500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306585500
7306585500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306586000
7306585500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306585500
7306585500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306586000
7306585500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306585500
7306585500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306586000
7306586000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306586000
7306586000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306586500
7306586000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306586000
7306586000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306586500
7306586000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306586000
7306586000: Cache: system.cpu2.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306586000: CachePort: system.cpu2.dcache.mem_side: Scheduling send event at 7306587000
7306586000: Event: system.cpu2.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 145 scheduled @ 7306587000
7306586000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306586500
7306586500: Event: system.cpu3.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 201 executed @ 7306586500
7306586500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306586500
7306586500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306587000
7306586500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306586500
7306586500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306587000
7306586500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306586500
7306586500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306587000
7306587000: Event: system.cpu2.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 145 executed @ 7306587000
7306587000: Cache: system.cpu2.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306587000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[9] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306587000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[9] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306587000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[9] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80 SF size: 0 lat: 0
7306587000: CoherentXBar: system.tol2bus: forwardTiming for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306587000: Cache: system.l2: access for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306587000: CachePort: system.l2.mem_side: Scheduling send event at 7306597500
7306587000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306588000
7306587000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306587000 to 7306588000
7306587000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306587000
7306587000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306587500
7306587000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306587000
7306587000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306587500
7306587000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306587000
7306587000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306587500
7306587500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306587500
7306587500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306588000
7306587500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306587500
7306587500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306588000
7306587500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306587500
7306587500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306588000
7306588000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306588000
7306588000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306588000
7306588000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fe80
7306588000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fe80
7306588000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306590000
7306588000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306593000
7306588000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306588000 to 7306593000
7306588000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306589250
7306588000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306588000
7306588000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306588500
7306588000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306588000
7306588000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306588500
7306588000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306588000
7306588000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306588500
7306588250: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306588250
7306588250: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306588250: DRAM: system.mem_ctrls: number of read entries for rank 1 is 2
7306588250: DRAM: system.mem_ctrls: Responding to Address 0x807371c0
7306588250: DRAM: system.mem_ctrls: Done: ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802400
7306588250: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306594750
7306588500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306588500
7306588500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306588500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306588500
7306588500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306589000
7306588500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306588500
7306588500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306589000
7306588500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306588500
7306588500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306589000
7306589000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306589000
7306589000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc8fb7f80
7306589000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[12] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc8fb7f80
7306589000: Event: system.tol2bus.slave[12]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1311 scheduled @ 7306589500
7306589000: Event: system.tol2bus.respLayer12.wrapped_function_event: EventFunctionWrapped 1312 scheduled @ 7306590500
7306589000: BaseXBar: system.tol2bus.respLayer12: The crossbar layer is now busy from tick 7306589000 to 7306590500
7306589000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306594000
7306589000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306589000
7306589000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306589500
7306589000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306589000
7306589000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306589500
7306589000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306589000
7306589000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306589500
7306589250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306589250
7306589250: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802a00 BUSY
7306589500: Event: system.tol2bus.slave[12]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1311 executed @ 7306589500
7306589500: Cache: system.cpu3.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc8fb7f80
7306589500: Event: system.cpu3.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 201 scheduled @ 7306591500
7306589500: CacheVerbose: system.cpu3.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc8fb7f80
7306589500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306589500
7306589500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306590000
7306589500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306589500
7306589500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306590000
7306589500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306589500
7306589500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306590000
7306590000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306590000
7306590000: Cache: system.l2: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fe80
7306590000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fe80
7306590000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306590000
7306590000: Cache: system.l2: sendMSHRQueuePacket: MSHR CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800
7306590000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fe80
7306590000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fe80
7306590000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306590000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306590000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fe80 SF size: 0 lat: 1
7306590000: CoherentXBar: system.membus: forwardTiming for CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fe80
7306590000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306591000
7306590000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306590000 to 7306591000
7306590000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet CleanInvalidResp [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fe80
7306590000: SnoopFilter: system.membus.snoop_filter: updateResponse:   old SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306590000: SnoopFilter: system.membus.snoop_filter: eraseIfNullEntry:   Removed SF entry.
7306590000: SnoopFilter: system.membus.snoop_filter: updateResponse:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306590000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306598000
7306590000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306593500
7306590000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306590000
7306590000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306590500
7306590000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306590000
7306590000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306590500
7306590000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306590000
7306590000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306590500
7306590500: Event: system.tol2bus.respLayer12.wrapped_function_event: EventFunctionWrapped 1312 executed @ 7306590500
7306590500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306590500
7306590500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306591000
7306590500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306590500
7306590500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306591000
7306590500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306590500
7306590500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306591000
7306591000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306591000
7306591000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306591000
7306591000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306591500
7306591000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306591000
7306591000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306591500
7306591000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306591000
7306591000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306591500
7306591500: Event: system.cpu3.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 201 executed @ 7306591500
7306591500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306591500
7306591500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306591500
7306591500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306592000
7306591500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306591500
7306591500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306592000
7306591500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306591500
7306591500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306592000
7306591500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306591500
7306591500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306592000
7306592000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306592000
7306592000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306592500
7306592000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306592000
7306592000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306592500
7306592000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306592000
7306592000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306592500
7306592000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306592000
7306592000: Cache: system.cpu3.icache: access for ReadReq [807371c0:807371ff] IF UC D=c046d2d18f550000d07a3fd5fd7f0000b85380b301000000a05780b3010000001800000000000000002980c98f5500000000000000010000a544865a467c0653 ptr=0x558fc8fb7c80
7306592000: CachePort: system.cpu3.icache.mem_side: Scheduling send event at 7306593000
7306592000: Event: system.cpu3.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 203 scheduled @ 7306593000
7306592000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306592500
7306592500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306592500
7306592500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306593000
7306592500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306592500
7306592500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306593000
7306592500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306592500
7306592500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306593000
7306592500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306592500
7306592500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306593000
7306593000: Event: system.cpu3.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 203 executed @ 7306593000
7306593000: Cache: system.cpu3.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c046d2d18f550000d07a3fd5fd7f0000b85380b301000000a05780b3010000001800000000000000002980c98f5500000000000000010000a544865a467c0653 ptr=0x558fc8fb7c80
7306593000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[12] packet ReadReq [807371c0:807371ff] IF UC D=4010d1d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363539333030300a0000c39a0100018b430400d10000238a ptr=0x558fc8fb7f80
7306593000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[12] packet ReadReq [807371c0:807371ff] IF UC D=4010d1d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363539333030300a0000c39a0100018b430400d10000238a ptr=0x558fc8fb7f80
7306593000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[12] packet ReadReq [807371c0:807371ff] IF UC D=4010d1d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363539333030300a0000c39a0100018b430400d10000238a ptr=0x558fc8fb7f80 SF size: 0 lat: 0
7306593000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=4010d1d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363539333030300a0000c39a0100018b430400d10000238a ptr=0x558fc8fb7f80
7306593000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=4010d1d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363539333030300a0000c39a0100018b430400d10000238a ptr=0x558fc8fb7f80
7306593000: CachePort: system.l2.mem_side: Scheduling send event at 7306603500
7306593000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306593500
7306593000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306593000 to 7306593500
7306593000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306593000
7306593000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802a00
7306593000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802a00
7306593000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 rescheduled @ 7306595000
7306593000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306598000
7306593000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306593000 to 7306598000
7306593000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306593001
7306593000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306593000
7306593000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306593500
7306593000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306593000
7306593000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306593500
7306593000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306593000
7306593000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306593500
7306593000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306593000
7306593000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306593500
7306593001: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306593001
7306593001: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480 BUSY
7306593500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306593500
7306593500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306593500
7306593500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=80b7acd38f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363538333030300a006561647954696d650a000000000000 ptr=0x558fd070ff80
7306593500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=40d882c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802900
7306593500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=40d882c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802900
7306593500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=40d882c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802900 SF size: 0 lat: 1
7306593500: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=40d882c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802900
7306593500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306593500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306593500: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306593500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306593500: DRAM: system.mem_ctrls: Adding to read queue
7306593500: DRAM: system.mem_ctrls: Request scheduled immediately
7306593500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306593500
7306593500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306595000
7306593500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306593500 to 7306595000
7306593500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306597500
7306593500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306593500
7306593500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306593500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306593500: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306593500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306616000
7306593500: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306634750 next burst at 7306621000.
7306593500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306593500
7306593500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306593500
7306593500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306593500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306593500
7306593500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306594000
7306593500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306593500
7306593500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306594000
7306593500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306593500
7306593500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306594000
7306593500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306593500
7306593500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306594000
7306594000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306594000
7306594000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802180
7306594000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[16] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802180
7306594000: Event: system.tol2bus.slave[16]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1319 scheduled @ 7306594500
7306594000: Event: system.tol2bus.respLayer16.wrapped_function_event: EventFunctionWrapped 1320 scheduled @ 7306595500
7306594000: BaseXBar: system.tol2bus.respLayer16: The crossbar layer is now busy from tick 7306594000 to 7306595500
7306594000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306599000
7306594000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306594000
7306594000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306594500
7306594000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306594000
7306594000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306594500
7306594000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306594000
7306594000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306594500
7306594000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306594000
7306594000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306594500
7306594500: Event: system.tol2bus.slave[16]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1319 executed @ 7306594500
7306594500: Cache: system.cpu4.icache: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802180
7306594500: Event: system.cpu4.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 246 scheduled @ 7306596500
7306594500: CacheVerbose: system.cpu4.icache: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802180
7306594500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306594500
7306594500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306595000
7306594500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306594500
7306594500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306595000
7306594500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306594500
7306594500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306595000
7306594500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306594500
7306594500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306595000
7306594750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306594750
7306594750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306594750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 2
7306594750: DRAM: system.mem_ctrls: Responding to Address 0x807371c0
7306594750: DRAM: system.mem_ctrls: Done: ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9824080
7306594750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306629750
7306595000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306595000
7306595000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306595000
7306595000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802a00
7306595000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802a00
7306595000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306598000
7306595000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306595000
7306595000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306595500
7306595000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306595000
7306595000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306595500
7306595000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306595000
7306595000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306595500
7306595000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306595000
7306591500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306595000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306595500
7306595500: Event: system.tol2bus.respLayer16.wrapped_function_event: EventFunctionWrapped 1320 executed @ 7306595500
7306595500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306595500
7306595500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306596000
7306595500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306595500
7306595500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306596000
7306595500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306595500
7306595500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306596000
7306595500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306595500
7306595500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306596000
7306596000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306596000
7306596000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306596500
7306596000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306596000
7306596000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306596500
7306596000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306596000
7306596000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306596500
7306596000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306596000
7306596000: Cache: system.cpu3.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306596000: CachePort: system.cpu3.dcache.mem_side: Scheduling send event at 7306597000
7306596000: Event: system.cpu3.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 190 scheduled @ 7306597000
7306596000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306596500
7306596500: Event: system.cpu4.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 246 executed @ 7306596500
7306596500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306596500
7306596500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306597000
7306596500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306596500
7306596500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306597000
7306596500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306596500
7306596500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306597000
7306596500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306596500
7306596500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306597000
7306597000: Event: system.cpu3.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 190 executed @ 7306597000
7306597000: Cache: system.cpu3.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306597000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[13] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306597000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[13] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306597000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[13] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00 SF size: 0 lat: 0
7306597000: CoherentXBar: system.tol2bus: forwardTiming for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306597000: Cache: system.l2: access for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306597000: CachePort: system.l2.mem_side: Scheduling send event at 7306607500
7306597000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306598000
7306597000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306597000 to 7306598000
7306597000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306597000
7306597000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306597500
7306597000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306597000
7306597000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306597500
7306597000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306597000
7306597000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306597500
7306597000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306597000
7306597000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306597500
7306597250: Event: system.mem_ctrls_1.wrapped_function_event: EventFunctionWrapped 19 executed @ 7306597250
7306597250: Event: system.mem_ctrls_1.wrapped_function_event: EventFunctionWrapped 20 executed @ 7306597250
7306597500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306597500
7306597500: Cache: system.l2: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306597500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306597500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306597500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80 SF size: 0 lat: 1
7306597500: CoherentXBar: system.membus: forwardTiming for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306597500: DRAM: system.mem_ctrls: recvTimingReq: request WriteReq addr 0x80a70800 size 4
7306597500: DRAM: system.mem_ctrls: Write queue limit 64, current size 26, entries needed 1
7306597500: DRAM: system.mem_ctrls: Merging write burst with existing queue entry
7306597500: DRAM: system.mem_ctrls: Responding to Address 0x80a70800
7306597500: DRAM: system.mem_ctrls: Done: WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306597500: DRAM: system.mem_ctrls: Request scheduled immediately
7306597500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306597500
7306597500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306600000
7306597500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306597500 to 7306600000
7306597500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306603500
7306597500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306597500
7306597500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306597500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306597500
7306597500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306598000
7306597500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306597500
7306597500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306598000
7306597500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306597500
7306597500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306598000
7306597500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306597500
7306597500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306598000
7306598000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306598000
7306598000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306598000
7306598000: Cache: system.l2: recvTimingResp: Handling response CleanInvalidResp [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fe80
7306598000: CacheVerbose: system.l2: recvTimingResp: Leaving with CleanInvalidResp [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fe80
7306598000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306598000
7306598000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306598000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306598000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306600000
7306598000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306599000
7306598000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306598000 to 7306599000
7306598000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306605750
7306598000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306598000
7306598000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306598500
7306598000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306598000
7306598000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306598500
7306598000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306598000
7306598000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306598500
7306598000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306598000
7306598000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306598500
7306598500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306598500
7306598500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306599000
7306598500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306598500
7306598500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306599000
7306598500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306598500
7306598500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306599000
7306598500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306598500
7306598500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306599000
7306599000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306599000
7306599000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306599000
7306599000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc8fb7d00
7306599000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[16] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc8fb7d00
7306599000: Event: system.tol2bus.slave[16]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1319 scheduled @ 7306599500
7306599000: Event: system.tol2bus.respLayer16.wrapped_function_event: EventFunctionWrapped 1320 scheduled @ 7306600500
7306599000: BaseXBar: system.tol2bus.respLayer16: The crossbar layer is now busy from tick 7306599000 to 7306600500
7306599000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306604000
7306599000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306599000
7306599000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306599500
7306599000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306599000
7306599000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306599500
7306599000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306599000
7306599000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306599500
7306599000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306599000
7306599000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306599500
7306599500: Event: system.tol2bus.slave[16]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1319 executed @ 7306599500
7306599500: Cache: system.cpu4.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc8fb7d00
7306599500: Event: system.cpu4.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 246 scheduled @ 7306601500
7306599500: CacheVerbose: system.cpu4.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc8fb7d00
7306599500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306599500
7306599500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306600000
7306599500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306599500
7306599500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306600000
7306599500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306599500
7306599500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306600000
7306599500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306599500
7306599500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306600000
7306600000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306600000
7306600000: Cache: system.l2: recvTimingResp: Handling response WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306600000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306600000
7306600000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306600000
7306600000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306600500
7306600000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306600000
7306600000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306600500
7306600000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306600000
7306600000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306600500
7306600000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306600000
7306600000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306600500
7306600500: Event: system.tol2bus.respLayer16.wrapped_function_event: EventFunctionWrapped 1320 executed @ 7306600500
7306600500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306600500
7306600500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306601000
7306600500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306600500
7306600500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306601000
7306600500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306600500
7306600500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306601000
7306600500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306600500
7306600500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306601000
7306601000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306601000
7306601000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306601500
7306601000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306601000
7306601000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306601500
7306601000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306601000
7306601000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306601500
7306601000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306601000
7306601000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306601500
7306601500: Event: system.cpu4.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 246 executed @ 7306601500
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306601500
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306601500
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306602000
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306601500
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306602000
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306601500
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306602000
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306601500
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306602000
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306601500
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306602000
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306602000
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306602500
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306602000
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306602500
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306602000
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306602500
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306602000
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306602500
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306602000
7306602000: Cache: system.cpu4.icache: access for ReadReq [807371c0:807371ff] IF UC D=c032d4d18f5500006374696f6e5772617070656420323436207363686564756c6564204020373330363539363530300a000035370a00000090d4e9cd8f550000 ptr=0x558fd070f500
7306602000: CachePort: system.cpu4.icache.mem_side: Scheduling send event at 7306603000
7306602000: Event: system.cpu4.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 248 scheduled @ 7306603000
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306602500
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306602500
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306603000
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306602500
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306603000
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306602500
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306603000
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306602500
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306603000
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306602500
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306603000
7306603000: Event: system.cpu4.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 248 executed @ 7306603000
7306603000: Cache: system.cpu4.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c032d4d18f5500006374696f6e5772617070656420323436207363686564756c6564204020373330363539363530300a000035370a00000090d4e9cd8f550000 ptr=0x558fd070f500
7306603000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[16] packet ReadReq [807371c0:807371ff] IF UC D=0037d4d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363630333030300a0000b2c98f550000e0039fd6c11900b0 ptr=0x558fc8fb7d00
7306603000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[16] packet ReadReq [807371c0:807371ff] IF UC D=0037d4d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363630333030300a0000b2c98f550000e0039fd6c11900b0 ptr=0x558fc8fb7d00
7306603000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[16] packet ReadReq [807371c0:807371ff] IF UC D=0037d4d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363630333030300a0000b2c98f550000e0039fd6c11900b0 ptr=0x558fc8fb7d00 SF size: 0 lat: 0
7306603000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=0037d4d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363630333030300a0000b2c98f550000e0039fd6c11900b0 ptr=0x558fc8fb7d00
7306603000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=0037d4d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363630333030300a0000b2c98f550000e0039fd6c11900b0 ptr=0x558fc8fb7d00
7306603000: CachePort: system.l2.mem_side: Scheduling send event at 7306613500
7306603000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306603500
7306603000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306603000 to 7306603500
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306603000
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306603500
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306603000
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306603500
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306603000
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306603500
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306603000
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306603500
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306603000
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306603500
7306603500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306603500
7306603500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306603500
7306603500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=4010d1d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363539333030300a0000c39a0100018b430400d10000238a ptr=0x558fc8fb7f80
7306603500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=40bcacd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070fe80
7306603500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=40bcacd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070fe80
7306603500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=40bcacd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070fe80 SF size: 0 lat: 1
7306603500: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=40bcacd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070fe80
7306603500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306603500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306603500: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306603500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306603500: DRAM: system.mem_ctrls: Adding to read queue
7306603500: DRAM: system.mem_ctrls: Request scheduled immediately
7306603500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306603500
7306603500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306605000
7306603500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306603500 to 7306605000
7306603500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306607500
7306603500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306603500
7306603500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306603500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306603500: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306603500: DRAM: system.mem_ctrls: Removing burstTick for 7306595000
7306603500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306621000
7306603500: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306639750 next burst at 7306626000.
7306603500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306603500
7306603500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306603500
7306603500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306603500
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306604000
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306603500
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306604000
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306603500
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306604000
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306603500
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306604000
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306603500
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306604000
7306604000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306604000
7306604000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fd00
7306604000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[20] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fd00
7306604000: Event: system.tol2bus.slave[20]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1327 scheduled @ 7306604500
7306604000: Event: system.tol2bus.respLayer20.wrapped_function_event: EventFunctionWrapped 1328 scheduled @ 7306605500
7306604000: BaseXBar: system.tol2bus.respLayer20: The crossbar layer is now busy from tick 7306604000 to 7306605500
7306604000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306608000
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306604000
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306604500
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306604000
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306604500
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306604000
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306604500
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306604000
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306604500
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306604000
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306604500
7306604500: Event: system.tol2bus.slave[20]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1327 executed @ 7306604500
7306604500: Cache: system.cpu5.icache: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fd00
7306604500: Event: system.cpu5.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 291 scheduled @ 7306606500
7306604500: CacheVerbose: system.cpu5.icache: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fd00
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306604500
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306605000
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306604500
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306605000
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306604500
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306605000
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306604500
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306605000
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306604500
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306605000
7306605000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306605000
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306605000
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306605500
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306605000
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306605500
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306605000
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306605500
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306605000
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306605500
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306605000
7306601500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306605500
7306605500: Event: system.tol2bus.respLayer20.wrapped_function_event: EventFunctionWrapped 1328 executed @ 7306605500
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306605500
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306606000
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306605500
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306606000
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306605500
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306606000
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306605500
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306606000
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306605500
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306606000
7306605750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306605750
7306605750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802b80
7306605750: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802b80
7306605750: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306608000
7306605750: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306611000
7306605750: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306605750 to 7306611000
7306605750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306610750
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306606000
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306606500
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306606000
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306606500
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306606000
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306606500
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306606000
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306606500
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306606000
7306606000: Cache: system.cpu4.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fd00
7306606000: CachePort: system.cpu4.dcache.mem_side: Scheduling send event at 7306607000
7306606000: Event: system.cpu4.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 235 scheduled @ 7306607000
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306606500
7306606500: Event: system.cpu5.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 291 executed @ 7306606500
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306606500
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306607000
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306606500
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306607000
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306606500
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306607000
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306606500
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306607000
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306606500
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306607000
7306607000: Event: system.cpu4.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 235 executed @ 7306607000
7306607000: Cache: system.cpu4.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fd00
7306607000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[17] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fd00
7306607000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[17] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fd00
7306607000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[17] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fd00 SF size: 0 lat: 0
7306607000: CoherentXBar: system.tol2bus: forwardTiming for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fd00
7306607000: Cache: system.l2: access for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fd00
7306607000: CachePort: system.l2.mem_side: Scheduling send event at 7306617500
7306607000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306608000
7306607000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306607000 to 7306608000
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306607000
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306607500
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306607000
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306607500
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306607000
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306607500
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306607000
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306607500
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306607000
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306607500
7306607500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306607500
7306607500: Cache: system.l2: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306607500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306607500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306607500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00 SF size: 0 lat: 1
7306607500: CoherentXBar: system.membus: forwardTiming for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306607500: DRAM: system.mem_ctrls: recvTimingReq: request WriteReq addr 0x80a70800 size 4
7306607500: DRAM: system.mem_ctrls: Write queue limit 64, current size 26, entries needed 1
7306607500: DRAM: system.mem_ctrls: Merging write burst with existing queue entry
7306607500: DRAM: system.mem_ctrls: Responding to Address 0x80a70800
7306607500: DRAM: system.mem_ctrls: Done: WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306607500: DRAM: system.mem_ctrls: Request scheduled immediately
7306607500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306607500
7306607500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306610000
7306607500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306607500 to 7306610000
7306607500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306613500
7306607500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306607500
7306607500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306607500
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306608000
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306607500
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306608000
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306607500
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306608000
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306607500
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306608000
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306607500
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306608000
7306608000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306608000
7306608000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306608000
7306608000: Cache: system.l2: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802b80
7306608000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802b80
7306608000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306608000
7306608000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet CleanInvalidResp [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800
7306608000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[1] packet CleanInvalidResp [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800
7306608000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse:   old SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306608000: SnoopFilter: system.tol2bus.snoop_filter: eraseIfNullEntry:   Removed SF entry.
7306608000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306608000: Event: system.tol2bus.slave[1]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1289 scheduled @ 7306608500
7306608000: Event: system.tol2bus.respLayer1.wrapped_function_event: EventFunctionWrapped 1290 scheduled @ 7306608500
7306608000: BaseXBar: system.tol2bus.respLayer1: The crossbar layer is now busy from tick 7306608000 to 7306608500
7306608000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306609000
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306608000
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306608500
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306608000
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306608500
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306608000
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306608500
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306608000
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306608500
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306608000
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306608500
7306608500: Event: system.tol2bus.respLayer1.wrapped_function_event: EventFunctionWrapped 1290 executed @ 7306608500
7306608500: Event: system.tol2bus.slave[1]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1289 executed @ 7306608500
7306608500: Cache: system.cpu0.dcache: recvTimingResp: Handling response CleanInvalidResp [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800
7306608500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306609500
7306608500: CacheVerbose: system.cpu0.dcache: recvTimingResp: Leaving with CleanInvalidResp [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306608500
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306609000
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306608500
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306609000
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306608500
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306609000
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306608500
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306609000
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306608500
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306609000
7306609000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306609000
7306609000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802700
7306609000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[20] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802700
7306609000: Event: system.tol2bus.slave[20]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1327 scheduled @ 7306609500
7306609000: Event: system.tol2bus.respLayer20.wrapped_function_event: EventFunctionWrapped 1328 scheduled @ 7306610500
7306609000: BaseXBar: system.tol2bus.respLayer20: The crossbar layer is now busy from tick 7306609000 to 7306610500
7306609000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306610000
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306609000
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306609500
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306609000
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306609500
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306609000
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306609500
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306609000
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306609500
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306609000
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306609500
7306609500: Event: system.tol2bus.slave[20]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1327 executed @ 7306609500
7306609500: Cache: system.cpu5.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802700
7306609500: Event: system.cpu5.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 291 scheduled @ 7306611500
7306609500: CacheVerbose: system.cpu5.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802700
7306609500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306609500
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306609500
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306610000
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306609500
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306610000
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306609500
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306610000
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306609500
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306610000
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306609500
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306610000
7306610000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306610000
7306610000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306610000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[5] packet WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306610000: Event: system.tol2bus.slave[5]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1297 scheduled @ 7306610500
7306610000: Event: system.tol2bus.respLayer5.wrapped_function_event: EventFunctionWrapped 1298 scheduled @ 7306610500
7306610000: BaseXBar: system.tol2bus.respLayer5: The crossbar layer is now busy from tick 7306610000 to 7306610500
7306610000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306622000
7306610000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306610000
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306610000
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306610500
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306610000
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306610500
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306610000
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306610500
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306610000
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306610500
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306610000
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306610500
7306610500: Event: system.tol2bus.respLayer5.wrapped_function_event: EventFunctionWrapped 1298 executed @ 7306610500
7306610500: Event: system.tol2bus.slave[5]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1297 executed @ 7306610500
7306610500: Cache: system.cpu1.dcache: recvTimingResp: Handling response WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306610500: Event: system.cpu1.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 98 scheduled @ 7306611500
7306610500: Event: system.tol2bus.respLayer20.wrapped_function_event: EventFunctionWrapped 1328 executed @ 7306610500
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306610500
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306611000
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306610500
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306611000
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306610500
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306611000
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306610500
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306611000
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306610500
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306611000
7306610750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306610750
7306610750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802800 BUSY
7306611000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306611000
7306611000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802800
7306611000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802800
7306611000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306613000
7306611000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306616000
7306611000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306611000 to 7306616000
7306611000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306616750
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306611000
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306611500
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306611000
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306611500
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306611000
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306611500
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306611000
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306611500
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306611000
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306611500
7306611500: Event: system.cpu1.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 98 executed @ 7306611500
7306611500: Event: system.cpu5.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 291 executed @ 7306611500
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306611500
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306611500
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306612000
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306611500
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306612000
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306611500
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306612000
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306611500
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306612000
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306611500
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306612000
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306611500
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306612000
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306612000
7306519500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+48    :   dsb                      : IntAlu :   FetchSeq=13255200  CPSeq=11776692  flags=(IsSerializeAfter|IsMemBarrier)
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306612500
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306612000
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306612500
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306612000
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306612500
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306612000
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306612500
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306612000
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306612500
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306612000
7306612000: Cache: system.cpu5.icache: access for ReadReq [807371c0:807371ff] IF UC D=c03cd4d18f5500006374696f6e577261707065642031323835206578656375746564204020373330363630383030300a000035386664303730666430300018d5 ptr=0x558fc9802000
7306612000: CachePort: system.cpu5.icache.mem_side: Scheduling send event at 7306613000
7306612000: Event: system.cpu5.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 293 scheduled @ 7306613000
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306612500
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306612500
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306613000
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306612500
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306613000
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306612500
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306613000
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306612500
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306613000
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306612500
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306613000
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306612500
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306613000
7306613000: Event: system.cpu5.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 293 executed @ 7306613000
7306613000: Cache: system.cpu5.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c03cd4d18f5500006374696f6e577261707065642031323835206578656375746564204020373330363630383030300a000035386664303730666430300018d5 ptr=0x558fc9802000
7306613000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[20] packet ReadReq [807371c0:807371ff] IF UC D=0051d2d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363631333030300a00000000000000000000000000000000 ptr=0x558fd070f480
7306613000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[20] packet ReadReq [807371c0:807371ff] IF UC D=0051d2d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363631333030300a00000000000000000000000000000000 ptr=0x558fd070f480
7306613000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[20] packet ReadReq [807371c0:807371ff] IF UC D=0051d2d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363631333030300a00000000000000000000000000000000 ptr=0x558fd070f480 SF size: 0 lat: 0
7306613000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=0051d2d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363631333030300a00000000000000000000000000000000 ptr=0x558fd070f480
7306613000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=0051d2d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363631333030300a00000000000000000000000000000000 ptr=0x558fd070f480
7306613000: CachePort: system.l2.mem_side: Scheduling send event at 7306623500
7306613000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306613500
7306613000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306613000 to 7306613500
7306613000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306613000
7306613000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802800
7306613000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802800
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306613000
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306613500
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306613000
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306613500
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306613000
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306613500
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306613000
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306613500
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306613000
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306613500
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306613000
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306613500
7306613500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306613500
7306613500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306613500
7306613500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=0037d4d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363630333030300a0000b2c98f550000e0039fd6c11900b0 ptr=0x558fc8fb7d00
7306613500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=4097d6d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802800
7306613500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=4097d6d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802800
7306613500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=4097d6d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802800 SF size: 0 lat: 1
7306613500: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=4097d6d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802800
7306613500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306613500: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306613500: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306613500: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306613500: DRAM: system.mem_ctrls: Adding to read queue
7306613500: DRAM: system.mem_ctrls: Request scheduled immediately
7306613500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306613500
7306613500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306615000
7306613500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306613500 to 7306615000
7306613500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306617500
7306613500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306613500
7306613500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306613500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306613500: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306613500: DRAM: system.mem_ctrls: Removing burstTick for 7306610000
7306613500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306626000
7306613500: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306644750 next burst at 7306631000.
7306613500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306613500
7306613500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306613500
7306613500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306613500
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306614000
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306613500
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306614000
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306613500
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306614000
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306613500
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306614000
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306613500
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306614000
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306613500
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306614000
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306614000
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306614500
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306614000
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375188    :   dmb                      : IntAlu :   FetchSeq=184  CPSeq=39  flags=(IsMemBarrier)
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306614500
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306614000
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306614500
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306614000
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306614500
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306614000
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306614500
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306614000
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306614500
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306614500
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306615000
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306614500
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306615000
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306614500
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306615000
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306614500
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306615000
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306614500
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375192    :   dc ivac   , x1           : MemWrite :  A=0x80a70800  FetchSeq=185  CPSeq=40  flags=(IsInteger|IsMemRef|IsStore)
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375196    :   ret                      : IntAlu :   FetchSeq=186  CPSeq=41  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306615000
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306614500
7306614500: Cache: system.cpu0.icache: access for ReadReq [80337900:8033793f] IF D=c097d6d18f550000400b80c98f5500005141ca0000000000e07974d08f5500000000000000000000901ab2c98f5500009833b2c98f5500000000000000000000 ptr=0x558fd070f580 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x200cd set: 0xe4 way: 0
7306614500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306615500
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306615000
7306615000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306615000
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306615000
7306519500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+52    :   ret                      : IntAlu :   FetchSeq=13255201  CPSeq=11776693  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306615500
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306615000
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306615500
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306615000
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306615500
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306615000
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306615500
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306615000
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306615500
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306615000
7306611500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306615500
7306615500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306615500
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306615500
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306616000
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306615500
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306616000
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306615500
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306616000
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306615500
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306616000
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306615500
7306615500: Cache: system.cpu1.dcache: access for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f580 miss
7306615500: CachePort: system.cpu1.dcache.mem_side: Scheduling send event at 7306616500
7306615500: Event: system.cpu1.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 100 scheduled @ 7306616500
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306616000
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306615500
7306615500: Cache: system.cpu0.dcache: access for ReadReq [8d847df0:8d847df7] D=482e6acf8f550000 ptr=0x558fc9802700 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306615500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306616500
7306615500: Cache: system.cpu0.dcache: access for ReadReq [8d847de0:8d847def] D=30c116d28f5500002024ebc88f550000 ptr=0x558fd070f800 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306616000
7306616000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306616000
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306616000
7306616000: Cache: system.cpu0.icache: access for ReadReq [80337940:8033797f] IF D=c04fd2d18f550000602febc88f550000733eca0000000000000000000100ffff000000008f550000a0adeac88f55000050beeac88f55000090adb9cd8f550000 ptr=0x558fc9802b80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x200cd set: 0xe5 way: 0x1
7306616000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306617000
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306616500
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306616000
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306616500
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306616000
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306616500
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306616000
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306616500
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306616000
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306616500
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306616000
7306616000: Cache: system.cpu5.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fe00
7306616000: CachePort: system.cpu5.dcache.mem_side: Scheduling send event at 7306617000
7306616000: Event: system.cpu5.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 280 scheduled @ 7306617000
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306616500
7306616500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306616500
7306616500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306616501
7306616500: Event: system.cpu1.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 100 executed @ 7306616500
7306616500: Cache: system.cpu1.dcache: sendMSHRQueuePacket: MSHR InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f580
7306616500: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[5] packet InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fd80
7306616500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[5] packet InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fd80
7306616500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306616500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306616500: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[5] packet InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fd80 SF size: 0 lat: 0
7306616500: CoherentXBar: system.tol2bus: forwardTiming for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fd80
7306616500: Cache: system.l2: access for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fd80 miss
7306616500: CachePort: system.l2.mem_side: Scheduling send event at 7306627000
7306616500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306617000
7306616500: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306616500 to 7306617000
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306616500
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306617000
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306616500
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306617000
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306616500
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306617000
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306616500
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306617000
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306616500
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306617000
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306616500
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306617000
7306616501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306616501
7306616750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306616750
7306616750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802400
7306616750: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802400
7306616750: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306619000
7306616750: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306622000
7306616750: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306616750 to 7306622000
7306616750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306617000
7306617000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306617000
7306617000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80 BUSY
7306617000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306617000
7306617000: Event: system.cpu5.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 280 executed @ 7306617000
7306617000: Cache: system.cpu5.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fe00
7306617000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[21] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fe00
7306617000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[21] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fe00
7306617000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306617000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[21] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fe00 SF size: 1 lat: 0
7306617000: CoherentXBar: system.tol2bus: forwardTiming for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fe00
7306617000: CacheVerbose: system.cpu1.dcache: recvTimingSnoopReq: for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fe00
7306617000: Cache: global: handleSnoop for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fe00