cirosantilli2/README.md

## README.md

      
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    ./run -aA -eg -N1 --linux-exec /home/ciro/bak/git/linux-kernel-module-cheat/out/gem5/test_binaries/binaries/vmlinux.arm64 --cpus 8 --trace FmtFlag,CacheAll,DRAM,ExecAll,Event,XBar --G=--debug-start=7306449500 -- --cpu-type DerivO3CPU --caches --l2cache 

gem5 3ca404da175a66e0b958165ad75eb5f54cb5e772 full CLI:
+ M5_OVERRIDE_PY_SOURCE=true \
  rr record /home/ciro/bak/git/linux-kernel-module-cheat/out/gem5/1/build/ARM/gem5.debug \
  --debug-file trace.txt \
  --listener-mode on \
  --outdir /home/ciro/bak/git/linux-kernel-module-cheat/out/run/gem5/aarch64/0/m5out \
  --debug-flags FmtFlag,ExecAll,Cache,DRAM,Event \
  /home/ciro/bak/git/linux-kernel-module-cheat/data/gem5/1/configs/example/fs.py \
  --kernel /home/ciro/bak/git/linux-kernel-module-cheat/out/gem5/test_binaries/binaries/vmlinux.arm64 \
  --num-cpus 8 \
  --script /home/ciro/bak/git/linux-kernel-module-cheat/out/run/gem5/aarch64/0/readfile \
  --disk-image /home/ciro/bak/git/linux-kernel-module-cheat/out/buildroot/build/default/aarch64/images/rootfs.ext2 \
  --machine-type VExpress_GEM5_V1 \
  --command-line 'earlyprintk=pl011,0x1c090000 lpj=19988480 rw loglevel=8 mem=256MB root=/dev/sda console_msg_format=syslog nokaslr norandmaps panic=-1 printk.devkmsg=on printk.time=y rw console=ttyAMA0 - lkmc_home=/lkmc' \
  --param 'system.workload.panic_on_panic = True' \
  --bootloader /home/ciro/bak/git/linux-kernel-module-cheat/out/gem5/1/system/binaries/boot.arm64 \
  --mem-size 256MB \
  --cpu-type DerivO3CPU --caches --l2cache \
;

Reproduces error:
panic: panic condition (pkt->needsWritable() != pkt->isInvalidate()) && !pkt->req->isCacheMaintenance() occurred: global got snoop WriteReq [80a70800:80a70803] UC D=110e0000 where needsWritable, does not match isInvalidate

Panic comes from:
bool
MSHR::handleSnoop(PacketPtr pkt, Counter _order)
{
    DPRINTF(Cache, "%s for %s\n", __func__, pkt->print());

    // when we snoop packets the needsWritable and isInvalidate flags
    // should always be the same, however, this assumes that we never
    // snoop writes as they are currently not marked as invalidations
    panic_if((pkt->needsWritable() != pkt->isInvalidate()) &&
             !pkt->req->isCacheMaintenance(),

GDB values:
>>> p pkt->needsWritable()
$1 = true
>>> p pkt->isInvalidate()
$2 = false

Backtrace to it:
MSHR::handleSnoop(Packet*, long)+0xaa0)[0x5568a52a6920]
Cache::recvTimingSnoopReq(Packet*)+0x293)[0x5568a529a7e3]
CoherentXBar::forwardTiming(Packet*, short, std::vector<QueuedSlavePort*, std::allocator<QueuedSlavePort*> > const&)+0xbc)[0x5568a69e6efc]
CoherentXBar::recvTimingReq(Packet*, short)+0xde9)[0x5568a69eab79]
BaseCache::sendWriteQueuePacket(WriteQueueEntry*)+0x24e)[0x5568a529325e]
BaseCache::CacheReqPacketQueue::sendDeferredPacket()+0xd9)[0x5568a5286709]
EventQueue::serviceOne()+0xb9)[0x5568a6d04e09]
doSimLoop(EventQueue*)+0xf8)[0x5568a6d25d18]
simulate(unsigned long)+0xaed)[0x5568a6d26b0d]

Code snippets from backtrace:
void
Cache::recvTimingSnoopReq(PacketPtr pkt)
{
    DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print());
    ...
    if (mshr && mshr->handleSnoop(pkt, order++)) {

void
CoherentXBar::forwardTiming(PacketPtr pkt, PortID exclude_slave_port_id,
                           const std::vector<QueuedSlavePort*>& dests)
{
    DPRINTF(CoherentXBar, "%s for %s\n", __func__, pkt->print());

    // snoops should only happen if the system isn't bypassing caches
    assert(!system->bypassCaches());

    unsigned fanout = 0;

    for (const auto& p: dests) {
        // we could have gotten this request from a snooping master
        // (corresponding to our own slave port that is also in
        // snoopPorts) and should not send it back to where it came
        // from
        if (exclude_slave_port_id == InvalidPortID ||
            p->getId() != exclude_slave_port_id) {
            // cache is not allowed to refuse snoop
            p->sendTimingSnoopReq(pkt);
            fanout++;
        }
    }

    // Stats for fanout of this forward operation
    snoopFanout.sample(fanout);
}

CoherentXBar::recvTimingReq(PacketPtr pkt, PortID slave_port_id)
{

    ....

    const bool is_destination = isDestination(pkt);

    const bool snoop_caches = !system->bypassCaches() &&
        pkt->cmd != MemCmd::WriteClean;
    if (snoop_caches) {
        assert(pkt->snoopDelay == 0);

        if (pkt->isClean() && !is_destination) {
            // before snooping we need to make sure that the memory
            // below is not busy and the cache clean request can be
            // forwarded to it
            if (!masterPorts[master_port_id]->tryTiming(pkt)) {
                DPRINTF(CoherentXBar, "%s: src %s packet %s RETRY\n", __func__,
                        src_port->name(), pkt->print());

                // update the layer state and schedule an idle event
                reqLayers[master_port_id]->failedTiming(src_port,
                                                        clockEdge(Cycles(1)));
                return false;
            }
        }


        // the packet is a memory-mapped request and should be
        // broadcasted to our snoopers but the source
        if (snoopFilter) {
            // check with the snoop filter where to forward this packet
            auto sf_res = snoopFilter->lookupRequest(pkt, *src_port);
            // the time required by a packet to be delivered through
            // the xbar has to be charged also with to lookup latency
            // of the snoop filter
            pkt->headerDelay += sf_res.second * clockPeriod();
            DPRINTF(CoherentXBar, "%s: src %s packet %s SF size: %i lat: %i\n",
                    __func__, src_port->name(), pkt->print(),
                    sf_res.first.size(), sf_res.second);

            if (pkt->isEviction()) {
                // for block-evicting packets, i.e. writebacks and
                // clean evictions, there is no need to snoop up, as
                // all we do is determine if the block is cached or
                // not, instead just set it here based on the snoop
                // filter result
                if (!sf_res.first.empty())
                    pkt->setBlockCached();
            } else {
                forwardTiming(pkt, slave_port_id, sf_res.first);
            }
        } else {
            forwardTiming(pkt, slave_port_id);
        }

bool
BaseCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry)
{
    assert(wq_entry);

    // always a single target for write queue entries
    PacketPtr tgt_pkt = wq_entry->getTarget()->pkt;

    DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print());

    // forward as is, both for evictions and uncacheable writes
    if (!memSidePort.sendTimingReq(tgt_pkt)) {
        // note that we have now masked any requestBus and
        // schedSendEvent (we will wait for a retry before
        // doing anything), and this is so even if we do not
        // care about this packet and might override it before
        // it gets retried
        return true;
    } else {
        markInService(wq_entry);
        return false;
    }
}

Last tick:
7306611500: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)

Last cpu0 instruction:
7306519500: system.cpu0: A0 T0 : @__flush_dcache_area+52    :   ret                      : IntAlu :   FetchSeq=13255201  CPSeq=11776693  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)

grep 80a70800 trace.txt
      0: CacheVerbose: system.iocache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.l2: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu0.icache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu0.dcache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu1.icache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu1.dcache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu2.icache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu2.dcache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu3.icache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu3.dcache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu4.icache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu4.dcache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu5.icache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu5.dcache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu6.icache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu6.dcache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu7.icache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
      0: CacheVerbose: system.cpu7.dcache: functionalAccess: WriteReq [80a70800:80a7083f] D=120e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
2116500: ExecEnable: system.cpu0: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=218  CPSeq=74  flags=(IsInteger)
2199500: ExecEnable: system.cpu0: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=226  CPSeq=77  flags=(IsInteger|IsMemRef|IsStore)
2204000: Cache: system.cpu0.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000
2205000: Cache: system.cpu0.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
2205000: Cache: system.l2: access for WriteReq [80a70800:80a70803] UC D=110e0000
2215500: Cache: system.l2: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
2215500: DRAM: system.mem_ctrls: recvTimingReq: request WriteReq addr 0x80a70800 size 4
2215500: DRAM: system.mem_ctrls: Responding to Address 0x80a70800.. 2215500: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 8 scheduled @ 2235000
2215500: DRAM: system.mem_ctrls: Done: WriteResp [80a70800:80a70803] UC D=110e0000
2237000: Cache: system.l2: recvTimingResp: Handling response WriteResp [80a70800:80a70803] UC D=110e0000
2247500: Cache: system.cpu0.dcache: recvTimingResp: Handling response WriteResp [80a70800:80a70803] UC D=110e0000
2199500: ExecEnable: system.cpu0: A0 T0 : @_kernel_size_le_lo32+2144375192    :   dc ivac   , x1           : MemWrite :  A=0x80a70800  FetchSeq=228  CPSeq=79  flags=(IsInteger|IsMemRef|IsStore)
2252500: Cache: system.cpu0.dcache: access for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 miss
2253500: Cache: system.cpu0.dcache: sendMSHRQueuePacket: MSHR InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
2253500: Cache: system.l2: access for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 miss
2264000: Cache: system.l2: sendMSHRQueuePacket: MSHR InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
2272000: Cache: system.l2: recvTimingResp: Handling response InvalidateResp [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
2272000: CacheVerbose: system.l2: recvTimingResp: Leaving with InvalidateResp [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
2282500: Cache: system.cpu0.dcache: recvTimingResp: Handling response InvalidateResp [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
2282500: CacheVerbose: system.cpu0.dcache: recvTimingResp: Leaving with InvalidateResp [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
18843500: ExecEnable: system.cpu0: A0 T0 : @_kernel_size_le_lo32+2144375372    :   dc ivac   , x1           : MemWrite :  A=0x80a70800  FetchSeq=9292  CPSeq=8760  flags=(IsInteger|IsMemRef|IsStore)
18896500: Cache: system.cpu0.dcache: access for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 miss
18897500: Cache: system.cpu0.dcache: sendMSHRQueuePacket: MSHR InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
18897500: Cache: system.l2: access for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 miss
18908000: Cache: system.l2: sendMSHRQueuePacket: MSHR InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
18916000: Cache: system.l2: recvTimingResp: Handling response InvalidateResp [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
18916000: CacheVerbose: system.l2: recvTimingResp: Leaving with InvalidateResp [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
18926500: Cache: system.cpu0.dcache: recvTimingResp: Handling response InvalidateResp [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
18926500: CacheVerbose: system.cpu0.dcache: recvTimingResp: Leaving with InvalidateResp [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6666523500: Cache: system.cpu0.dcache: access for ReadReq [80a70800:80a70803] D=6090b49e miss
6666524500: Cache: system.cpu0.dcache: sendMSHRQueuePacket: MSHR ReadReq [80a70800:80a70803] D=6090b49e
6666524500: Cache: system.cpu0.dcache: createMissPacket: created ReadSharedReq [80a70800:80a7083f] D=00e2ffa0655500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e74000a000000000000000000000000000000 from ReadReq [80a70800:80a70803] D=6090b49e
6666524500: Cache: system.l2: access for ReadSharedReq [80a70800:80a7083f] D=00e2ffa0655500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e74000a000000000000000000000000000000 miss
6666535000: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadSharedReq [80a70800:80a7083f] D=00e2ffa0655500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e74000a000000000000000000000000000000
6666535000: Cache: system.l2: createMissPacket: created ReadSharedReq [80a70800:80a7083f] D=00aca9986555000070100f9d65550000e0100f9d6555000050110f9d65550000c0110f9d6555000030120f9d65550000a0120f9d6555000010130f9d65550000 from ReadSharedReq [80a70800:80a7083f] D=00e2ffa0655500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e74000a000000000000000000000000000000
6666535000: DRAM: system.mem_ctrls: recvTimingReq: request ReadSharedReq addr 0x80a70800 size 64
6666567500: DRAM: system.mem_ctrls: Responding to Address 0x80a70800.. 6666567500: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 8 scheduled @ 6666595500
6666567500: DRAM: system.mem_ctrls: Done: ReadResp [80a70800:80a7083f] D=110e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6666598000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80a70800:80a7083f] D=110e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6666598000: Cache: system.l2: Block for addr 0x80a70800 being updated in Cache
6666598000: Cache: system.l2: Block addr 0x80a70800 (ns) moving from state 0 to state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x2029 set: 0xc20 way: 0x2
6666598000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80a70800:80a7083f] D=110e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6666608500: Cache: system.cpu0.dcache: recvTimingResp: Handling response ReadResp [80a70800:80a7083f] D=110e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6666608500: Cache: system.cpu0.dcache: Block for addr 0x80a70800 being updated in Cache
6666608500: Cache: system.cpu0.dcache: Block addr 0x80a70800 (ns) moving from state 0 to state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x1014e set: 0x20 way: 0x1
6666608500: CacheVerbose: system.cpu0.dcache: recvTimingResp: Leaving with ReadResp [80a70800:80a7083f] D=110e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6684591500: Cache: system.cpu0.dcache: Create CleanEvict CleanEvict [80a70800:80a7083f] D=
6684592500: Cache: system.cpu0.dcache: sendWriteQueuePacket: write CleanEvict [80a70800:80a7083f] D=
6684592500: Cache: system.l2: access for CleanEvict [80a70800:80a7083f] D= hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x2029 set: 0xc20 way: 0x2
6684592500: Cache: system.l2: handleTimingReqHit satisfied CleanEvict [80a70800:80a7083f] D=, no response needed
6825844000: Cache: system.cpu0.dcache: access for ReadReq [80a70800:80a70803] D=608eb49e miss
6825845000: Cache: system.cpu0.dcache: sendMSHRQueuePacket: MSHR ReadReq [80a70800:80a70803] D=608eb49e
6825845000: Cache: system.cpu0.dcache: createMissPacket: created ReadSharedReq [80a70800:80a7083f] D=00e1ffa0655500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e74000a00d79865550000746976650a005fd6 from ReadReq [80a70800:80a70803] D=608eb49e
6825845000: Cache: system.l2: access for ReadSharedReq [80a70800:80a7083f] D=00e1ffa0655500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e74000a00d79865550000746976650a005fd6 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x2029 set: 0xc20 way: 0x2
6825856000: Cache: system.cpu0.dcache: recvTimingResp: Handling response ReadResp [80a70800:80a7083f] D=110e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6825856000: Cache: system.cpu0.dcache: Block for addr 0x80a70800 being updated in Cache
6825856000: Cache: system.cpu0.dcache: Block addr 0x80a70800 (ns) moving from state 0 to state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x1014e set: 0x20 way: 0
6825856000: CacheVerbose: system.cpu0.dcache: recvTimingResp: Leaving with ReadResp [80a70800:80a7083f] D=110e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6836065000: Cache: system.cpu0.dcache: Create CleanEvict CleanEvict [80a70800:80a7083f] D=
6836066000: Cache: system.cpu0.dcache: sendWriteQueuePacket: write CleanEvict [80a70800:80a7083f] D=
6836066000: Cache: system.l2: access for CleanEvict [80a70800:80a7083f] D= hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x2029 set: 0xc20 way: 0x2
6836066000: Cache: system.l2: handleTimingReqHit satisfied CleanEvict [80a70800:80a7083f] D=, no response needed
6894097000: Cache: system.cpu0.dcache: access for ReadReq [80a70800:80a70803] D=388eb49e miss
6894098000: Cache: system.cpu0.dcache: sendMSHRQueuePacket: MSHR ReadReq [80a70800:80a70803] D=388eb49e
6894098000: Cache: system.cpu0.dcache: createMissPacket: created ReadSharedReq [80a70800:80a7083f] D=c09002a1655500006374696f6e5772617070656420343530207363686564756c6564204020363839343037303030300a00e03891ac63dd97a0c245b900030036 from ReadReq [80a70800:80a70803] D=388eb49e
6894098000: Cache: system.l2: access for ReadSharedReq [80a70800:80a7083f] D=c09002a1655500006374696f6e5772617070656420343530207363686564756c6564204020363839343037303030300a00e03891ac63dd97a0c245b900030036 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x2029 set: 0xc20 way: 0x2
6894109000: Cache: system.cpu0.dcache: recvTimingResp: Handling response ReadResp [80a70800:80a7083f] D=110e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6894109000: Cache: system.cpu0.dcache: Block for addr 0x80a70800 being updated in Cache
6894109000: Cache: system.cpu0.dcache: Block addr 0x80a70800 (ns) moving from state 0 to state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x1014e set: 0x20 way: 0x1
6894109000: CacheVerbose: system.cpu0.dcache: recvTimingResp: Leaving with ReadResp [80a70800:80a7083f] D=110e0000110e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6943904000: Cache: system.cpu0.dcache: Create CleanEvict CleanEvict [80a70800:80a7083f] D=
6943905000: Cache: system.cpu0.dcache: sendWriteQueuePacket: write CleanEvict [80a70800:80a7083f] D=
6943905000: Cache: system.l2: access for CleanEvict [80a70800:80a7083f] D= hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x2029 set: 0xc20 way: 0x2
6943905000: Cache: system.l2: handleTimingReqHit satisfied CleanEvict [80a70800:80a7083f] D=, no response needed
7306449500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306493500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306498500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306503500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306511500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306546500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306562000: Cache: system.cpu1.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000
7306563000: Cache: system.cpu1.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
7306563000: Cache: system.l2: access for WriteReq [80a70800:80a70803] UC D=110e0000
7306563000: Cache: system.l2: Create CleanEvict CleanEvict [80a70800:80a7083f] D=
7306563000: Cache: system.l2: Potential to merge writeback WriteReq [80a70800:80a70803] UC D=110e00007306563000: CachePort: system.l2.mem_side: Scheduling send event at 7306573500
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306573500: Cache: system.l2: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
7306573500: DRAM: system.mem_ctrls: recvTimingReq: request WriteReq addr 0x80a70800 size 4
7306573500: DRAM: system.mem_ctrls: Responding to Address 0x80a70800.. 7306573500: DRAM: system.mem_ctrls: Done: WriteResp [80a70800:80a70803] UC D=110e0000
7306583000: Cache: system.l2: sendWriteQueuePacket: write CleanEvict [80a70800:80a7083f] D=
7306581500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306586000: Cache: system.cpu2.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000
7306587000: Cache: system.cpu2.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
7306587000: Cache: system.l2: access for WriteReq [80a70800:80a70803] UC D=110e0000
7306591500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306596000: Cache: system.cpu3.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000
7306597000: Cache: system.cpu3.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
7306597000: Cache: system.l2: access for WriteReq [80a70800:80a70803] UC D=110e0000
7306597500: Cache: system.l2: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
7306597500: DRAM: system.mem_ctrls: recvTimingReq: request WriteReq addr 0x80a70800 size 4
7306597500: DRAM: system.mem_ctrls: Responding to Address 0x80a70800.. 7306597500: DRAM: system.mem_ctrls: Done: WriteResp [80a70800:80a70803] UC D=110e0000
7306600000: Cache: system.l2: recvTimingResp: Handling response WriteResp [80a70800:80a70803] UC D=110e0000
7306601500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306606000: Cache: system.cpu4.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000
7306607000: Cache: system.cpu4.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
7306607000: Cache: system.l2: access for WriteReq [80a70800:80a70803] UC D=110e0000
7306607500: Cache: system.l2: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
7306607500: DRAM: system.mem_ctrls: recvTimingReq: request WriteReq addr 0x80a70800 size 4
7306607500: DRAM: system.mem_ctrls: Responding to Address 0x80a70800.. 7306607500: DRAM: system.mem_ctrls: Done: WriteResp [80a70800:80a70803] UC D=110e0000
7306610500: Cache: system.cpu1.dcache: recvTimingResp: Handling response WriteResp [80a70800:80a70803] UC D=110e0000
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375192    :   dc ivac   , x1           : MemWrite :  A=0x80a70800  FetchSeq=185  CPSeq=40  flags=(IsInteger|IsMemRef|IsStore)
7306611500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306615500: Cache: system.cpu1.dcache: access for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 miss
7306616000: Cache: system.cpu5.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000
7306616500: Cache: system.cpu1.dcache: sendMSHRQueuePacket: MSHR InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306616500: Cache: system.l2: access for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 miss
7306617000: Cache: system.cpu5.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000
7306617000: CacheVerbose: system.cpu1.dcache: recvTimingSnoopReq: for WriteReq [80a70800:80a70803] UC D=110e0000
7306617000: Cache: global: handleSnoop for WriteReq [80a70800:80a70803] UC D=110e0000

The last line is actually the very last log line.
WriteReq already necessarily implies pkt->needsWritable() != pkt->isInvalidate() (needsWritable true, isInvalidate false).
One question is why CPU1 holds that cacheline at all. All requests to system.cpu1.dcache have been UC, except for one:
7306615500: Cache: system.cpu1.dcache: access for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 miss

which presumably comes from the DC IVAC!
g ExecEnable trace.txt  | gv cpu0 shows that there are very very few instructions executed on non cpu0 cpus, the crash happens very soon after they start running.
 108500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+6    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=1  CPSeq=1  flags=(IsInteger|IsSerializeBefore)
 108500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+10    :   subs   x0, #12           : IntAlu :  D=0x0000000000000000  FetchSeq=2  CPSeq=2  flags=(IsInteger)
 108500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+14    :   b.ne   <_kernel_flags_le_lo32+142> : IntAlu :   FetchSeq=3  CPSeq=3  flags=(IsControl|IsDirectControl|IsCondControl)
 118500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+6    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=1  CPSeq=1  flags=(IsInteger|IsSerializeBefore)
 118500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+10    :   subs   x0, #12           : IntAlu :  D=0x0000000000000000  FetchSeq=2  CPSeq=2  flags=(IsInteger)
 118500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+14    :   b.ne   <_kernel_flags_le_lo32+142> : IntAlu :   FetchSeq=3  CPSeq=3  flags=(IsControl|IsDirectControl|IsCondControl)
 123500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+6    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=1  CPSeq=1  flags=(IsInteger|IsSerializeBefore)
 123500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+10    :   subs   x0, #12           : IntAlu :  D=0x0000000000000000  FetchSeq=2  CPSeq=2  flags=(IsInteger)
 123500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+14    :   b.ne   <_kernel_flags_le_lo32+142> : IntAlu :   FetchSeq=3  CPSeq=3  flags=(IsControl|IsDirectControl|IsCondControl)
 128500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+6    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=1  CPSeq=1  flags=(IsInteger|IsSerializeBefore)
 128500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+10    :   subs   x0, #12           : IntAlu :  D=0x0000000000000000  FetchSeq=2  CPSeq=2  flags=(IsInteger)
 128500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+14    :   b.ne   <_kernel_flags_le_lo32+142> : IntAlu :   FetchSeq=3  CPSeq=3  flags=(IsControl|IsDirectControl|IsCondControl)
 133500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+6    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=1  CPSeq=1  flags=(IsInteger|IsSerializeBefore)
 133500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+10    :   subs   x0, #12           : IntAlu :  D=0x0000000000000000  FetchSeq=2  CPSeq=2  flags=(IsInteger)
 133500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+14    :   b.ne   <_kernel_flags_le_lo32+142> : IntAlu :   FetchSeq=3  CPSeq=3  flags=(IsControl|IsDirectControl|IsCondControl)
 138500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+6    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=1  CPSeq=1  flags=(IsInteger|IsSerializeBefore)
 138500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+10    :   subs   x0, #12           : IntAlu :  D=0x0000000000000000  FetchSeq=2  CPSeq=2  flags=(IsInteger)
 138500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+14    :   b.ne   <_kernel_flags_le_lo32+142> : IntAlu :   FetchSeq=3  CPSeq=3  flags=(IsControl|IsDirectControl|IsCondControl)
 143500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+6    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=1  CPSeq=1  flags=(IsInteger|IsSerializeBefore)
 143500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+10    :   subs   x0, #12           : IntAlu :  D=0x0000000000000000  FetchSeq=2  CPSeq=2  flags=(IsInteger)
 143500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+14    :   b.ne   <_kernel_flags_le_lo32+142> : IntAlu :   FetchSeq=3  CPSeq=3  flags=(IsControl|IsDirectControl|IsCondControl)
 187500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+142    :   orr   x0, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=13  CPSeq=4  flags=(IsInteger)
 187500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+146    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=14  CPSeq=5  flags=(IsInteger)
 187500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+150    :   orr   x2, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=15  CPSeq=6  flags=(IsInteger)
 187500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+154    :   orr   x3, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=16  CPSeq=7  flags=(IsInteger)
 187500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+158    :   mrs   x4, mpidr_el1      : IntAlu :  D=0x0000000080000001  FetchSeq=17  CPSeq=8  flags=(IsInteger|IsSerializeBefore)
 207500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+142    :   orr   x0, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=13  CPSeq=4  flags=(IsInteger)
 207500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+146    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=14  CPSeq=5  flags=(IsInteger)
 207500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+150    :   orr   x2, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=15  CPSeq=6  flags=(IsInteger)
 207500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+154    :   orr   x3, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=16  CPSeq=7  flags=(IsInteger)
 207500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+158    :   mrs   x4, mpidr_el1      : IntAlu :  D=0x0000000080000002  FetchSeq=17  CPSeq=8  flags=(IsInteger|IsSerializeBefore)
 217500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+142    :   orr   x0, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=13  CPSeq=4  flags=(IsInteger)
 217500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+146    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=14  CPSeq=5  flags=(IsInteger)
 217500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+150    :   orr   x2, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=15  CPSeq=6  flags=(IsInteger)
 217500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+154    :   orr   x3, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=16  CPSeq=7  flags=(IsInteger)
 217500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+158    :   mrs   x4, mpidr_el1      : IntAlu :  D=0x0000000080000003  FetchSeq=17  CPSeq=8  flags=(IsInteger|IsSerializeBefore)
 227500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+142    :   orr   x0, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=13  CPSeq=4  flags=(IsInteger)
 227500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+146    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=14  CPSeq=5  flags=(IsInteger)
 227500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+150    :   orr   x2, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=15  CPSeq=6  flags=(IsInteger)
 227500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+154    :   orr   x3, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=16  CPSeq=7  flags=(IsInteger)
 227500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+158    :   mrs   x4, mpidr_el1      : IntAlu :  D=0x0000000080000004  FetchSeq=17  CPSeq=8  flags=(IsInteger|IsSerializeBefore)
 237500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+142    :   orr   x0, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=13  CPSeq=4  flags=(IsInteger)
 237500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+146    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=14  CPSeq=5  flags=(IsInteger)
 237500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+150    :   orr   x2, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=15  CPSeq=6  flags=(IsInteger)
 237500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+154    :   orr   x3, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=16  CPSeq=7  flags=(IsInteger)
 237500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+158    :   mrs   x4, mpidr_el1      : IntAlu :  D=0x0000000080000005  FetchSeq=17  CPSeq=8  flags=(IsInteger|IsSerializeBefore)
 247500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+142    :   orr   x0, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=13  CPSeq=4  flags=(IsInteger)
 247500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+146    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=14  CPSeq=5  flags=(IsInteger)
 247500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+150    :   orr   x2, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=15  CPSeq=6  flags=(IsInteger)
 247500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+154    :   orr   x3, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=16  CPSeq=7  flags=(IsInteger)
 247500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+158    :   mrs   x4, mpidr_el1      : IntAlu :  D=0x0000000080000006  FetchSeq=17  CPSeq=8  flags=(IsInteger|IsSerializeBefore)
 252500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+142    :   orr   x0, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=13  CPSeq=4  flags=(IsInteger)
 252500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+146    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=14  CPSeq=5  flags=(IsInteger)
 252500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+150    :   orr   x2, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=15  CPSeq=6  flags=(IsInteger)
 252500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+154    :   orr   x3, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=16  CPSeq=7  flags=(IsInteger)
 252500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+158    :   mrs   x4, mpidr_el1      : IntAlu :  D=0x0000000080000007  FetchSeq=17  CPSeq=8  flags=(IsInteger|IsSerializeBefore)
 187500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+162    :   ldr   w1, #264           : MemRead :  D=0x000000ff00ffffff A=0x108  FetchSeq=18  CPSeq=9  flags=(IsInteger|IsMemRef|IsLoad)
 187500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+166    :   ands   x4, x1            : IntAlu :  D=0x0000000000000000  FetchSeq=19  CPSeq=10  flags=(IsInteger)
 187500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+170    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=20  CPSeq=11  flags=(IsInteger)
 188000: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+174    :   b.eq   <_kernel_flags_le_lo32+198> : IntAlu :   FetchSeq=21  CPSeq=12  flags=(IsControl|IsDirectControl|IsCondControl)
 188000: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=22  CPSeq=13  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 207500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+162    :   ldr   w1, #264           : MemRead :  D=0x000000ff00ffffff A=0x108  FetchSeq=18  CPSeq=9  flags=(IsInteger|IsMemRef|IsLoad)
 207500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+166    :   ands   x4, x1            : IntAlu :  D=0x0000000000000000  FetchSeq=19  CPSeq=10  flags=(IsInteger)
 207500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+170    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=20  CPSeq=11  flags=(IsInteger)
 208000: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+174    :   b.eq   <_kernel_flags_le_lo32+198> : IntAlu :   FetchSeq=21  CPSeq=12  flags=(IsControl|IsDirectControl|IsCondControl)
 208000: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=22  CPSeq=13  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 217500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+162    :   ldr   w1, #264           : MemRead :  D=0x000000ff00ffffff A=0x108  FetchSeq=18  CPSeq=9  flags=(IsInteger|IsMemRef|IsLoad)
 217500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+166    :   ands   x4, x1            : IntAlu :  D=0x0000000000000000  FetchSeq=19  CPSeq=10  flags=(IsInteger)
 217500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+170    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=20  CPSeq=11  flags=(IsInteger)
 218000: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+174    :   b.eq   <_kernel_flags_le_lo32+198> : IntAlu :   FetchSeq=21  CPSeq=12  flags=(IsControl|IsDirectControl|IsCondControl)
 218000: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=22  CPSeq=13  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 227500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+162    :   ldr   w1, #264           : MemRead :  D=0x000000ff00ffffff A=0x108  FetchSeq=18  CPSeq=9  flags=(IsInteger|IsMemRef|IsLoad)
 227500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+166    :   ands   x4, x1            : IntAlu :  D=0x0000000000000000  FetchSeq=19  CPSeq=10  flags=(IsInteger)
 227500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+170    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=20  CPSeq=11  flags=(IsInteger)
 228000: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+174    :   b.eq   <_kernel_flags_le_lo32+198> : IntAlu :   FetchSeq=21  CPSeq=12  flags=(IsControl|IsDirectControl|IsCondControl)
 228000: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=22  CPSeq=13  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 237500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+162    :   ldr   w1, #264           : MemRead :  D=0x000000ff00ffffff A=0x108  FetchSeq=18  CPSeq=9  flags=(IsInteger|IsMemRef|IsLoad)
 237500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+166    :   ands   x4, x1            : IntAlu :  D=0x0000000000000000  FetchSeq=19  CPSeq=10  flags=(IsInteger)
 237500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+170    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=20  CPSeq=11  flags=(IsInteger)
 238000: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+174    :   b.eq   <_kernel_flags_le_lo32+198> : IntAlu :   FetchSeq=21  CPSeq=12  flags=(IsControl|IsDirectControl|IsCondControl)
 238000: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=22  CPSeq=13  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 247500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+162    :   ldr   w1, #264           : MemRead :  D=0x000000ff00ffffff A=0x108  FetchSeq=18  CPSeq=9  flags=(IsInteger|IsMemRef|IsLoad)
 247500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+166    :   ands   x4, x1            : IntAlu :  D=0x0000000000000000  FetchSeq=19  CPSeq=10  flags=(IsInteger)
 247500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+170    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=20  CPSeq=11  flags=(IsInteger)
 248000: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+174    :   b.eq   <_kernel_flags_le_lo32+198> : IntAlu :   FetchSeq=21  CPSeq=12  flags=(IsControl|IsDirectControl|IsCondControl)
 248000: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=22  CPSeq=13  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 252500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+162    :   ldr   w1, #264           : MemRead :  D=0x000000ff00ffffff A=0x108  FetchSeq=18  CPSeq=9  flags=(IsInteger|IsMemRef|IsLoad)
 252500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+166    :   ands   x4, x1            : IntAlu :  D=0x0000000000000000  FetchSeq=19  CPSeq=10  flags=(IsInteger)
 252500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+170    :   orr   x1, xzr, xzr       : IntAlu :  D=0x0000000000000000  FetchSeq=20  CPSeq=11  flags=(IsInteger)
 253000: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+174    :   b.eq   <_kernel_flags_le_lo32+198> : IntAlu :   FetchSeq=21  CPSeq=12  flags=(IsControl|IsDirectControl|IsCondControl)
 253000: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=22  CPSeq=13  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 334500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=23  CPSeq=14  flags=(IsInteger|IsMemRef|IsLoad)
 354500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=23  CPSeq=14  flags=(IsInteger|IsMemRef|IsLoad)
 364500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=23  CPSeq=14  flags=(IsInteger|IsMemRef|IsLoad)
 374500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=23  CPSeq=14  flags=(IsInteger|IsMemRef|IsLoad)
 384500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=23  CPSeq=14  flags=(IsInteger|IsMemRef|IsLoad)
 394500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=23  CPSeq=14  flags=(IsInteger|IsMemRef|IsLoad)
 399500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=23  CPSeq=14  flags=(IsInteger|IsMemRef|IsLoad)
 334500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x0000000000000000 A=0x8000fff8  FetchSeq=24  CPSeq=15  flags=(IsInteger|IsMemRef|IsLoad)
 334500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=25  CPSeq=16  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
 354500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x0000000000000000 A=0x8000fff8  FetchSeq=24  CPSeq=15  flags=(IsInteger|IsMemRef|IsLoad)
 354500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=25  CPSeq=16  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
 364500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x0000000000000000 A=0x8000fff8  FetchSeq=24  CPSeq=15  flags=(IsInteger|IsMemRef|IsLoad)
 364500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=25  CPSeq=16  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
 374500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x0000000000000000 A=0x8000fff8  FetchSeq=24  CPSeq=15  flags=(IsInteger|IsMemRef|IsLoad)
 374500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=25  CPSeq=16  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
 384500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x0000000000000000 A=0x8000fff8  FetchSeq=24  CPSeq=15  flags=(IsInteger|IsMemRef|IsLoad)
 384500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=25  CPSeq=16  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
 394500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x0000000000000000 A=0x8000fff8  FetchSeq=24  CPSeq=15  flags=(IsInteger|IsMemRef|IsLoad)
 394500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=25  CPSeq=16  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
 399500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x0000000000000000 A=0x8000fff8  FetchSeq=24  CPSeq=15  flags=(IsInteger|IsMemRef|IsLoad)
 399500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=25  CPSeq=16  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
 567500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=74  CPSeq=17  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 577500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=74  CPSeq=17  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 587500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=74  CPSeq=17  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 597500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=74  CPSeq=17  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 607500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=74  CPSeq=17  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 617500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=74  CPSeq=17  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
 627500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+178    :   wfe                      : IntAlu :  D=0x0000000000000000  FetchSeq=74  CPSeq=17  flags=(IsSerializeAfter|IsNonSpeculative|IsQuiesce|IsUnverifiable)
7305644500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=75  CPSeq=18  flags=(IsInteger|IsMemRef|IsLoad)
7305649500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=75  CPSeq=18  flags=(IsInteger|IsMemRef|IsLoad)
7305654500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=75  CPSeq=18  flags=(IsInteger|IsMemRef|IsLoad)
7305659500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=75  CPSeq=18  flags=(IsInteger|IsMemRef|IsLoad)
7305664500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=75  CPSeq=18  flags=(IsInteger|IsMemRef|IsLoad)
7305669500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=75  CPSeq=18  flags=(IsInteger|IsMemRef|IsLoad)
7305674500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+182    :   ldr   w4, #304           : MemRead :  D=0x000000008000fff8 A=0x130  FetchSeq=75  CPSeq=18  flags=(IsInteger|IsMemRef|IsLoad)
7305644500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x00000000807371a0 A=0x8000fff8  FetchSeq=76  CPSeq=19  flags=(IsInteger|IsMemRef|IsLoad)
7305644500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=77  CPSeq=20  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7305644500: ExecEnable: system.cpu1: A0 T0 : @_kernel_flags_le_lo32+194    :   br   x4                  : IntAlu :   FetchSeq=78  CPSeq=21  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl)
7305649500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x00000000807371a0 A=0x8000fff8  FetchSeq=76  CPSeq=19  flags=(IsInteger|IsMemRef|IsLoad)
7305649500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=77  CPSeq=20  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7305649500: ExecEnable: system.cpu2: A0 T0 : @_kernel_flags_le_lo32+194    :   br   x4                  : IntAlu :   FetchSeq=78  CPSeq=21  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl)
7305654500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x00000000807371a0 A=0x8000fff8  FetchSeq=76  CPSeq=19  flags=(IsInteger|IsMemRef|IsLoad)
7305654500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=77  CPSeq=20  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7305654500: ExecEnable: system.cpu3: A0 T0 : @_kernel_flags_le_lo32+194    :   br   x4                  : IntAlu :   FetchSeq=78  CPSeq=21  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl)
7305659500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x00000000807371a0 A=0x8000fff8  FetchSeq=76  CPSeq=19  flags=(IsInteger|IsMemRef|IsLoad)
7305659500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=77  CPSeq=20  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7305659500: ExecEnable: system.cpu4: A0 T0 : @_kernel_flags_le_lo32+194    :   br   x4                  : IntAlu :   FetchSeq=78  CPSeq=21  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl)
7305664500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x00000000807371a0 A=0x8000fff8  FetchSeq=76  CPSeq=19  flags=(IsInteger|IsMemRef|IsLoad)
7305664500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=77  CPSeq=20  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7305664500: ExecEnable: system.cpu5: A0 T0 : @_kernel_flags_le_lo32+194    :   br   x4                  : IntAlu :   FetchSeq=78  CPSeq=21  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl)
7305669500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x00000000807371a0 A=0x8000fff8  FetchSeq=76  CPSeq=19  flags=(IsInteger|IsMemRef|IsLoad)
7305669500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=77  CPSeq=20  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7305669500: ExecEnable: system.cpu6: A0 T0 : @_kernel_flags_le_lo32+194    :   br   x4                  : IntAlu :   FetchSeq=78  CPSeq=21  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl)
7305674500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+186    :   ldr   x4, [x4]           : MemRead :  D=0x00000000807371a0 A=0x8000fff8  FetchSeq=76  CPSeq=19  flags=(IsInteger|IsMemRef|IsLoad)
7305674500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+190    :   cbz   x4, <_kernel_flags_le_lo32+178> : IntAlu :   FetchSeq=77  CPSeq=20  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7305674500: ExecEnable: system.cpu7: A0 T0 : @_kernel_flags_le_lo32+194    :   br   x4                  : IntAlu :   FetchSeq=78  CPSeq=21  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl)
7305955500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375200    :   bl   <arch_find_n_match_cpu_physical_id> : IntAlu :  D=0x00000000807371a4  FetchSeq=142  CPSeq=22  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7305960500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375200    :   bl   <arch_find_n_match_cpu_physical_id> : IntAlu :  D=0x00000000807371a4  FetchSeq=142  CPSeq=22  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7305970500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375200    :   bl   <arch_find_n_match_cpu_physical_id> : IntAlu :  D=0x00000000807371a4  FetchSeq=142  CPSeq=22  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7305980500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375200    :   bl   <arch_find_n_match_cpu_physical_id> : IntAlu :  D=0x00000000807371a4  FetchSeq=142  CPSeq=22  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7305985500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375200    :   bl   <arch_find_n_match_cpu_physical_id> : IntAlu :  D=0x00000000807371a4  FetchSeq=142  CPSeq=22  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7305990500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375200    :   bl   <arch_find_n_match_cpu_physical_id> : IntAlu :  D=0x00000000807371a4  FetchSeq=142  CPSeq=22  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7305995500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375200    :   bl   <arch_find_n_match_cpu_physical_id> : IntAlu :  D=0x00000000807371a4  FetchSeq=142  CPSeq=22  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306038500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374792    :   msr   spsel, #0x1        : IntAlu :  D=0x0000000000000001  FetchSeq=150  CPSeq=23  flags=(IsSerializeAfter|IsNonSpeculative)
7306038500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374796    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=151  CPSeq=24  flags=(IsInteger|IsSerializeBefore)
7306038500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374800    :   subs   x0, #8            : IntAlu :  D=0x0000000000000000  FetchSeq=152  CPSeq=25  flags=(IsInteger)
7306038500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374804    :   b.eq   <_kernel_size_le_lo32+2144374832> : IntAlu :   FetchSeq=153  CPSeq=26  flags=(IsControl|IsDirectControl|IsCondControl)
7306038500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374808    :   movz   x0, #12368, #16   : IntAlu :  D=0x0000000030500000  FetchSeq=154  CPSeq=27  flags=(IsInteger)
7306038500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374812    :   movk   x0, #2048, #0     : IntAlu :  D=0x0000000030500800  FetchSeq=155  CPSeq=28  flags=(IsInteger)
7306038500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374816    :   msr   sctlr_el1, x0      : IntAlu :  D=0x0000000030500800  FetchSeq=156  CPSeq=29  flags=(IsInteger|IsSerializeAfter|IsNonSpeculative)
7306048500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374792    :   msr   spsel, #0x1        : IntAlu :  D=0x0000000000000001  FetchSeq=150  CPSeq=23  flags=(IsSerializeAfter|IsNonSpeculative)
7306038500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374820    :   movz   w0, #3601, #0     : IntAlu :  D=0x0000000000000e11  FetchSeq=157  CPSeq=30  flags=(IsInteger)
7306039000: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374824    :   isb                      : IntAlu :   FetchSeq=158  CPSeq=31  flags=(IsSquashAfter)
7306048500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374796    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=151  CPSeq=24  flags=(IsInteger|IsSerializeBefore)
7306048500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374800    :   subs   x0, #8            : IntAlu :  D=0x0000000000000000  FetchSeq=152  CPSeq=25  flags=(IsInteger)
7306048500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374804    :   b.eq   <_kernel_size_le_lo32+2144374832> : IntAlu :   FetchSeq=153  CPSeq=26  flags=(IsControl|IsDirectControl|IsCondControl)
7306048500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374808    :   movz   x0, #12368, #16   : IntAlu :  D=0x0000000030500000  FetchSeq=154  CPSeq=27  flags=(IsInteger)
7306048500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374812    :   movk   x0, #2048, #0     : IntAlu :  D=0x0000000030500800  FetchSeq=155  CPSeq=28  flags=(IsInteger)
7306048500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374816    :   msr   sctlr_el1, x0      : IntAlu :  D=0x0000000030500800  FetchSeq=156  CPSeq=29  flags=(IsInteger|IsSerializeAfter|IsNonSpeculative)
7306058500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374792    :   msr   spsel, #0x1        : IntAlu :  D=0x0000000000000001  FetchSeq=150  CPSeq=23  flags=(IsSerializeAfter|IsNonSpeculative)
7306048500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374820    :   movz   w0, #3601, #0     : IntAlu :  D=0x0000000000000e11  FetchSeq=157  CPSeq=30  flags=(IsInteger)
7306049000: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374824    :   isb                      : IntAlu :   FetchSeq=158  CPSeq=31  flags=(IsSquashAfter)
7306058500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374796    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=151  CPSeq=24  flags=(IsInteger|IsSerializeBefore)
7306058500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374800    :   subs   x0, #8            : IntAlu :  D=0x0000000000000000  FetchSeq=152  CPSeq=25  flags=(IsInteger)
7306058500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374804    :   b.eq   <_kernel_size_le_lo32+2144374832> : IntAlu :   FetchSeq=153  CPSeq=26  flags=(IsControl|IsDirectControl|IsCondControl)
7306058500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374808    :   movz   x0, #12368, #16   : IntAlu :  D=0x0000000030500000  FetchSeq=154  CPSeq=27  flags=(IsInteger)
7306058500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374812    :   movk   x0, #2048, #0     : IntAlu :  D=0x0000000030500800  FetchSeq=155  CPSeq=28  flags=(IsInteger)
7306058500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374816    :   msr   sctlr_el1, x0      : IntAlu :  D=0x0000000030500800  FetchSeq=156  CPSeq=29  flags=(IsInteger|IsSerializeAfter|IsNonSpeculative)
7306068500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374792    :   msr   spsel, #0x1        : IntAlu :  D=0x0000000000000001  FetchSeq=150  CPSeq=23  flags=(IsSerializeAfter|IsNonSpeculative)
7306058500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374820    :   movz   w0, #3601, #0     : IntAlu :  D=0x0000000000000e11  FetchSeq=157  CPSeq=30  flags=(IsInteger)
7306059000: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374824    :   isb                      : IntAlu :   FetchSeq=158  CPSeq=31  flags=(IsSquashAfter)
7306068500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374796    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=151  CPSeq=24  flags=(IsInteger|IsSerializeBefore)
7306068500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374800    :   subs   x0, #8            : IntAlu :  D=0x0000000000000000  FetchSeq=152  CPSeq=25  flags=(IsInteger)
7306068500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374804    :   b.eq   <_kernel_size_le_lo32+2144374832> : IntAlu :   FetchSeq=153  CPSeq=26  flags=(IsControl|IsDirectControl|IsCondControl)
7306068500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374808    :   movz   x0, #12368, #16   : IntAlu :  D=0x0000000030500000  FetchSeq=154  CPSeq=27  flags=(IsInteger)
7306068500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374812    :   movk   x0, #2048, #0     : IntAlu :  D=0x0000000030500800  FetchSeq=155  CPSeq=28  flags=(IsInteger)
7306068500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374816    :   msr   sctlr_el1, x0      : IntAlu :  D=0x0000000030500800  FetchSeq=156  CPSeq=29  flags=(IsInteger|IsSerializeAfter|IsNonSpeculative)
7306068500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374820    :   movz   w0, #3601, #0     : IntAlu :  D=0x0000000000000e11  FetchSeq=157  CPSeq=30  flags=(IsInteger)
7306069000: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374824    :   isb                      : IntAlu :   FetchSeq=158  CPSeq=31  flags=(IsSquashAfter)
7306108500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374792    :   msr   spsel, #0x1        : IntAlu :  D=0x0000000000000001  FetchSeq=150  CPSeq=23  flags=(IsSerializeAfter|IsNonSpeculative)
7306108500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374796    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=151  CPSeq=24  flags=(IsInteger|IsSerializeBefore)
7306108500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374800    :   subs   x0, #8            : IntAlu :  D=0x0000000000000000  FetchSeq=152  CPSeq=25  flags=(IsInteger)
7306108500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374804    :   b.eq   <_kernel_size_le_lo32+2144374832> : IntAlu :   FetchSeq=153  CPSeq=26  flags=(IsControl|IsDirectControl|IsCondControl)
7306108500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374808    :   movz   x0, #12368, #16   : IntAlu :  D=0x0000000030500000  FetchSeq=154  CPSeq=27  flags=(IsInteger)
7306108500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374812    :   movk   x0, #2048, #0     : IntAlu :  D=0x0000000030500800  FetchSeq=155  CPSeq=28  flags=(IsInteger)
7306108500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374816    :   msr   sctlr_el1, x0      : IntAlu :  D=0x0000000030500800  FetchSeq=156  CPSeq=29  flags=(IsInteger|IsSerializeAfter|IsNonSpeculative)
7306118500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374792    :   msr   spsel, #0x1        : IntAlu :  D=0x0000000000000001  FetchSeq=150  CPSeq=23  flags=(IsSerializeAfter|IsNonSpeculative)
7306108500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374820    :   movz   w0, #3601, #0     : IntAlu :  D=0x0000000000000e11  FetchSeq=157  CPSeq=30  flags=(IsInteger)
7306109000: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374824    :   isb                      : IntAlu :   FetchSeq=158  CPSeq=31  flags=(IsSquashAfter)
7306118500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374796    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=151  CPSeq=24  flags=(IsInteger|IsSerializeBefore)
7306118500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374800    :   subs   x0, #8            : IntAlu :  D=0x0000000000000000  FetchSeq=152  CPSeq=25  flags=(IsInteger)
7306118500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374804    :   b.eq   <_kernel_size_le_lo32+2144374832> : IntAlu :   FetchSeq=153  CPSeq=26  flags=(IsControl|IsDirectControl|IsCondControl)
7306118500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374808    :   movz   x0, #12368, #16   : IntAlu :  D=0x0000000030500000  FetchSeq=154  CPSeq=27  flags=(IsInteger)
7306118500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374812    :   movk   x0, #2048, #0     : IntAlu :  D=0x0000000030500800  FetchSeq=155  CPSeq=28  flags=(IsInteger)
7306118500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374816    :   msr   sctlr_el1, x0      : IntAlu :  D=0x0000000030500800  FetchSeq=156  CPSeq=29  flags=(IsInteger|IsSerializeAfter|IsNonSpeculative)
7306128500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374792    :   msr   spsel, #0x1        : IntAlu :  D=0x0000000000000001  FetchSeq=150  CPSeq=23  flags=(IsSerializeAfter|IsNonSpeculative)
7306118500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374820    :   movz   w0, #3601, #0     : IntAlu :  D=0x0000000000000e11  FetchSeq=157  CPSeq=30  flags=(IsInteger)
7306119000: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374824    :   isb                      : IntAlu :   FetchSeq=158  CPSeq=31  flags=(IsSquashAfter)
7306128500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374796    :   mrs   x0, currentel      : IntAlu :  D=0x0000000000000004  FetchSeq=151  CPSeq=24  flags=(IsInteger|IsSerializeBefore)
7306128500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374800    :   subs   x0, #8            : IntAlu :  D=0x0000000000000000  FetchSeq=152  CPSeq=25  flags=(IsInteger)
7306128500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374804    :   b.eq   <_kernel_size_le_lo32+2144374832> : IntAlu :   FetchSeq=153  CPSeq=26  flags=(IsControl|IsDirectControl|IsCondControl)
7306128500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374808    :   movz   x0, #12368, #16   : IntAlu :  D=0x0000000030500000  FetchSeq=154  CPSeq=27  flags=(IsInteger)
7306128500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374812    :   movk   x0, #2048, #0     : IntAlu :  D=0x0000000030500800  FetchSeq=155  CPSeq=28  flags=(IsInteger)
7306128500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374816    :   msr   sctlr_el1, x0      : IntAlu :  D=0x0000000030500800  FetchSeq=156  CPSeq=29  flags=(IsInteger|IsSerializeAfter|IsNonSpeculative)
7306128500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374820    :   movz   w0, #3601, #0     : IntAlu :  D=0x0000000000000e11  FetchSeq=157  CPSeq=30  flags=(IsInteger)
7306129000: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374824    :   isb                      : IntAlu :   FetchSeq=158  CPSeq=31  flags=(IsSquashAfter)
7306143500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144374828    :   ret                      : IntAlu :   FetchSeq=160  CPSeq=32  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306153500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144374828    :   ret                      : IntAlu :   FetchSeq=160  CPSeq=32  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306163500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144374828    :   ret                      : IntAlu :   FetchSeq=160  CPSeq=32  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306168500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144374828    :   ret                      : IntAlu :   FetchSeq=160  CPSeq=32  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306261500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144374828    :   ret                      : IntAlu :   FetchSeq=160  CPSeq=32  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306271500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144374828    :   ret                      : IntAlu :   FetchSeq=160  CPSeq=32  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306276500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375204    :   bl   <__memblock_alloc_base> : IntAlu :  D=0x00000000807371a8  FetchSeq=161  CPSeq=33  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306281500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144374828    :   ret                      : IntAlu :   FetchSeq=160  CPSeq=32  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306286500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375204    :   bl   <__memblock_alloc_base> : IntAlu :  D=0x00000000807371a8  FetchSeq=161  CPSeq=33  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306291500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375204    :   bl   <__memblock_alloc_base> : IntAlu :  D=0x00000000807371a8  FetchSeq=161  CPSeq=33  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306296500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375204    :   bl   <__memblock_alloc_base> : IntAlu :  D=0x00000000807371a8  FetchSeq=161  CPSeq=33  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306338500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375204    :   bl   <__memblock_alloc_base> : IntAlu :  D=0x00000000807371a8  FetchSeq=161  CPSeq=33  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306348500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375204    :   bl   <__memblock_alloc_base> : IntAlu :  D=0x00000000807371a8  FetchSeq=161  CPSeq=33  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306359500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375164    :   adrp   x1, #3379200      : IntAlu :  D=0x0000000080a70000  FetchSeq=168  CPSeq=34  flags=(IsInteger)
7306364500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375204    :   bl   <__memblock_alloc_base> : IntAlu :  D=0x00000000807371a8  FetchSeq=161  CPSeq=33  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306404500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375164    :   adrp   x1, #3379200      : IntAlu :  D=0x0000000080a70000  FetchSeq=168  CPSeq=34  flags=(IsInteger)
7306414500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375164    :   adrp   x1, #3379200      : IntAlu :  D=0x0000000080a70000  FetchSeq=168  CPSeq=34  flags=(IsInteger)
7306424500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375164    :   adrp   x1, #3379200      : IntAlu :  D=0x0000000080a70000  FetchSeq=168  CPSeq=34  flags=(IsInteger)
7306434500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375164    :   adrp   x1, #3379200      : IntAlu :  D=0x0000000080a70000  FetchSeq=168  CPSeq=34  flags=(IsInteger)
7306444500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375164    :   adrp   x1, #3379200      : IntAlu :  D=0x0000000080a70000  FetchSeq=168  CPSeq=34  flags=(IsInteger)
7306449500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306449500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306449500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306459500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375164    :   adrp   x1, #3379200      : IntAlu :  D=0x0000000080a70000  FetchSeq=168  CPSeq=34  flags=(IsInteger)
7306493500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306493500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306493500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306498500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306498500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306498500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306503500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306503500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306503500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306511500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306511500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306511500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306546500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306546500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306546500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306581500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306591500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306601500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375188    :   dmb                      : IntAlu :   FetchSeq=184  CPSeq=39  flags=(IsMemBarrier)
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375192    :   dc ivac   , x1           : MemWrite :  A=0x80a70800  FetchSeq=185  CPSeq=40  flags=(IsInteger|IsMemRef|IsStore)
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375196    :   ret                      : IntAlu :   FetchSeq=186  CPSeq=41  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306611500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)

The ones near @_kernel_flags_le_lo32 are form the gem5 bootloader, the others must be kernel. I don't know why their symbol is lost, but by grepping the kernel source, the entry seems to be secondary_holding_pen, and the last function where the crash happens is https://github.com/torvalds/linux/blob/v4.18/arch/arm64/kernel/head.S#L646:
/*
 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
 * in w0. See arch/arm64/include/asm/virt.h for more info.
 */
set_cpu_boot_mode_flag:
	adr_l	x1, __boot_cpu_mode
	cmp	w0, #BOOT_CPU_MODE_EL2
	b.ne	1f
	add	x1, x1, #4
1:	str	w0, [x1]			// This CPU has booted in EL1
	dmb	sy
	dc	ivac, x1			// Invalidate potentially stale cache line
	ret
ENDPROC(set_cpu_boot_mode_flag)

Near the crash at the end, we see that several CPUs are doing a store to a single memory address:
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306581500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306591500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306601500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375188    :   dmb                      : IntAlu :   FetchSeq=184  CPSeq=39  flags=(IsMemBarrier)
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375192    :   dc ivac   , x1           : MemWrite :  A=0x80a70800  FetchSeq=185  CPSeq=40  flags=(IsInteger|IsMemRef|IsStore)
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375196    :   ret                      : IntAlu :   FetchSeq=186  CPSeq=41  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306611500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)

CPU1 finishes first, and then proceeds to do some memory operations: dmb and dc ivac.
cpu5 is then the first CPU to do its str after those memory operations, so presumably they are the cause of the crash.

  
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## full_log_after_cpu1.txt
7306449500: Event: system.cpu1.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 111 executed @ 7306449500
7306449500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306449500
7306449500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306449500
7306449500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306450000
7306449500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306449500
7306449500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306450000
7306449500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306449500
7306449500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306450000
7306450000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306450000
7306450000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306450500
7306450000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306450000
7306450000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306450500
7306450000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306450000
7306450000: Cache: system.cpu1.icache: access for ReadReq [807371c0:807371ff] IF UC D=80a4acd38f550000d07a3fd5fd7f0000c4e07db301000000ace47db301000000150000000000000000f870d08f55000000000000000100000000000000000000 ptr=0x558fc9802480
7306450000: CachePort: system.cpu1.icache.mem_side: Scheduling send event at 7306451000
7306450000: Event: system.cpu1.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 113 scheduled @ 7306451000
7306450000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306450500
7306450500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306450500
7306450500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306451000
7306450500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306450500
7306450500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306451000
7306450500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306450500
7306450500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306451000
7306451000: Event: system.cpu1.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 113 executed @ 7306451000
7306451000: Cache: system.cpu1.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=80a4acd38f550000d07a3fd5fd7f0000c4e07db301000000ace47db301000000150000000000000000f870d08f55000000000000000100000000000000000000 ptr=0x558fc9802480
7306451000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[4] packet ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363435313030300a000000000001000090d4e9cd8f550000 ptr=0x558fc9802100
7306451000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[4] packet ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363435313030300a000000000001000090d4e9cd8f550000 ptr=0x558fc9802100
7306451000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[4] packet ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363435313030300a000000000001000090d4e9cd8f550000 ptr=0x558fc9802100 SF size: 0 lat: 0
7306451000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363435313030300a000000000001000090d4e9cd8f550000 ptr=0x558fc9802100
7306451000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363435313030300a000000000001000090d4e9cd8f550000 ptr=0x558fc9802100
7306451000: CachePort: system.l2.mem_side: Scheduling send event at 7306461500
7306451000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306451500
7306451000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306451000 to 7306451500
7306451000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306451000
7306451000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306451500
7306451000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306451000
7306451000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306451500
7306451000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306451000
7306451000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306451500
7306451500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306451500
7306451500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306451500
7306451500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306452000
7306451500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306451500
7306451500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306452000
7306451500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306451500
7306451500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306452000
7306451750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306451750
7306451750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306451750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 2
7306451750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306451750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600
7306451750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306456750
7306452000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306452000
7306452000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f980
7306452000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[28] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f980
7306452000: Event: system.tol2bus.slave[28]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1343 scheduled @ 7306452500
7306452000: Event: system.tol2bus.respLayer28.wrapped_function_event: EventFunctionWrapped 1344 scheduled @ 7306453500
7306452000: BaseXBar: system.tol2bus.respLayer28: The crossbar layer is now busy from tick 7306452000 to 7306453500
7306452000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306457000
7306452000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306452000
7306452000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306452500
7306452000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306452000
7306452000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306452500
7306452000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306452000
7306452000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306452500
7306452500: Event: system.tol2bus.slave[28]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1343 executed @ 7306452500
7306452500: Cache: system.cpu7.icache: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f980
7306452500: Event: system.cpu7.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 381 scheduled @ 7306454500
7306452500: CacheVerbose: system.cpu7.icache: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f980
7306452500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306452500
7306452500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306453000
7306452500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306452500
7306452500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306453000
7306452500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306452500
7306452500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306453000
7306453000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306453000
7306453000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306453500
7306453000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306453000
7306453000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306453500
7306453000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306453000
7306453000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306453500
7306453500: Event: system.tol2bus.respLayer28.wrapped_function_event: EventFunctionWrapped 1344 executed @ 7306453500
7306453500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306453500
7306449500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306449500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306449500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306453500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306454000
7306453500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306453500
7306453500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306454000
7306453500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306453500
7306453500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306454000
7306454000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306454000
7306454000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306454500
7306454000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306454000
7306454000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306454000
7306454000: Cache: system.cpu1.icache: access for ReadReq [80737180:807371bf] IF UC D=0024d4d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363435343030300a000000000001000090dbe9cd8f550000 ptr=0x558fd070f980
7306454000: CachePort: system.cpu1.icache.mem_side: Scheduling send event at 7306455000
7306454000: Event: system.cpu1.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 113 scheduled @ 7306455000
7306454000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306454500
7306454500: Event: system.cpu7.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 381 executed @ 7306454500
7306454500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306454500
7306454500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306455000
7306454500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306454500
7306454500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306455000
7306455000: Event: system.cpu1.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 113 executed @ 7306455000
7306455000: Cache: system.cpu1.icache: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=0024d4d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363435343030300a000000000001000090dbe9cd8f550000 ptr=0x558fd070f980
7306455000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[4] packet ReadReq [80737180:807371bf] IF UC D=4000d1d18f5500004100005421100091200000b9bf3f03d500fbd2d18f550000000003d28f550000a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80
7306455000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[4] packet ReadReq [80737180:807371bf] IF UC D=4000d1d18f5500004100005421100091200000b9bf3f03d500fbd2d18f550000000003d28f550000a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80
7306455000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[4] packet ReadReq [80737180:807371bf] IF UC D=4000d1d18f5500004100005421100091200000b9bf3f03d500fbd2d18f550000000003d28f550000a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80 SF size: 0 lat: 0
7306455000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=4000d1d18f5500004100005421100091200000b9bf3f03d500fbd2d18f550000000003d28f550000a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80
7306455000: Cache: system.l2: access for ReadReq [80737180:807371bf] IF UC D=4000d1d18f5500004100005421100091200000b9bf3f03d500fbd2d18f550000000003d28f550000a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80
7306455000: CachePort: system.l2.mem_side: Scheduling send event at 7306465500
7306455000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306455500
7306455000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306455000 to 7306455500
7306455000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306455000
7306455000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306455500
7306455000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306455000
7306455000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306455500
7306455500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306455500
7306455500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306455500
7306455500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306456000
7306455500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306455500
7306455500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306456000
7306456000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306456000
7306456000: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=c04bd2d18f5500000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fa00
7306456000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c00ad1d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070f280
7306456000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c00ad1d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070f280
7306456000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c00ad1d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070f280 SF size: 0 lat: 1
7306456000: CoherentXBar: system.membus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=c00ad1d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070f280
7306456000: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x80737180 size 64
7306456000: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306456000: DRAM: system.mem_ctrls: Address: 0x737180 Rank 1 Bank 3 Row 57
7306456000: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306456000: DRAM: system.mem_ctrls: Adding to read queue
7306456000: DRAM: system.mem_ctrls: Request scheduled immediately
7306456000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306456000
7306456000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306457000
7306456000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306456000 to 7306457000
7306456000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306461500
7306456000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306456000
7306456000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306456000: DRAM: system.mem_ctrls: Single request, going to a free rank
7306456000: DRAM: system.mem_ctrls: Timing access to addr 0x737180, rank/bank/row 1 3 57
7306456000: DRAM: system.mem_ctrls: Removing burstTick for 7306445000
7306456000: DRAM: system.mem_ctrls: Activate at tick 7306467250
7306456000: DRAM: system.mem_ctrls: Activate bank 3, rank 1 at tick 7306467250, now got 5 active
7306456000: Event: system.mem_ctrls_1.wrapped_function_event: EventFunctionWrapped 19 scheduled @ 7306467250
7306456000: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306481000
7306456000: DRAM: system.mem_ctrls: Access to 0x737180, ready at 7306499750 next burst at 7306486000.
7306456000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306458500
7306456000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306456000
7306456000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306456500
7306456000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306456000
7306456000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306456500
7306456500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306456500
7306456500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306457000
7306456500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306456500
7306456500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306457000
7306456750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306456750
7306456750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306456750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 2
7306456750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306456750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802900
7306456750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306464750
7306457000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306457000
7306457000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306457000
7306457000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737140:8073717f] IF UC D=218c60d3c10000b400f8779240111cd5df3f03d5e13f80d201121cd5a0caffd00000009100c01cd5a07880d200401cd53e401cd540c28152e0039fd6c11900b0 ptr=0x558fd070f480
7306457000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[28] packet ReadResp [80737140:8073717f] IF UC D=218c60d3c10000b400f8779240111cd5df3f03d5e13f80d201121cd5a0caffd00000009100c01cd5a07880d200401cd53e401cd540c28152e0039fd6c11900b0 ptr=0x558fd070f480
7306457000: Event: system.tol2bus.slave[28]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1343 scheduled @ 7306457500
7306457000: Event: system.tol2bus.respLayer28.wrapped_function_event: EventFunctionWrapped 1344 scheduled @ 7306458500
7306457000: BaseXBar: system.tol2bus.respLayer28: The crossbar layer is now busy from tick 7306457000 to 7306458500
7306457000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306457000
7306457000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306457500
7306457000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306457000
7306457000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306457500
7306457500: Event: system.tol2bus.slave[28]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1343 executed @ 7306457500
7306457500: Cache: system.cpu7.icache: recvTimingResp: Handling response ReadResp [80737140:8073717f] IF UC D=218c60d3c10000b400f8779240111cd5df3f03d5e13f80d201121cd5a0caffd00000009100c01cd5a07880d200401cd53e401cd540c28152e0039fd6c11900b0 ptr=0x558fd070f480
7306457500: Event: system.cpu7.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 381 scheduled @ 7306459500
7306457500: CacheVerbose: system.cpu7.icache: recvTimingResp: Leaving with ReadResp [80737140:8073717f] IF UC D=218c60d3c10000b400f8779240111cd5df3f03d5e13f80d201121cd5a0caffd00000009100c01cd5a07880d200401cd53e401cd540c28152e0039fd6c11900b0 ptr=0x558fd070f480
7306457500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306457500
7306457500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306458000
7306457500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306457500
7306457500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306458000
7306458000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306458000
7306458000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306458500
7306458000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306458000
7306458000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306458500
7306458500: Event: system.tol2bus.respLayer28.wrapped_function_event: EventFunctionWrapped 1344 executed @ 7306458500
7306458500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306458500
7306458500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306458500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306458500
7306458500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306459000
7306458500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306458500
7306458500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306459000
7306459000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306459000
7306459000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306459500
7306459000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306459000
7306459000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306459500
7306459500: Event: system.cpu7.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 381 executed @ 7306459500
7306459500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306459500
7306459500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306459500
7306459500: Cache: system.cpu7.icache: access for ReadReq [80737180:807371bf] IF UC D=0018d1d18f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363435393530300a00001cd540c28152e0039fd6c11900b0 ptr=0x558fc9802800
7306459500: CachePort: system.cpu7.icache.mem_side: Scheduling send event at 7306460500
7306459500: Event: system.cpu7.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 383 scheduled @ 7306460500
7306459500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306460000
7306459500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306459500
7306459500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306459500
7306459500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306460000
7306460000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306460000
7306460000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306460500
7306460000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306460000
7306460000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306460500
7306460500: Event: system.cpu7.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 383 executed @ 7306460500
7306460500: Cache: system.cpu7.icache: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=0018d1d18f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363435393530300a00001cd540c28152e0039fd6c11900b0 ptr=0x558fc9802800
7306460500: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[28] packet ReadReq [80737180:807371bf] IF UC D=0058d2d18f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363436303530300a00000000000000000000000000000000 ptr=0x558fd070f480
7306460500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[28] packet ReadReq [80737180:807371bf] IF UC D=0058d2d18f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363436303530300a00000000000000000000000000000000 ptr=0x558fd070f480
7306460500: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[28] packet ReadReq [80737180:807371bf] IF UC D=0058d2d18f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363436303530300a00000000000000000000000000000000 ptr=0x558fd070f480 SF size: 0 lat: 0
7306460500: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=0058d2d18f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363436303530300a00000000000000000000000000000000 ptr=0x558fd070f480
7306460500: Cache: system.l2: access for ReadReq [80737180:807371bf] IF UC D=0058d2d18f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363436303530300a00000000000000000000000000000000 ptr=0x558fd070f480
7306460500: CachePort: system.l2.mem_side: Scheduling send event at 7306471000
7306460500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306461000
7306460500: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306460500 to 7306461000
7306460500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306460500
7306460500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306461000
7306460500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306460500
7306460500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306461000
7306461000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306461000
7306461000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306461000
7306461000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306461500
7306461000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306461000
7306461000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306461500
7306461500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306461500
7306461500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363435313030300a000000000001000090d4e9cd8f550000 ptr=0x558fc9802100
7306461500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=00d382c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070f580
7306461500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=00d382c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070f580
7306461500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=00d382c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070f580 SF size: 0 lat: 1
7306461500: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=00d382c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070f580
7306461500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306461500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306461500: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306461500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306461500: DRAM: system.mem_ctrls: Adding to read queue
7306461500: DRAM: system.mem_ctrls: Request scheduled immediately
7306461500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306461500
7306461500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306463000
7306461500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306461500 to 7306463000
7306461500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306465500
7306461500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306461500
7306461500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306461500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306461500: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306461500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306486000
7306461500: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306504750 next burst at 7306491000.
7306461500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306463500
7306461500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306461500
7306461500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306462000
7306461500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306461500
7306461500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306462000
7306462000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306462000
7306462000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306462500
7306462000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306462000
7306462000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306462500
7306462500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306462500
7306462500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306463000
7306462500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306462500
7306462500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306463000
7306463000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306463000
7306463000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306463000
7306463000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306463500
7306463000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306463000
7306459500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375164    :   adrp   x1, #3379200      : IntAlu :  D=0x0000000080a70000  FetchSeq=168  CPSeq=34  flags=(IsInteger)
7306463000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306463500
7306463500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306463500
7306463500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306463500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306463500
7306463500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306464000
7306463500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306463500
7306463500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306464000
7306464000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306464000
7306464000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306464500
7306464000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306464000
7306464000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306464500
7306464500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306464500
7306464500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306465000
7306464500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306464500
7306464500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306465000
7306464750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306464750
7306464750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306464750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 2
7306464750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306464750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b00
7306464750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306499750
7306465000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306465000
7306465000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306465500
7306465000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306465000
7306465000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306465500
7306465500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306465500
7306465500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=4000d1d18f5500004100005421100091200000b9bf3f03d500fbd2d18f550000000003d28f550000a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80
7306465500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=0091d6d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802200
7306465500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=0091d6d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802200
7306465500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=0091d6d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802200 SF size: 0 lat: 1
7306465500: CoherentXBar: system.membus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=0091d6d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802200
7306465500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x80737180 size 64
7306465500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306465500: DRAM: system.mem_ctrls: Address: 0x737180 Rank 1 Bank 3 Row 57
7306465500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306465500: DRAM: system.mem_ctrls: Adding to read queue
7306465500: DRAM: system.mem_ctrls: Request scheduled immediately
7306465500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306465500
7306465500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306467000
7306465500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306465500 to 7306467000
7306465500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306471000
7306465500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306465500
7306465500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306465500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306465500: DRAM: system.mem_ctrls: Timing access to addr 0x737180, rank/bank/row 1 3 57
7306465500: DRAM: system.mem_ctrls: Removing burstTick for 7306465000
7306465500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306491000
7306465500: DRAM: system.mem_ctrls: Access to 0x737180, ready at 7306509750 next burst at 7306496000.
7306465500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306468500
7306465500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306465500
7306465500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306466000
7306465500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306465500
7306465500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306466000
7306466000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306466000
7306466000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306466500
7306466000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306466000
7306466000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306466500
7306466500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306466500
7306466500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306467000
7306466500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306466500
7306466500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306467000
7306467000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306467000
7306467000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306467000
7306467000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306467500
7306467000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306467000
7306467000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306467500
7306467250: Event: system.mem_ctrls_1.wrapped_function_event: EventFunctionWrapped 19 executed @ 7306467250
7306467250: Event: system.mem_ctrls_1.wrapped_function_event: EventFunctionWrapped 20 executed @ 7306467250
7306467250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306467250
7306467250: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadExResp [8ef8d000:8ef8d03f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9824000
7306467250: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadExResp [8ef8d000:8ef8d03f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9824000
7306467250: SnoopFilter: system.membus.snoop_filter: updateResponse:   old SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306467250: SnoopFilter: system.membus.snoop_filter: updateResponse:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306467250: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306470000
7306467250: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306473000
7306467250: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306467250 to 7306473000
7306467250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306474750
7306467500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306467500
7306467500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306468000
7306467500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306467500
7306467500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306468000
7306468000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306468000
7306468000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306468500
7306468000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306468000
7306468000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306468500
7306468500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306468500
7306468500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306468500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306468500
7306468500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306469000
7306468500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306468500
7306468500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306469000
7306469000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306469000
7306469000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306469500
7306469000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306469000
7306469500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306469500
7306469500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306470000
7306470000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306470000
7306470000: Cache: system.l2: recvTimingResp: Handling response ReadExResp [8ef8d000:8ef8d03f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9824000
7306470000: Cache: system.l2: Block for addr 0x8ef8d000 being updated in Cache
7306470000: CacheRepl: system.l2: Replacement victim: state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x23a2 set: 0x340 way: 0x1
7306470000: Cache: system.l2: Create Writeback WritebackDirty [8e88d000:8e88d03f] D= ptr=0x558fd070f800 writable: 1, dirty: 1
7306470000: Cache: system.l2: Block addr 0x8ef8d000 (ns) moving from state 0 (I) to state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x23be set: 0x340 way: 0x1
7306470000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306480000
7306470000: CoherentXBar: system.tol2bus: recvTimingSnoopReq: src system.tol2bus.master[0] packet WritebackDirty [8e88d000:8e88d03f] ES D= ptr=0x7ffdd53f7cd0
7306470000: SnoopFilter: system.tol2bus.snoop_filter: lookupSnoop: packet WritebackDirty [8e88d000:8e88d03f] ES D= ptr=0x7ffdd53f7cd0
7306470000: CoherentXBar: system.tol2bus: recvTimingSnoopReq: src system.tol2bus.master[0] packet WritebackDirty [8e88d000:8e88d03f] ES D= ptr=0x7ffdd53f7cd0 SF size: 0 lat: 0
7306470000: CoherentXBar: system.tol2bus: forwardTiming for WritebackDirty [8e88d000:8e88d03f] ES D= ptr=0x7ffdd53f7cd0
7306470000: CachePort: system.l2.mem_side: Scheduling send event at 7306480000
7306470000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadExResp [8ef8d000:8ef8d03f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9824000
7306470000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306470000
7306470000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306470500
7306470500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306470500
7306470500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306471000
7306471000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306471000
7306471000: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=0058d2d18f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363436303530300a00000000000000000000000000000000 ptr=0x558fd070f480
7306471000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=00ca82c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9824000
7306471000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=00ca82c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9824000
7306471000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=00ca82c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9824000 SF size: 0 lat: 1
7306471000: CoherentXBar: system.membus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=00ca82c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9824000
7306471000: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x80737180 size 64
7306471000: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306471000: DRAM: system.mem_ctrls: Address: 0x737180 Rank 1 Bank 3 Row 57
7306471000: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306471000: DRAM: system.mem_ctrls: Adding to read queue
7306471000: DRAM: system.mem_ctrls: Request scheduled immediately
7306471000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306471000
7306471000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306472000
7306471000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306471000 to 7306472000
7306471000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306480000
7306471000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306471000
7306471000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306471000: DRAM: system.mem_ctrls: Single request, going to a free rank
7306471000: DRAM: system.mem_ctrls: Timing access to addr 0x737180, rank/bank/row 1 3 57
7306471000: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306496000
7306471000: DRAM: system.mem_ctrls: Access to 0x737180, ready at 7306514750 next burst at 7306501000.
7306471000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306473500
7306471000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306471000
7306471000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306471500
7306471500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306471500
7306471500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306472000
7306472000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306472000
7306472000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306472000
7306472000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306472500
7306472500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306472500
7306472500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306473000
7306473000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306473000
7306473000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306473000
7306473000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306473500
7306473500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306473500
7306473500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306473500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306473500
7306473500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306474000
7306474000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306474000
7306474000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306474500
7306474500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306474500
7306474500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306475000
7306474750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306474750
7306474750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802300
7306474750: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802300
7306474750: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306477000
7306474750: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306480000
7306474750: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306474750 to 7306480000
7306474750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306479750
7306475000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306475000
7306475000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306475500
7306475500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306475500
7306475500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306476000
7306476000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306476000
7306476000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306476500
7306476500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306476500
7306476500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306477000
7306477000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306477000
7306477000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802300
7306477000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802300
7306477000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306477000
7306477000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306477500
7306477500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306477500
7306477500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306478000
7306478000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306478000
7306478000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306478500
7306478500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306478500
7306478500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306479000
7306479000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306479000
7306479000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306479500
7306479500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306479500
7306479500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306480000
7306479750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306479750
7306479750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600 BUSY
7306480000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306480000
7306480000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600
7306480000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600
7306480000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306482000
7306480000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306485000
7306480000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306480000 to 7306485000
7306480000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306484750
7306480000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306480000
7306480000: Cache: system.l2: sendWriteQueuePacket: write WritebackDirty [8e88d000:8e88d03f] D=000000000000000008d02800bfffffff08d02800bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f800
7306480000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WritebackDirty [8e88d000:8e88d03f] D=000000000000000008d02800bfffffff08d02800bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f800
7306480000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet WritebackDirty [8e88d000:8e88d03f] D=000000000000000008d02800bfffffff08d02800bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f800
7306480000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306480000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306480000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WritebackDirty [8e88d000:8e88d03f] D=000000000000000008d02800bfffffff08d02800bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f800 SF size: 0 lat: 1
7306480000: DRAM: system.mem_ctrls: recvTimingReq: request WritebackDirty addr 0x8e88d000 size 64
7306480000: DRAM: system.mem_ctrls: Write queue limit 64, current size 23, entries needed 1
7306480000: DRAM: system.mem_ctrls: Address: 0xe88d000 Rank 0 Bank 6 Row 1860
7306480000: DRAM: system.mem_ctrls: Adding to write queue
7306480000: DRAM: system.mem_ctrls: Responding to Address 0x8e88d000
7306480000: DRAM: system.mem_ctrls: Done: WritebackDirty [8e88d000:8e88d03f] D=000000000000000008d02800bfffffff08d02800bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f800
7306480000: DRAM: system.mem_ctrls: Request scheduled immediately
7306480000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306480000
7306480000: SnoopFilter: system.membus.snoop_filter: eraseIfNullEntry:   Removed SF entry.
7306480000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306485000
7306480000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306480000 to 7306485000
7306480000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306480000
7306480000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306480000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306480000
7306480000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadExResp [8ef8d000:8ef8d03f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f300
7306480000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[1] packet ReadExResp [8ef8d000:8ef8d03f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f300
7306480000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse:   old SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306480000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306480000: Event: system.tol2bus.slave[1]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1289 scheduled @ 7306480500
7306480000: Event: system.tol2bus.respLayer1.wrapped_function_event: EventFunctionWrapped 1290 scheduled @ 7306481500
7306480000: BaseXBar: system.tol2bus.respLayer1: The crossbar layer is now busy from tick 7306480000 to 7306481500
7306480000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306491000
7306480000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306480000
7306480000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306480500
7306480500: Event: system.tol2bus.slave[1]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1289 executed @ 7306480500
7306480500: Cache: system.cpu0.dcache: recvTimingResp: Handling response ReadExResp [8ef8d000:8ef8d03f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f300
7306480500: Cache: system.cpu0.dcache: Block for addr 0x8ef8d000 being updated in Cache
7306480500: CacheRepl: system.cpu0.dcache: Replacement victim: state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x140 way: 0x1
7306480500: Cache: system.cpu0.dcache: Create Writeback WritebackDirty [8d845000:8d84503f] D= ptr=0x558fc9802880 writable: 1, dirty: 1
7306480500: Cache: system.cpu0.dcache: Block addr 0x8ef8d000 (ns) moving from state 0 (I) to state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x11df1 set: 0x140 way: 0x1
7306480500: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8ef8d018:8ef8d01b] D=04000000 ptr=0x558fc9802180 (write)
7306480500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306481500
7306480500: CachePort: system.cpu0.dcache.mem_side: Scheduling send event at 7306481500
7306480500: Event: system.cpu0.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 55 scheduled @ 7306481500
7306480500: CacheVerbose: system.cpu0.dcache: recvTimingResp: Leaving with ReadExResp [8ef8d000:8ef8d03f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f300
7306480500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306480500
7306480500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306481000
7306481000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306481000
7306481000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306481500
7306481500: Event: system.cpu0.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 55 executed @ 7306481500
7306481500: Cache: system.cpu0.dcache: sendWriteQueuePacket: write WritebackDirty [8d845000:8d84503f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9802880
7306481500: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[1] packet WritebackDirty [8d845000:8d84503f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9802880
7306481500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[1] packet WritebackDirty [8d845000:8d84503f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9802880
7306481500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306481500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306481500: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[1] packet WritebackDirty [8d845000:8d84503f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9802880 SF size: 0 lat: 0
7306481500: Cache: system.l2: access for WritebackDirty [8d845000:8d84503f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9802880 miss
7306481500: CacheRepl: system.l2: Replacement victim: state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x23a0 set: 0x140 way: 0x4
7306481500: Cache: system.l2: Create Writeback WritebackDirty [8e805000:8e80503f] D= ptr=0x558fd070f300 writable: 1, dirty: 1
7306481500: Cache: system.l2: access new state is state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x2361 set: 0x140 way: 0x4
7306481500: CoherentXBar: system.tol2bus: recvTimingSnoopReq: src system.tol2bus.master[0] packet WritebackDirty [8e805000:8e80503f] ES D= ptr=0x7ffdd53f73a0
7306481500: SnoopFilter: system.tol2bus.snoop_filter: lookupSnoop: packet WritebackDirty [8e805000:8e80503f] ES D= ptr=0x7ffdd53f73a0
7306481500: CoherentXBar: system.tol2bus: recvTimingSnoopReq: src system.tol2bus.master[0] packet WritebackDirty [8e805000:8e80503f] ES D= ptr=0x7ffdd53f73a0 SF size: 0 lat: 0
7306481500: CoherentXBar: system.tol2bus: forwardTiming for WritebackDirty [8e805000:8e80503f] ES D= ptr=0x7ffdd53f73a0
7306481500: CachePort: system.l2.mem_side: Scheduling send event at 7306502000
7306481500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306502000
7306481500: Cache: system.l2: handleTimingReqHit satisfied WritebackDirty [8d845000:8d84503f] D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9802880, no response needed
7306481500: SnoopFilter: system.tol2bus.snoop_filter: eraseIfNullEntry:   Removed SF entry.
7306481500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306483000
7306481500: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306481500 to 7306483000
7306481500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306481500
7306481500: Event: system.tol2bus.respLayer1.wrapped_function_event: EventFunctionWrapped 1290 executed @ 7306481500
7306481500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306481500
7306481500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306482000
7306482000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306482000
7306482000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600
7306482000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600
7306482000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306482000
7306482000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306482500
7306482500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306482500
7306482500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306483000
7306483000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306483000
7306483000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306483000
7306483000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306483500
7306483500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306483500
7306483500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306484000
7306484000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306484000
7306484000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306484500
7306484500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306484500
7306484500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306485000
7306484750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306484750
7306484750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802900 BUSY
7306485000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306485000
7306485000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306485000
7306485000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802900
7306485000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802900
7306485000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306487000
7306485000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306490000
7306485000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306485000 to 7306490000
7306485000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306492750
7306485000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306485000
7306485000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306485500
7306485500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306485500
7306485500: Cache: system.cpu0.dcache: access for WriteReq [8d847dc0:8d847dc7] D=0400000000000000 ptr=0x558fd070f600 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306485500: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847dc0:8d847dc7] D=0400000000000000 ptr=0x558fd070f600 (write)
7306485500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306486500
7306485500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306486000
7306486000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306486000
7306486000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306486500
7306486500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306486500
7306486500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306486500
7306486500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306487000
7306487000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306487000
7306487000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802900
7306487000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802900
7306487000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306487000
7306487000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306487500
7306487500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306487500
7306487500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306488000
7306488000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306488000
7306488000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306488500
7306488500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306488500
7306488500: Cache: system.cpu0.dcache: access for ReadReq [8d860010:8d860013] D=802c6acf ptr=0x558fc9802900 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b0c set: 0 way: 0
7306488500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306489500
7306488500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306489000
7306489000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306489000
7306489000: Cache: system.cpu0.icache: access for ReadReq [80712540:8071257f] IF D=4010d1d18f5500000027d4d18f550000be40ca0000000000409d7dd08f550000000000000000000080b5eac88f55000020beeac88f5500000000000000000000 ptr=0x558fd070f600 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x201c4 set: 0x95 way: 0
7306489000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306490000
7306489000: Cache: system.cpu0.dcache: access for ReadReq [8ef31018:8ef3101b] D=48316acf ptr=0x558fc9802180 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11de6 set: 0x40 way: 0x1
7306489000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306489500
7306489500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306489500
7306489500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306490000
7306489500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306489500
7306489500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306490000
7306490000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306490000
7306490000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306490000
7306490000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306490000
7306490000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306490000
7306490000: Cache: system.cpu0.icache: access for ReadReq [80712580:807125bf] IF D=8055d2d18f550000205b38656638643031383a38656638643031625d20443d3034303030303030207074723d3078353538666339383032313830000000000000 ptr=0x558fd070f600 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x201c4 set: 0x96 way: 0
7306490000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306491000
7306490000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306490500
7306490500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306490500
7306490500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306491000
7306491000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306491000
7306491000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306491000
7306491000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f880
7306491000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[8] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f880
7306491000: Event: system.tol2bus.slave[8]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1303 scheduled @ 7306491500
7306491000: Event: system.tol2bus.respLayer8.wrapped_function_event: EventFunctionWrapped 1304 scheduled @ 7306492500
7306491000: BaseXBar: system.tol2bus.respLayer8: The crossbar layer is now busy from tick 7306491000 to 7306492500
7306491000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306496000
7306491000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306491000
7306491000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306491500
7306491500: Event: system.tol2bus.slave[8]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1303 executed @ 7306491500
7306491500: Cache: system.cpu2.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f880
7306491500: Event: system.cpu2.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 156 scheduled @ 7306493500
7306491500: CacheVerbose: system.cpu2.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f880
7306491500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306491500
7306491500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306492000
7306492000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306492000
7306492000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306492500
7306492500: Event: system.tol2bus.respLayer8.wrapped_function_event: EventFunctionWrapped 1304 executed @ 7306492500
7306492500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306492500
7306492500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306493000
7306492750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306492750
7306492750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b00
7306492750: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b00
7306492750: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306495000
7306492750: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306498000
7306492750: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306492750 to 7306498000
7306493000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306493000
7306493000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306493500
7306493500: Event: system.cpu2.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 156 executed @ 7306493500
7306493500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306493500
7306493500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306493500
7306493500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306494000
7306493500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306493500
7306493500: Cache: system.cpu0.icache: access for ReadReq [80994000:8099403f] IF D=400ad1d18f550000fd7bbda902008012fd030091f35301a9e0d01dd28f550000e07974d08f550000f50300aa1f2003d542040011012080d2e00315aa427c4093 ptr=0x558fc8fb7d00 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20265 set: 0 way: 0x1
7306493500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306494500
7306493500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306494000
7306494000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306494000
7306494000: Cache: system.cpu0.dcache: access for ReadReq [8d8602e0:8d8602e7] D=682d6acf8f550000 ptr=0x558fc9802180 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b0c set: 0xb way: 0
7306494000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306495000
7306494000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306494500
7306494000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306494000
7306494000: Cache: system.cpu2.icache: access for ReadReq [807371c0:807371ff] IF UC D=401b80c98f5500008014d1d18f5500001b41ca0000000000806d74d08f55000040cbd1d18f55000090b4eac88f55000090b7eac88f5500000000000000000000 ptr=0x558fd070f880
7306494000: CachePort: system.cpu2.icache.mem_side: Scheduling send event at 7306495000
7306494000: Event: system.cpu2.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 158 scheduled @ 7306495000
7306494000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306494500
7306494500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306494500
7306494500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306494500
7306494500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306495000
7306494500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306494500
7306494500: Cache: system.cpu0.icache: access for ReadReq [80993f80:80993fbf] IF D=00b2acd38f55000080b2acd38f5500001d41ca00000000002061d4d18f5500002093d0d18f55000028b0eac88f55000090b4eac88f550000001c0012fd7bc1a8 ptr=0x558fc8fb7d00 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20264 set: 0xfe way: 0
7306494500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306495500
7306494500: Cache: system.cpu0.dcache: access for ReadReq [807507f0:807507f7] D=78306acf8f550000 ptr=0x558fc9802900 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x100ea set: 0x1f way: 0x1
7306494500: Cache: system.cpu0.dcache: access for ReadReq [8d8602e8:8d8602ef] D=382e6acf8f550000 ptr=0x558fd070f600 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b0c set: 0xb way: 0
7306494500: Cache: system.cpu0.dcache: access for ReadReq [8d8602f0:8d8602f7] D=002f6acf8f550000 ptr=0x558fd070fd00 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b0c set: 0xb way: 0
7306494500: Cache: system.cpu0.dcache: access for ReadReq [8d8602f8:8d8602ff] D=30326acf8f550000 ptr=0x558fd070fe00 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b0c set: 0xb way: 0
7306494500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306495000
7306495000: Event: system.cpu2.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 158 executed @ 7306495000
7306495000: Cache: system.cpu2.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=401b80c98f5500008014d1d18f5500001b41ca0000000000806d74d08f55000040cbd1d18f55000090b4eac88f55000090b7eac88f5500000000000000000000 ptr=0x558fd070f880
7306495000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[8] packet ReadReq [807371c0:807371ff] IF UC D=c094d6d18f550000c01cd1d18f5500006d41ca0000000000000000000200ffff00000000f6ffff9798aceac88f550000b0afeac88f5500000000018ac31900d0 ptr=0x558fc9802d00
7306495000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[8] packet ReadReq [807371c0:807371ff] IF UC D=c094d6d18f550000c01cd1d18f5500006d41ca0000000000000000000200ffff00000000f6ffff9798aceac88f550000b0afeac88f5500000000018ac31900d0 ptr=0x558fc9802d00
7306495000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[8] packet ReadReq [807371c0:807371ff] IF UC D=c094d6d18f550000c01cd1d18f5500006d41ca0000000000000000000200ffff00000000f6ffff9798aceac88f550000b0afeac88f5500000000018ac31900d0 ptr=0x558fc9802d00 SF size: 0 lat: 0
7306495000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=c094d6d18f550000c01cd1d18f5500006d41ca0000000000000000000200ffff00000000f6ffff9798aceac88f550000b0afeac88f5500000000018ac31900d0 ptr=0x558fc9802d00
7306495000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=c094d6d18f550000c01cd1d18f5500006d41ca0000000000000000000200ffff00000000f6ffff9798aceac88f550000b0afeac88f5500000000018ac31900d0 ptr=0x558fc9802d00
7306495000: CachePort: system.l2.mem_side: Scheduling send event at 7306505500
7306495000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306495500
7306495000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306495000 to 7306495500
7306495000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306495000
7306495000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306495500
7306495000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306495000
7306495000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b00
7306495000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b00
7306495000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306495000
7306495000: Cache: system.cpu0.dcache: access for ReadReq [807507f8:807507ff] D=802d6acf8f550000 ptr=0x558fc9802b00 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x100ea set: 0x1f way: 0x1
7306495000: Cache: system.cpu0.dcache: access for ReadReq [80750800:80750807] D=102d6acf8f550000 ptr=0x558fd070fc80 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x100ea set: 0x20 way: 0x1
7306495000: Cache: system.cpu0.dcache: access for ReadReq [80750808:8075080f] D=782f6acf8f550000 ptr=0x558fc9824180 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x100ea set: 0x20 way: 0x1
7306495000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306495500
7306495000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306495000
7306495000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306495500
7306495500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306495500
7306495500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306495501
7306495500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306495500
7306495500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306495500
7306495500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306495500
7306495500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306496000
7306495500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306495500
7306495500: Cache: system.cpu0.icache: access for ReadReq [80714980:807149bf] IF D=80a6aed38f5500006374696f6e577261707065642031323835206578656375746564204020373330363439353530300a00b3eac88f55000010d8e9cd8f550000 ptr=0x558fc8fb7d00 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x201c5 set: 0x26 way: 0x1
7306495500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306496500
7306495500: Cache: system.cpu0.dcache: access for ReadReq [8d847dc0:8d847dc7] D=e02f6acf8f550000 ptr=0x558fc9802300 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306495500: Cache: system.cpu0.dcache: access for ReadReq [8d847db0:8d847dbf] D=d0f667d08f550000d0fa67d08f550000 ptr=0x558fd070f500 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f6 way: 0
7306495500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306496000
7306495501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306495501
7306495501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306495502
7306495502: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306495502
7306495502: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306495503
7306495503: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306495503
7306495503: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306496000
7306496000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306496000
7306496000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306496001
7306496000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306496000
7306496000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802700
7306496000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[12] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802700
7306496000: Event: system.tol2bus.slave[12]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1311 scheduled @ 7306496500
7306496000: Event: system.tol2bus.respLayer12.wrapped_function_event: EventFunctionWrapped 1312 scheduled @ 7306497500
7306496000: BaseXBar: system.tol2bus.respLayer12: The crossbar layer is now busy from tick 7306496000 to 7306497500
7306496000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306501000
7306496000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306496000
7306496000: Cache: system.cpu0.dcache: access for ReadReq [8d847df0:8d847dff] D=80fc67d08f550000b04d3ccd8f550000 ptr=0x558fc9802500 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306496000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306496500
7306496000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306496000
7306496000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306496500
7306496001: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306496001
7306496001: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306496002
7306496002: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306496002
7306496002: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306496500
7306496500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306496500
7306496500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306496501
7306496500: Event: system.tol2bus.slave[12]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1311 executed @ 7306496500
7306496500: Cache: system.cpu3.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802700
7306496500: Event: system.cpu3.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 201 scheduled @ 7306498500
7306496500: CacheVerbose: system.cpu3.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802700
7306496500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306496500
7306496500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306496500
7306496500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306497000
7306496500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306496500
7306496500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306497000
7306496501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306496501
7306496501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306497000
7306497000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306497000
7306497000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306497000
7306497000: Cache: system.cpu0.icache: access for ReadReq [803378c0:803378ff] IF D=0059d2d18f5500004021d4d18f5500007741ca0000000000000000000300ffff0000000020373330e0aceac88f55000080a9eac88f550000e0039fd6c11900b0 ptr=0x558fc9802180 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x200cd set: 0xe3 way: 0
7306497000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306498000
7306497000: Cache: system.cpu0.dcache: access for ReadReq [80934310:80934317] D=402f6acf8f550000 ptr=0x558fc8fb7d00 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x10126 set: 0x10c way: 0
7306497000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306498000
7306497000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306497500
7306497000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306497000
7306497000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306497500
7306497500: Event: system.tol2bus.respLayer12.wrapped_function_event: EventFunctionWrapped 1312 executed @ 7306497500
7306497500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306497500
7306493500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306493500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306493500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306497500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306498000
7306497500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306497500
7306497500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306498000
7306498000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306498000
7306498000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306498000
7306498000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306498000
7306498000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306498000
7306498000: Cache: system.cpu0.icache: access for ReadReq [80337900:8033793f] IF D=4006d1d18f550000c0df82c98f5500005141ca0000000000204a03d28f550000000000008f5500002834b2c98f55000080fab1c98f55000010d8e9cd8f550000 ptr=0x558fc9802180 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x200cd set: 0xe4 way: 0
7306498000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306499000
7306498000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306498500
7306498000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306498000
7306498000: Cache: system.cpu2.icache: access for ReadReq [80737180:807371bf] IF UC D=808dd6d18f5500009f0000ebc00000545f2003d5fcffff17e07074d08f550000a085d3d18f550000100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802b00
7306498000: CachePort: system.cpu2.icache.mem_side: Scheduling send event at 7306499000
7306498000: Event: system.cpu2.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 158 scheduled @ 7306499000
7306498000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306498500
7306498500: Event: system.cpu3.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 201 executed @ 7306498500
7306498500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306498500
7306498500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306498500
7306498500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306499000
7306498500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306498500
7306498500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306499000
7306498500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306498500
7306498500: Cache: system.cpu0.dcache: access for ReadReq [80743f88:80743f8f] D=48316acf8f550000 ptr=0x558fc8fb7c80 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x100e8 set: 0xfe way: 0
7306498500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306499500
7306498500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306499000
7306499000: Event: system.cpu2.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 158 executed @ 7306499000
7306499000: Cache: system.cpu2.icache: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=808dd6d18f5500009f0000ebc00000545f2003d5fcffff17e07074d08f550000a085d3d18f550000100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802b00
7306499000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[8] packet ReadReq [80737180:807371bf] IF UC D=40dd82c98f5500000018d1d18f5500001241ca000000000020aabfc98f550000000000008f55000030abeac88f55000030abeac88f5500000000000000000000 ptr=0x558fd070f600
7306499000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[8] packet ReadReq [80737180:807371bf] IF UC D=40dd82c98f5500000018d1d18f5500001241ca000000000020aabfc98f550000000000008f55000030abeac88f55000030abeac88f5500000000000000000000 ptr=0x558fd070f600
7306499000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[8] packet ReadReq [80737180:807371bf] IF UC D=40dd82c98f5500000018d1d18f5500001241ca000000000020aabfc98f550000000000008f55000030abeac88f55000030abeac88f5500000000000000000000 ptr=0x558fd070f600 SF size: 0 lat: 0
7306499000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=40dd82c98f5500000018d1d18f5500001241ca000000000020aabfc98f550000000000008f55000030abeac88f55000030abeac88f5500000000000000000000 ptr=0x558fd070f600
7306499000: Cache: system.l2: access for ReadReq [80737180:807371bf] IF UC D=40dd82c98f5500000018d1d18f5500001241ca000000000020aabfc98f550000000000008f55000030abeac88f55000030abeac88f5500000000000000000000 ptr=0x558fd070f600
7306499000: CachePort: system.l2.mem_side: Scheduling send event at 7306509500
7306499000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306499500
7306499000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306499000 to 7306499500
7306499000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306499000
7306499000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306499000
7306499000: Cache: system.cpu0.icache: access for ReadReq [80993f80:80993fbf] IF D=80abaed38f55000043fc46d3037863f8c30000b5420001913f0002eb68ffff54e00301aac0035fd66300c0da6310c0da6200028b3f0002eb2190829ae00301aa ptr=0x558fc9802180 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20264 set: 0xfe way: 0
7306499000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306500000
7306499000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306499500
7306499000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306499000
7306499000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306499500
7306499000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306499000
7306499000: Cache: system.cpu3.icache: access for ReadReq [807371c0:807371ff] IF UC D=801b80c98f5500000000000000000000000000000000000000f202d28f5500000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9802900
7306499000: CachePort: system.cpu3.icache.mem_side: Scheduling send event at 7306500000
7306499000: Event: system.cpu3.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 203 scheduled @ 7306500000
7306499000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306499500
7306499500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306499500
7306499500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306499500
7306499500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306499500
7306499500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306500000
7306499500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306499500
7306499500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306500000
7306499500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306499500
7306499500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306500000
7306499750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306499750
7306499750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306499750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 3
7306499750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306499750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306527750
7306499750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f280
7306499750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306504750
7306500000: Event: system.cpu3.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 203 executed @ 7306500000
7306500000: Cache: system.cpu3.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=801b80c98f5500000000000000000000000000000000000000f202d28f5500000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fc9802900
7306500000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[12] packet ReadReq [807371c0:807371ff] IF UC D=0053d2d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00cd8f550000 ptr=0x558fc9824180
7306500000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[12] packet ReadReq [807371c0:807371ff] IF UC D=0053d2d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00cd8f550000 ptr=0x558fc9824180
7306500000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[12] packet ReadReq [807371c0:807371ff] IF UC D=0053d2d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00cd8f550000 ptr=0x558fc9824180 SF size: 0 lat: 0
7306500000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=0053d2d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00cd8f550000 ptr=0x558fc9824180
7306500000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=0053d2d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00cd8f550000 ptr=0x558fc9824180
7306500000: CachePort: system.l2.mem_side: Scheduling send event at 7306510500
7306500000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306500500
7306500000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306500000 to 7306500500
7306500000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306500000
7306500000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306500000
7306500000: Cache: system.cpu0.icache: access for ReadReq [80714980:807149bf] IF D=c0b6acd38f550000c090d6d18f5500001e41ca000000000060acbfc98f55000000e0d4d18f550000f8b2eac88f55000078baeac88f5500000101010101010101 ptr=0x558fc9802180 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x201c5 set: 0x26 way: 0x1
7306500000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306501000
7306488500: ExecEnable: system.cpu0: A0 T0 : @smp_prepare_cpus+144    :   orr   w0, wzr, w19       : IntAlu :  D=0x0000000000000004  FetchSeq=13255061  CPSeq=11776595  flags=(IsInteger)
7306500000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306500500
7306500000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306500000
7306500000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306500500
7306500000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306500000
7306500000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306500500
7306500500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306500500
7306500500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306500500
7306500500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306501000
7306500500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306500500
7306500500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306501000
7306500500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306500500
7306500500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306501000
7306501000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306501000
7306501000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306501000
7306501000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fd80
7306501000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[16] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fd80
7306501000: Event: system.tol2bus.slave[16]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1319 scheduled @ 7306501500
7306501000: Event: system.tol2bus.respLayer16.wrapped_function_event: EventFunctionWrapped 1320 scheduled @ 7306502500
7306501000: BaseXBar: system.tol2bus.respLayer16: The crossbar layer is now busy from tick 7306501000 to 7306502500
7306501000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306509000
7306501000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306501000
7306501000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306501500
7306501000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306501000
7306501000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306501500
7306501000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306501000
7306501000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306501500
7306501500: Event: system.tol2bus.slave[16]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1319 executed @ 7306501500
7306501500: Cache: system.cpu4.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fd80
7306501500: Event: system.cpu4.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 246 scheduled @ 7306503500
7306501500: CacheVerbose: system.cpu4.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fd80
7306501500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306501500
7306501500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306502000
7306501500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306501500
7306501500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306502000
7306501500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306501500
7306501500: Cache: system.cpu0.icache: access for ReadReq [800932c0:800932ff] IF D=8019d1d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363530323030300a001fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fd80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20024 set: 0xcb way: 0x1
7306501500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306502500
7306488500: ExecEnable: system.cpu0: A0 T0 : @smp_prepare_cpus+148    :   cbz   x1, <smp_prepare_cpus+72> : IntAlu :   FetchSeq=13255062  CPSeq=11776596  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7306488500: ExecEnable: system.cpu0: A0 T0 : @smp_prepare_cpus+152    :   ldr   x1, [x1, #16]      : MemRead :  D=0xffffff80080932c0 A=0xffffff8008743f88  FetchSeq=13255063  CPSeq=11776597  flags=(IsInteger|IsMemRef|IsLoad)
7306488500: ExecEnable: system.cpu0: A0 T0 : @smp_prepare_cpus+156    :   blr   x1                 : IntAlu :  D=0xffffff8008993fec  FetchSeq=13255064  CPSeq=11776598  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsCall)
7306501500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306502000
7306502000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306502000
7306502000: Cache: system.l2: sendWriteQueuePacket: write WritebackDirty [8e805000:8e80503f] D=000000000000000008502000bfffffff08502000bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f300
7306502000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WritebackDirty [8e805000:8e80503f] D=000000000000000008502000bfffffff08502000bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f300
7306502000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet WritebackDirty [8e805000:8e80503f] D=000000000000000008502000bfffffff08502000bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f300
7306502000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306502000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306502000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WritebackDirty [8e805000:8e80503f] D=000000000000000008502000bfffffff08502000bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f300 SF size: 0 lat: 1
7306502000: DRAM: system.mem_ctrls: recvTimingReq: request WritebackDirty addr 0x8e805000 size 64
7306502000: DRAM: system.mem_ctrls: Write queue limit 64, current size 24, entries needed 1
7306502000: DRAM: system.mem_ctrls: Address: 0xe805000 Rank 0 Bank 2 Row 1856
7306502000: DRAM: system.mem_ctrls: Adding to write queue
7306502000: DRAM: system.mem_ctrls: Responding to Address 0x8e805000
7306502000: DRAM: system.mem_ctrls: Done: WritebackDirty [8e805000:8e80503f] D=000000000000000008502000bfffffff08502000bfffffff000000000000000000000000000000000000000000000000ffffffff000000000000000000000000 ptr=0x558fd070f300
7306502000: DRAM: system.mem_ctrls: Request scheduled immediately
7306502000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306502000
7306502000: SnoopFilter: system.membus.snoop_filter: eraseIfNullEntry:   Removed SF entry.
7306502000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306507000
7306502000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306502000 to 7306507000
7306502000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306505500
7306502000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306502000
7306502000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306502000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306502000
7306502000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306502500
7306502000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306502000
7306502000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306502500
7306502000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306502000
7306502000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306502500
7306502500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306502500
7306502500: Event: system.tol2bus.respLayer16.wrapped_function_event: EventFunctionWrapped 1320 executed @ 7306502500
7306502500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306502500
7306498500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306498500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306498500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306502500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306503000
7306502500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306502500
7306502500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306503000
7306502500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306502500
7306502500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306503000
7306503000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306503000
7306503000: Cache: system.cpu0.icache: access for ReadReq [8009b800:8009b83f] IF D=404bd2d18f550000602febc88f5500009841ca0000000000000000002100ffff0000000000000000a0b3eac88f55000078b4eac88f5500000000000000000000 ptr=0x558fd070fd80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20026 set: 0xe0 way: 0
7306503000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306504000
7306503000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306503500
7306503000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306503000
7306503000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306503500
7306503000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306503000
7306503000: Cache: system.cpu3.icache: access for ReadReq [80737180:807371bf] IF UC D=0098d6d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363530333530300a000314aa3f00176b69020054417877f8 ptr=0x558fc8fb7c80
7306503000: CachePort: system.cpu3.icache.mem_side: Scheduling send event at 7306504000
7306503000: Event: system.cpu3.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 203 scheduled @ 7306504000
7306503000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306503500
7306503500: Event: system.cpu4.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 246 executed @ 7306503500
7306503500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306503500
7306503500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306503500
7306503500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306504000
7306503500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306503500
7306503500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306504000
7306503500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306503500
7306503500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306503500
7306503500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306504000
7306504000: Event: system.cpu3.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 203 executed @ 7306504000
7306504000: Cache: system.cpu3.icache: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=0098d6d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363530333530300a000314aa3f00176b69020054417877f8 ptr=0x558fc8fb7c80
7306504000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[12] packet ReadReq [80737180:807371bf] IF UC D=0033d4d18f5500006374696f6e5772617070656420343632203c03d28f5500006564204020373330363438303030300a002035370a0000000000000000000000 ptr=0x558fc8fb7f80
7306504000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[12] packet ReadReq [80737180:807371bf] IF UC D=0033d4d18f5500006374696f6e5772617070656420343632203c03d28f5500006564204020373330363438303030300a002035370a0000000000000000000000 ptr=0x558fc8fb7f80
7306504000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[12] packet ReadReq [80737180:807371bf] IF UC D=0033d4d18f5500006374696f6e5772617070656420343632203c03d28f5500006564204020373330363438303030300a002035370a0000000000000000000000 ptr=0x558fc8fb7f80 SF size: 0 lat: 0
7306504000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=0033d4d18f5500006374696f6e5772617070656420343632203c03d28f5500006564204020373330363438303030300a002035370a0000000000000000000000 ptr=0x558fc8fb7f80
7306504000: Cache: system.l2: access for ReadReq [80737180:807371bf] IF UC D=0033d4d18f5500006374696f6e5772617070656420343632203c03d28f5500006564204020373330363438303030300a002035370a0000000000000000000000 ptr=0x558fc8fb7f80
7306504000: CachePort: system.l2.mem_side: Scheduling send event at 7306514500
7306504000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306504500
7306504000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306504000 to 7306504500
7306504000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306504000
7306504000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306504000
7306504000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306504500
7306504000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306504000
7306504000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306504500
7306504000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306504000
7306504000: Cache: system.cpu4.icache: access for ReadReq [807371c0:807371ff] IF UC D=c08fd6d18f5500006374696f6e5772617070656420323436207363686564756c6564204020373330363530333530300a0000b1c98f5500000000000000000000 ptr=0x558fd070fd80
7306504000: CachePort: system.cpu4.icache.mem_side: Scheduling send event at 7306505000
7306504000: Event: system.cpu4.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 248 scheduled @ 7306505000
7306504000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306504500
7306504500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306504500
7306504500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306504500
7306504500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306505000
7306504500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306504500
7306504500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306505000
7306504500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306504500
7306504500: Cache: system.cpu0.icache: access for ReadReq [8009b1c0:8009b1ff] IF D=001f80c98f550000401780c98f5500009041ca0000000000050000000200ffff000000008f5500009035b2c98f55000018f0b1c98f55000090bbb9cd8f550000 ptr=0x558fd070f800 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20026 set: 0xc7 way: 0
7306504500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306505500
7306504500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306505000
7306504750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306504750
7306504750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306504750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 2
7306504750: DRAM: system.mem_ctrls: Responding to Address 0x807371c0
7306504750: DRAM: system.mem_ctrls: Done: ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f580
7306504750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306509750
7306505000: Event: system.cpu4.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 248 executed @ 7306505000
7306505000: Cache: system.cpu4.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c08fd6d18f5500006374696f6e5772617070656420323436207363686564756c6564204020373330363530333530300a0000b1c98f5500000000000000000000 ptr=0x558fd070fd80
7306505000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[16] packet ReadReq [807371c0:807371ff] IF UC D=800ed1d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00d18f550000 ptr=0x558fc9802180
7306505000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[16] packet ReadReq [807371c0:807371ff] IF UC D=800ed1d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00d18f550000 ptr=0x558fc9802180
7306505000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[16] packet ReadReq [807371c0:807371ff] IF UC D=800ed1d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00d18f550000 ptr=0x558fc9802180 SF size: 0 lat: 0
7306505000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=800ed1d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00d18f550000 ptr=0x558fc9802180
7306505000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=800ed1d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00d18f550000 ptr=0x558fc9802180
7306505000: CachePort: system.l2.mem_side: Scheduling send event at 7306515500
7306505000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306505500
7306505000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306505000 to 7306505500
7306505000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306505000
7306505000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306505500
7306505000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306505000
7306505000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306505500
7306505000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306505000
7306505000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306505500
7306505500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306505500
7306505500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306505500
7306505500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306505500
7306505500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c094d6d18f550000c01cd1d18f5500006d41ca0000000000000000000200ffff00000000f6ffff9798aceac88f550000b0afeac88f5500000000018ac31900d0 ptr=0x558fc9802d00
7306505500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=001780c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070f800 BUSY
7306505500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306505500
7306505500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306506000
7306505500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306505500
7306505500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306506000
7306505500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306505500
7306505500: Cache: system.cpu0.icache: access for ReadReq [801ae300:801ae33f] IF D=c020d4d18f5500004045d2d18f5500008d41ca0000000000000000002000ffff000000008f55000048b4eac88f550000f8b8eac88f5500000000000000000000 ptr=0x558fd070f800 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x2006b set: 0x8c way: 0
7306505500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306506500
7306505500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306506000
7306506000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306506000
7306506000: Cache: system.cpu0.dcache: access for ReadReq [80a75798:80a7579f] D=f82f6acf8f550000 ptr=0x558fc8fb7d00 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x1014e set: 0x15e way: 0
7306506000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306507000
7306502500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare    :   adrp   x1, #10362880     : IntAlu :  D=0xffffff8008a75000  FetchSeq=13255106  CPSeq=11776599  flags=(IsInteger)
7306506000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306506500
7306506000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306506000
7306506000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306506500
7306506000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306506000
7306506000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306506500
7306506500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306506500
7306506500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306506500
7306506500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306507000
7306506500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306506500
7306506500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306507000
7306506500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306506500
7306506500: Cache: system.cpu0.icache: access for ReadReq [801ae340:801ae37f] IF D=400ad1d18f550000409bd6d18f5500008541ca0000000000050000000200ffff000000008f55000018f0b1c98f55000080d6b1c98f550000c0035fd61f2003d5 ptr=0x558fd070f800 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x2006b set: 0x8d way: 0x1
7306506500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306507500
7306502500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+4    :   add   x1, x1, #1912      : IntAlu :  D=0xffffff8008a75778  FetchSeq=13255107  CPSeq=11776600  flags=(IsInteger)
7306506500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306507000
7306507000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306507000
7306507000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306507000
7306507000: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c094d6d18f550000c01cd1d18f5500006d41ca0000000000000000000200ffff00000000f6ffff9798aceac88f550000b0afeac88f5500000000018ac31900d0 ptr=0x558fc9802d00
7306507000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=0021d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802500
7306507000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=0021d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802500
7306507000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=0021d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802500 SF size: 0 lat: 1
7306507000: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=0021d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802500
7306507000: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306507000: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306507000: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306507000: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306507000: DRAM: system.mem_ctrls: Adding to read queue
7306507000: DRAM: system.mem_ctrls: Request scheduled immediately
7306507000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306507000
7306507000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306508000
7306507000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306507000 to 7306508000
7306507000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306509500
7306507000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306507000
7306507000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306507000: DRAM: system.mem_ctrls: Single request, going to a free rank
7306507000: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306507000: DRAM: system.mem_ctrls: Removing burstTick for 7306495000
7306507000: DRAM: system.mem_ctrls: Removing burstTick for 7306490000
7306507000: DRAM: system.mem_ctrls: Removing burstTick for 7306485000
7306507000: DRAM: system.mem_ctrls: Removing burstTick for 7306480000
7306507000: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306507000
7306507000: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306525750 next burst at 7306512000.
7306507000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306507000
7306507000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306507000
7306507000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306507000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306507000
7306507000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306507500
7306507000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306507000
7306507000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306507500
7306507000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306507000
7306507000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306507500
7306507500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306507500
7306507500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306507500
7306503500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306503500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306503500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306507500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306508000
7306507500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306507500
7306507500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306508000
7306507500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306507500
7306507500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306508000
7306508000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306508000
7306508000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306508000
7306508000: Cache: system.cpu0.icache: access for ReadReq [801ae380:801ae3bf] IF D=00a6aed38f550000636365737320746f20616464722030783733373163302c2072616e6b2f62616e6b2f726f77203120332035370a0000000000000000000000 ptr=0x558fd070f800 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x2006b set: 0x8e way: 0x1
7306508000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306509000
7306502500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+8    :   ldr   x0, [x1, x0, UXTW #3] : MemRead :  D=0x000000008000fff8 A=0xffffff8008a75798  FetchSeq=13255108  CPSeq=11776601  flags=(IsInteger|IsMemRef|IsLoad)
7306508000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306508500
7306508000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306508000
7306508000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306508500
7306508000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306508000
7306508000: Cache: system.cpu4.icache: access for ReadReq [80737180:807371bf] IF UC D=00a6aed38f5500006374696f6e5772617070656420313834207363686564756c6564204020373330363530383530300a0098a3cc8f550000f35301a9452cf297 ptr=0x558fd070f500
7306508000: CachePort: system.cpu4.icache.mem_side: Scheduling send event at 7306509000
7306508000: Event: system.cpu4.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 248 scheduled @ 7306509000
7306508000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306508500
7306508500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306508500
7306508500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306509000
7306508500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306508500
7306508500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306508500
7306502500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+12    :   cbz   x0, <smp_spin_table_cpu_prepare+104> : IntAlu :   FetchSeq=13255109  CPSeq=11776602  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7306502500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+16    : stp
7306502500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+16. 0 :   addxi_uop   ureg0, sp, #-32 : IntAlu :  D=0xffffff8008043de0  FetchSeq=13255110  CPSeq=11776603  flags=(IsInteger|IsMicroop|IsDelayedCommit|IsFirstMicroop)
7306502500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+16. 1 :   strxi_uop   x29, [ureg0] : MemWrite :  D=0xffffff8008043e00 A=0xffffff8008043de0  FetchSeq=13255111  CPSeq=11776604  flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit)
7306502500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+16. 2 :   strxi_uop   x30, [ureg0, #8] : MemWrite :  D=0xffffff8008993fec A=0xffffff8008043de8  FetchSeq=13255112  CPSeq=11776605  flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit)
7306502500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+16. 3 :   addxi_uop   sp, ureg0, #0 : IntAlu :  D=0xffffff8008043de0  FetchSeq=13255113  CPSeq=11776606  flags=(IsInteger|IsMicroop|IsLastMicroop)
7306503000: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+20    :   movz   x1, #8, #0        : IntAlu :  D=0x0000000000000008  FetchSeq=13255114  CPSeq=11776607  flags=(IsInteger)
7306503000: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+24    :   add   x29, sp, #0        : IntAlu :  D=0xffffff8008043de0  FetchSeq=13255115  CPSeq=11776608  flags=(IsInteger)
7306503000: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+28    :   str   x19, [sp, #16]     : MemWrite :  D=0x0000000000000004 A=0xffffff8008043df0  FetchSeq=13255116  CPSeq=11776609  flags=(IsInteger|IsMemRef|IsStore)
7306508500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306509000
7306509000: Event: system.cpu4.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 248 executed @ 7306509000
7306509000: Cache: system.cpu4.icache: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=00a6aed38f5500006374696f6e5772617070656420313834207363686564756c6564204020373330363530383530300a0098a3cc8f550000f35301a9452cf297 ptr=0x558fd070f500
7306509000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[16] packet ReadReq [80737180:807371bf] IF UC D=c034d4d18f5500000091d6d18f550000c441ca0000000000000000000000ffff0000000020373330f0a8eac88f550000d0b3eac88f55000010d8e9cd8f550000 ptr=0x558fc8fb7d00
7306509000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[16] packet ReadReq [80737180:807371bf] IF UC D=c034d4d18f5500000091d6d18f550000c441ca0000000000000000000000ffff0000000020373330f0a8eac88f550000d0b3eac88f55000010d8e9cd8f550000 ptr=0x558fc8fb7d00
7306509000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[16] packet ReadReq [80737180:807371bf] IF UC D=c034d4d18f5500000091d6d18f550000c441ca0000000000000000000000ffff0000000020373330f0a8eac88f550000d0b3eac88f55000010d8e9cd8f550000 ptr=0x558fc8fb7d00 SF size: 0 lat: 0
7306509000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=c034d4d18f5500000091d6d18f550000c441ca0000000000000000000000ffff0000000020373330f0a8eac88f550000d0b3eac88f55000010d8e9cd8f550000 ptr=0x558fc8fb7d00
7306509000: Cache: system.l2: access for ReadReq [80737180:807371bf] IF UC D=c034d4d18f5500000091d6d18f550000c441ca0000000000000000000000ffff0000000020373330f0a8eac88f550000d0b3eac88f55000010d8e9cd8f550000 ptr=0x558fc8fb7d00
7306509000: CachePort: system.l2.mem_side: Scheduling send event at 7306519500
7306509000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306509500
7306509000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306509000 to 7306509500
7306509000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306509000
7306509000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306509000
7306509000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400
7306509000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[20] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400
7306509000: Event: system.tol2bus.slave[20]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1327 scheduled @ 7306509500
7306509000: Event: system.tol2bus.respLayer20.wrapped_function_event: EventFunctionWrapped 1328 scheduled @ 7306510500
7306509000: BaseXBar: system.tol2bus.respLayer20: The crossbar layer is now busy from tick 7306509000 to 7306510500
7306509000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306509000
7306509000: Cache: system.cpu0.icache: access for ReadReq [801ae340:801ae37f] IF D=0027d4d18f5500006374696f6e577261707065642031333238207363686564756c6564204020373330363531303530300a0004cd8f5500000000000000000000 ptr=0x558fd070f800 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x2006b set: 0x8d way: 0x1
7306509000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306510000
7306503000: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+32    :   bl   <ioremap_cache>     : IntAlu :  D=0xffffff80080932e4  FetchSeq=13255117  CPSeq=11776610  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache    : stp
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache. 0 :   addxi_uop   ureg0, sp, #-48 : IntAlu :  D=0xffffff8008043db0  FetchSeq=13255118  CPSeq=11776611  flags=(IsInteger|IsMicroop|IsDelayedCommit|IsFirstMicroop)
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache. 1 :   strxi_uop   x29, [ureg0] : MemWrite :  D=0xffffff8008043de0 A=0xffffff8008043db0  FetchSeq=13255119  CPSeq=11776612  flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit)
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache. 2 :   strxi_uop   x30, [ureg0, #8] : MemWrite :  D=0xffffff80080932e4 A=0xffffff8008043db8  FetchSeq=13255120  CPSeq=11776613  flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit)
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache. 3 :   addxi_uop   sp, ureg0, #0 : IntAlu :  D=0xffffff8008043db0  FetchSeq=13255121  CPSeq=11776614  flags=(IsInteger|IsMicroop|IsLastMicroop)
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+4    :   add   x29, sp, #0        : IntAlu :  D=0xffffff8008043db0  FetchSeq=13255122  CPSeq=11776615  flags=(IsInteger)
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+8    : stp
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+8. 0 :   addxi_uop   ureg0, sp, #16 : IntAlu :  D=0xffffff8008043dc0  FetchSeq=13255123  CPSeq=11776616  flags=(IsInteger|IsMicroop|IsDelayedCommit|IsFirstMicroop)
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+8. 1 :   strxi_uop   x19, [ureg0] : MemWrite :  D=0x0000000000000004 A=0xffffff8008043dc0  FetchSeq=13255124  CPSeq=11776617  flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit)
7306509000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306509500
7306509000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306509000
7306509000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306509500
7306509500: Event: system.tol2bus.slave[20]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1327 executed @ 7306509500
7306509500: Cache: system.cpu5.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400
7306509500: Event: system.cpu5.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 291 scheduled @ 7306511500
7306509500: CacheVerbose: system.cpu5.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400
7306509500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306509500
7306509500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306509500
7306509500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=40dd82c98f5500000018d1d18f5500001241ca000000000020aabfc98f550000000000008f55000030abeac88f55000030abeac88f5500000000000000000000 ptr=0x558fd070f600
7306509500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c00f80c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802400
7306509500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c00f80c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802400
7306509500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c00f80c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802400 SF size: 0 lat: 1
7306509500: CoherentXBar: system.membus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=c00f80c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802400
7306509500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x80737180 size 64
7306509500: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306509500: DRAM: system.mem_ctrls: Address: 0x737180 Rank 1 Bank 3 Row 57
7306509500: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306509500: DRAM: system.mem_ctrls: Adding to read queue
7306509500: DRAM: system.mem_ctrls: Request scheduled immediately
7306509500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306509500
7306509500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306511000
7306509500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306509500 to 7306511000
7306509500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306510500
7306509500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306509500
7306509500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306509500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306509500: DRAM: system.mem_ctrls: Timing access to addr 0x737180, rank/bank/row 1 3 57
7306509500: DRAM: system.mem_ctrls: Removing burstTick for 7306505000
7306509500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306512000
7306509500: DRAM: system.mem_ctrls: Access to 0x737180, ready at 7306530750 next burst at 7306517000.
7306509500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306509500
7306509500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306509500
7306509500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306509500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306509500
7306509500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306510000
7306509500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306509500
7306509500: Cache: system.cpu0.dcache: access for WriteReq [8d847de0:8d847de7] D=003e040880ffffff ptr=0x558fc9802300 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306509500: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847de0:8d847de7] D=003e040880ffffff ptr=0x558fc9802300 (write)
7306509500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306510500
7306509500: Cache: system.cpu0.dcache: access for WriteReq [8d847de8:8d847def] D=ec3f990880ffffff ptr=0x558fd070fe00 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306509500: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847de8:8d847def] D=ec3f990880ffffff ptr=0x558fd070fe00 (write)
7306509500: Cache: system.cpu0.dcache: access for WriteReq [8d847df0:8d847df7] D=0400000000000000 ptr=0x558fd070fc80 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306509500: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847df0:8d847df7] D=0400000000000000 ptr=0x558fd070fc80 (write)
7306504000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+8. 2 :   strxi_uop   x20, [ureg0, #8] : MemWrite :  D=0xffffff80089e9018 A=0xffffff8008043dc8  FetchSeq=13255125  CPSeq=11776618  flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsLastMicroop)
7306504500: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+12    :   orr   x19, xzr, x0       : IntAlu :  D=0x000000008000fff8  FetchSeq=13255126  CPSeq=11776619  flags=(IsInteger)
7306504500: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+16    :   str   x21, [sp, #32]     : MemWrite :  D=0xffffff8008a08724 A=0xffffff8008043dd0  FetchSeq=13255127  CPSeq=11776620  flags=(IsInteger|IsMemRef|IsStore)
7306504500: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+20    :   orr   x20, xzr, x1       : IntAlu :  D=0x0000000000000008  FetchSeq=13255128  CPSeq=11776621  flags=(IsInteger)
7306504500: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+24    :   ubfm   x0, x0, #12, #63  : IntAlu :  D=0x000000000008000f  FetchSeq=13255129  CPSeq=11776622  flags=(IsInteger)
7306504500: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+28    :   orr   x21, xzr, x30      : IntAlu :  D=0xffffff80080932e4  FetchSeq=13255130  CPSeq=11776623  flags=(IsInteger)
7306504500: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+32    :   bl   <pfn_valid>         : IntAlu :  D=0xffffff800809b82c  FetchSeq=13255131  CPSeq=11776624  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306505500: ExecEnable: system.cpu0: A0 T0 : @pfn_valid    : stp
7306505500: ExecEnable: system.cpu0: A0 T0 : @pfn_valid. 0 :   addxi_uop   ureg0, sp, #-16 : IntAlu :  D=0xffffff8008043da0  FetchSeq=13255132  CPSeq=11776625  flags=(IsInteger|IsMicroop|IsDelayedCommit|IsFirstMicroop)
7306509500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306510000
7306509750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306509750
7306509750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306509750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 3
7306509750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306509750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802200
7306509750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306514750
7306510000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306510000
7306510000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306510000
7306510000: Cache: system.cpu0.icache: access for ReadReq [801ae380:801ae3bf] IF D=4053d2d18f550000c020d4d18f550000d341ca0000000000000000002300ffff000000008f550000f0b1eac88f55000000b1eac88f550000ca8bf097fd7bc1a8 ptr=0x558fd070f800 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x2006b set: 0x8e way: 0x1
7306510000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306511000
7306510000: Cache: system.cpu0.dcache: access for ReadReq [80a26470:80a26473] D=18316acf ptr=0x558fd070fd00 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x10144 set: 0x191 way: 0x1
7306510000: Cache: system.cpu0.dcache: access for ReadReq [80a26488:80a2648f] D=e02f6acf8f550000 ptr=0x558fc9802700 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x10144 set: 0x192 way: 0x1
7306510000: Cache: system.cpu0.dcache: access for WriteReq [8d847db0:8d847db7] D=e03d040880ffffff ptr=0x558fc9802780 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f6 way: 0
7306510000: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847db0:8d847db7] D=e03d040880ffffff ptr=0x558fc9802780 (write)
7306510000: Cache: system.cpu0.dcache: access for WriteReq [8d847db8:8d847dbf] D=e432090880ffffff ptr=0x558fc9802000 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f6 way: 0
7306510000: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847db8:8d847dbf] D=e432090880ffffff ptr=0x558fc9802000 (write)
7306510000: Cache: system.cpu0.dcache: access for WriteReq [8d847dc0:8d847dc7] D=0400000000000000 ptr=0x558fd070ff80 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306510000: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847dc0:8d847dc7] D=0400000000000000 ptr=0x558fd070ff80 (write)
7306505500: ExecEnable: system.cpu0: A0 T0 : @pfn_valid. 1 :   strxi_uop   x29, [ureg0] : MemWrite :  D=0xffffff8008043db0 A=0xffffff8008043da0  FetchSeq=13255133  CPSeq=11776626  flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit)
7306505500: ExecEnable: system.cpu0: A0 T0 : @pfn_valid. 2 :   strxi_uop   x30, [ureg0, #8] : MemWrite :  D=0xffffff800809b82c A=0xffffff8008043da8  FetchSeq=13255134  CPSeq=11776627  flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit)
7306505500: ExecEnable: system.cpu0: A0 T0 : @pfn_valid. 3 :   addxi_uop   sp, ureg0, #0 : IntAlu :  D=0xffffff8008043da0  FetchSeq=13255135  CPSeq=11776628  flags=(IsInteger|IsMicroop|IsLastMicroop)
7306505500: ExecEnable: system.cpu0: A0 T0 : @pfn_valid+4    :   ubfm   x0, x0, #52, #51  : IntAlu :  D=0x000000008000f000  FetchSeq=13255136  CPSeq=11776629  flags=(IsInteger)
7306505500: ExecEnable: system.cpu0: A0 T0 : @pfn_valid+8    :   add   x29, sp, #0        : IntAlu :  D=0xffffff8008043da0  FetchSeq=13255137  CPSeq=11776630  flags=(IsInteger)
7306505500: ExecEnable: system.cpu0: A0 T0 : @pfn_valid+12    :   bl   <memblock_is_map_memory> : IntAlu :  D=0xffffff800809b1f8  FetchSeq=13255138  CPSeq=11776631  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306506500: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory    :   adrp   x1, #8880128      : IntAlu :  D=0xffffff8008a26000  FetchSeq=13255139  CPSeq=11776632  flags=(IsInteger)
7306510000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306510500
7306510000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306510000
7306510000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306510500
7306510500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306510500
7306510500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306510501
7306510500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306510500
7306510500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=0053d2d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00cd8f550000 ptr=0x558fc9824180
7306510500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=8043d2d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802300 BUSY
7306510500: Event: system.tol2bus.respLayer20.wrapped_function_event: EventFunctionWrapped 1328 executed @ 7306510500
7306510500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306510500
7306510500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306511000
7306510500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306510500
7306510500: Cache: system.cpu0.dcache: access for WriteReq [8d847dc8:8d847dcf] D=18909e0880ffffff ptr=0x558fc9802300 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306510500: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847dc8:8d847dcf] D=18909e0880ffffff ptr=0x558fc9802300 (write)
7306510500: Cache: system.cpu0.dcache: access for WriteReq [8d847dd0:8d847dd7] D=2487a00880ffffff ptr=0x558fc9802c00 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306510500: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847dd0:8d847dd7] D=2487a00880ffffff ptr=0x558fc9802c00 (write)
7306506500: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+4    :   add   x1, x1, #1120      : IntAlu :  D=0xffffff8008a26460  FetchSeq=13255140  CPSeq=11776633  flags=(IsInteger)
7306506500: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+8    :   movz   w4, #0, #0        : IntAlu :  D=0x0000000000000000  FetchSeq=13255141  CPSeq=11776634  flags=(IsInteger)
7306506500: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+12    :   movz   w7, #24, #0       : IntAlu :  D=0x0000000000000018  FetchSeq=13255142  CPSeq=11776635  flags=(IsInteger)
7306510500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306511000
7306510501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306510501
7306510501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306510502
7306510502: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306510502
7306510502: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306511000
7306511000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306511000
7306511000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306511001
7306511000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306511000
7306511000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306511000
7306511000: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=0053d2d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00cd8f550000 ptr=0x558fc9824180
7306511000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=0029d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070f800
7306511000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=0029d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070f800
7306511000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=0029d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070f800 SF size: 0 lat: 1
7306511000: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=0029d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070f800
7306511000: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306511000: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306511000: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306511000: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306511000: DRAM: system.mem_ctrls: Adding to read queue
7306511000: DRAM: system.mem_ctrls: Request scheduled immediately
7306511000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306511000
7306511000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306512000
7306511000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306511000 to 7306512000
7306511000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306514500
7306511000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306511000
7306511000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306511000: DRAM: system.mem_ctrls: Single request, going to a free rank
7306511000: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306511000: DRAM: system.mem_ctrls: Removing burstTick for 7306510000
7306511000: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306517000
7306511000: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306535750 next burst at 7306522000.
7306511000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306511000
7306511000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306511000
7306511000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306511000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306511000
7306511000: Cache: system.cpu0.icache: access for ReadReq [8009b1c0:8009b1ff] IF D=4008d1d18f550000c0bcacd38f550000e341ca0000000000000000000100ffff000000008f55000060bdeac88f55000040bceac88f550000ca8bf097fd7bc1a8 ptr=0x558fd070fc80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20026 set: 0xc7 way: 0
7306511000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306512000
7306511000: Cache: system.cpu0.dcache: access for WriteReq [8d847da0:8d847da7] D=b03d040880ffffff ptr=0x558fd070fe00 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f6 way: 0
7306511000: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847da0:8d847da7] D=b03d040880ffffff ptr=0x558fd070fe00 (write)
7306511000: Cache: system.cpu0.dcache: access for WriteReq [8d847da8:8d847daf] D=2cb8090880ffffff ptr=0x558fc9824080 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f6 way: 0
7306511000: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8d847da8:8d847daf] D=2cb8090880ffffff ptr=0x558fc9824080 (write)
7306511000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306511500
7306511000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306511000
7306511000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306511500
7306511001: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306511001
7306511001: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306511002
7306511002: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306511002
7306511002: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306511003
7306511003: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306511003
7306511003: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306511004
7306511004: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306511004
7306511004: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306511500
7306511500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306511500
7306511500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306511501
7306511500: Event: system.cpu5.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 291 executed @ 7306511500
7306511500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306511500
7306511500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306511500
7306511500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306512000
7306511500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306511500
7306511500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306512000
7306511500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306511500
7306511500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306512000
7306511501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306511501
7306511501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306512000
7306512000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306512000
7306512000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306512001
7306512000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306512000
7306512000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306512000
7306512000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306512000
7306512000: Cache: system.cpu0.icache: access for ReadReq [8009b200:8009b23f] IF D=00b2acd38f55000000a9acd38f5500004541ca000000000080f6d2d18f55000080d619d28f55000030abeac88f55000030abeac88f550000909fc7cd8f550000 ptr=0x558fd070fc80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20026 set: 0xc8 way: 0x1
7306512000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306513000
7306512000: Event: Event_102332: Functional unit completion 102332 scheduled @ 7306513000
7306507500: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+16    :   ldr   x3, [x1, #16]      : MemRead :  D=0x0000000000000001 A=0xffffff8008a26470  FetchSeq=13255143  CPSeq=11776636  flags=(IsInteger|IsMemRef|IsLoad)
7306512000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306512500
7306512000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306512000
7306512000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306512500
7306512000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306512000
7306512000: Cache: system.cpu5.icache: access for ReadReq [807371c0:807371ff] IF UC D=c03cd4d18f5500006374696f6e5772617070656420323239a0f7d6d18f550000403403d28f550000363530353030300a00bfeac88f55000010c3e9cd8f550000 ptr=0x558fd070fe00
7306512000: CachePort: system.cpu5.icache.mem_side: Scheduling send event at 7306513000
7306512000: Event: system.cpu5.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 293 scheduled @ 7306513000
7306512000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306512500
7306512001: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306512001
7306512500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306512500
7306512500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306513000
7306512500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306512500
7306512500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306513000
7306512500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306512500
7306507500: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+20    :   ldr   x5, [x1, #40]      : MemRead :  D=0xffffff8008a8c570 A=0xffffff8008a26488  FetchSeq=13255144  CPSeq=11776637  flags=(IsInteger|IsMemRef|IsLoad)
7306507500: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+24    :   b   <memblock_is_map_memory+56> : IntAlu :   FetchSeq=13255145  CPSeq=11776638  flags=(IsControl|IsDirectControl|IsUncondControl)
7306508000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+56    :   add   w1, w4, w3         : IntAlu :  D=0x0000000000000001  FetchSeq=13255146  CPSeq=11776639  flags=(IsInteger)
7306512500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306513000
7306513000: Event: system.cpu5.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 293 executed @ 7306513000
7306513000: Cache: system.cpu5.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c03cd4d18f5500006374696f6e5772617070656420323239a0f7d6d18f550000403403d28f550000363530353030300a00bfeac88f55000010c3e9cd8f550000 ptr=0x558fd070fe00
7306513000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[20] packet ReadReq [807371c0:807371ff] IF UC D=c020d4d18f5500000012d1d18f550000e741ca0000000000000000000300ffff000000002037333000b7eac88f55000030b1eac88f5500000000018ac31900d0 ptr=0x558fd070fd00
7306513000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[20] packet ReadReq [807371c0:807371ff] IF UC D=c020d4d18f5500000012d1d18f550000e741ca0000000000000000000300ffff000000002037333000b7eac88f55000030b1eac88f5500000000018ac31900d0 ptr=0x558fd070fd00
7306513000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[20] packet ReadReq [807371c0:807371ff] IF UC D=c020d4d18f5500000012d1d18f550000e741ca0000000000000000000300ffff000000002037333000b7eac88f55000030b1eac88f5500000000018ac31900d0 ptr=0x558fd070fd00 SF size: 0 lat: 0
7306513000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=c020d4d18f5500000012d1d18f550000e741ca0000000000000000000300ffff000000002037333000b7eac88f55000030b1eac88f5500000000018ac31900d0 ptr=0x558fd070fd00
7306513000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=c020d4d18f5500000012d1d18f550000e741ca0000000000000000000300ffff000000002037333000b7eac88f55000030b1eac88f5500000000018ac31900d0 ptr=0x558fd070fd00
7306513000: CachePort: system.l2.mem_side: Scheduling send event at 7306523500
7306513000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306513500
7306513000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306513000 to 7306513500
7306513000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306513000
7306513000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306513000
7306513000: Cache: system.cpu0.icache: access for ReadReq [8009b800:8009b83f] IF D=c00880c98f5500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e740090aeeac88f550000c0035fd61f2003d5 ptr=0x558fd070fc80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20026 set: 0xe0 way: 0
7306513000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306514000
7306508000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+60    :   ubfm   w1, w1, #1, #31   : IntAlu :  D=0x0000000000000000  FetchSeq=13255147  CPSeq=11776640  flags=(IsInteger)
7306513000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306513500
7306513000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306513000
7306513000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306513500
7306513000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306513000
7306513000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306513500
7306513000: Event: Event_102332: Functional unit completion 102332 executed @ 7306513000
7306513500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306513500
7306513500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306513500
7306513500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306514000
7306513500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306513500
7306513500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306513500
7306513500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306514000
7306514000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306514000
7306514000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306514000
7306514000: Cache: system.cpu0.icache: access for ReadReq [8009b880:8009b8bf] IF D=c093d6d18f5500006374696f6e5772617070656420313834203c03d28f550000608cd3d18f550000363530383030300a0000b2c98f55000090b4b9cd8f550000 ptr=0x558fd070fc80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20026 set: 0xe2 way: 0
7306514000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306515000
7306514000: Cache: system.cpu0.dcache: access for ReadReq [80a8c570:80a8c577] D=18316acf8f550000 ptr=0x558fc9802700 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x10151 set: 0x115 way: 0
7306514000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306515000
7306514000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306514500
7306514000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306514000
7306514000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306514500
7306514500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306514500
7306514500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=0033d4d18f5500006374696f6e5772617070656420343632203c03d28f5500006564204020373330363438303030300a002035370a0000000000000000000000 ptr=0x558fc8fb7f80
7306514500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c017d1d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9824080
7306514500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c017d1d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9824080
7306514500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c017d1d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9824080 SF size: 0 lat: 1
7306514500: CoherentXBar: system.membus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=c017d1d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9824080
7306514500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x80737180 size 64
7306514500: DRAM: system.mem_ctrls: Read queue limit 32, current size 4, entries needed 1
7306514500: DRAM: system.mem_ctrls: Address: 0x737180 Rank 1 Bank 3 Row 57
7306514500: DRAM: system.mem_ctrls: Read queue limit 32, current size 4, entries needed 1
7306514500: DRAM: system.mem_ctrls: Adding to read queue
7306514500: DRAM: system.mem_ctrls: Request scheduled immediately
7306514500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306514500
7306514500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306516000
7306514500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306514500 to 7306516000
7306514500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306515500
7306514500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306514500
7306514500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306514500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306514500: DRAM: system.mem_ctrls: Timing access to addr 0x737180, rank/bank/row 1 3 57
7306514500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306522000
7306514500: DRAM: system.mem_ctrls: Access to 0x737180, ready at 7306540750 next burst at 7306527000.
7306514500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306514500
7306514500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306514500
7306514500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306514500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306514500
7306514500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306515000
7306514500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306514500
7306514500: Cache: system.cpu0.dcache: access for ReadReq [80a8c578:80a8c57f] D=30326acf8f550000 ptr=0x558fc9802c00 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x10151 set: 0x115 way: 0
7306514500: Cache: system.cpu0.dcache: access for ReadReq [80a8c580:80a8c587] D=902d6acf8f550000 ptr=0x558fd070fe80 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x10151 set: 0x116 way: 0x1
7306514500: Cache: system.cpu0.dcache: access for ReadReq [8d847da0:8d847daf] D=b0f767d08f550000c0f867d08f550000 ptr=0x558fc9802300 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f6 way: 0
7306508000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+64    :   umaddl   x2, xzr, x1, x7 : IntMult :  D=0x0000000000000000  FetchSeq=13255148  CPSeq=11776641  flags=(IsInteger)
7306514500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306515000
7306514750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306514750
7306514750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306514750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 4
7306514750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306514750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824000
7306514750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306525750
7306515000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306515000
7306515000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306515500
7306515000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306515000
7306515000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306515000
7306508000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+68    :   add   x6, x5, x2         : IntAlu :  D=0xffffff8008a8c570  FetchSeq=13255149  CPSeq=11776642  flags=(IsInteger)
7306515000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306515500
7306515000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306515000
7306515000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306515500
7306515500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306515500
7306515500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306515501
7306515500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306515500
7306515500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=800ed1d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00d18f550000 ptr=0x558fc9802180
7306515500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=80abaed38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070fc80 BUSY
7306515500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306515500
7306511500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306511500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306511500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306515500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306516000
7306515500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306515500
7306515500: Cache: system.cpu0.icache: access for ReadReq [800932c0:800932ff] IF D=00bcacd38f5500006374696f6e5772617070656420323239c02fd6d18f5500006564204020373330363531323530300a00bceac88f5500000000000000000000 ptr=0x558fd070fc80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20024 set: 0xcb way: 0x1
7306515500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306516500
7306515500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306516000
7306515501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306515501
7306515501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306515502
7306515502: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306515502
7306516000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306516000
7306516000: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=800ed1d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00d18f550000 ptr=0x558fc9802180
7306516000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=00bcacd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070ff80
7306516000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=00bcacd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070ff80
7306516000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=00bcacd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070ff80 SF size: 0 lat: 1
7306516000: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=00bcacd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070ff80
7306516000: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306516000: DRAM: system.mem_ctrls: Read queue limit 32, current size 4, entries needed 1
7306516000: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306516000: DRAM: system.mem_ctrls: Read queue limit 32, current size 4, entries needed 1
7306516000: DRAM: system.mem_ctrls: Adding to read queue
7306516000: DRAM: system.mem_ctrls: Request scheduled immediately
7306516000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306516000
7306516000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306517000
7306516000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306516000 to 7306517000
7306516000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306519500
7306516000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306516000
7306516000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306516000: DRAM: system.mem_ctrls: Single request, going to a free rank
7306516000: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306516000: DRAM: system.mem_ctrls: Removing burstTick for 7306515000
7306516000: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306527000
7306516000: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306545750 next burst at 7306532000.
7306516000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306516000
7306516000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306516000
7306516000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306516000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306516000
7306508000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+72    :   ldr   x2, [x5, x2]       : MemRead :  D=0x0000000080000000 A=0xffffff8008a8c570  FetchSeq=13255150  CPSeq=11776643  flags=(IsInteger|IsMemRef|IsLoad)
7306516000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306516500
7306516000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306516000
7306516000: Cache: system.cpu5.icache: access for ReadReq [80737180:807371bf] IF UC D=0000d1d18f55000060cff8cc8f550000ac0000000000000040ddd1d18f550000c0c6d1d18f5500008878f2cc8f5500007078f2cc8f5500000000018ac31900d0 ptr=0x558fc9802000
7306516000: CachePort: system.cpu5.icache.mem_side: Scheduling send event at 7306517000
7306516000: Event: system.cpu5.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 293 scheduled @ 7306517000
7306516000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306516500
7306516500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306516500
7306516500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306516500
7306516500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306517000
7306516500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306516500
7306516500: Cache: system.cpu0.icache: access for ReadReq [80093300:8009333f] IF D=0095d6d18f550000400ad1d18f550000a900000000000000000000000100ffff000000006374696f70482acd8f55000058482acd8f5500000000000000000000 ptr=0x558fd070fc80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20024 set: 0xcc way: 0x1
7306516500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306517500
7306508000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+76    :   subs   x0, x2            : IntAlu :  D=0x0000000000000001  FetchSeq=13255151  CPSeq=11776644  flags=(IsInteger)
7306516500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306517000
7306517000: Event: system.cpu5.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 293 executed @ 7306517000
7306517000: Cache: system.cpu5.icache: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=0000d1d18f55000060cff8cc8f550000ac0000000000000040ddd1d18f550000c0c6d1d18f5500008878f2cc8f5500007078f2cc8f5500000000018ac31900d0 ptr=0x558fc9802000
7306517000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[20] packet ReadReq [80737180:807371bf] IF UC D=808fd6d18f55000008000014c80440f9240400114200088ba08ed3d18f550000203c03d28f5500008100030b217c0153227ca79ba600028ba26862f81f0002eb ptr=0x558fc9802700
7306517000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[20] packet ReadReq [80737180:807371bf] IF UC D=808fd6d18f55000008000014c80440f9240400114200088ba08ed3d18f550000203c03d28f5500008100030b217c0153227ca79ba600028ba26862f81f0002eb ptr=0x558fc9802700
7306517000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[20] packet ReadReq [80737180:807371bf] IF UC D=808fd6d18f55000008000014c80440f9240400114200088ba08ed3d18f550000203c03d28f5500008100030b217c0153227ca79ba600028ba26862f81f0002eb ptr=0x558fc9802700 SF size: 0 lat: 0
7306517000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=808fd6d18f55000008000014c80440f9240400114200088ba08ed3d18f550000203c03d28f5500008100030b217c0153227ca79ba600028ba26862f81f0002eb ptr=0x558fc9802700
7306517000: Cache: system.l2: access for ReadReq [80737180:807371bf] IF UC D=808fd6d18f55000008000014c80440f9240400114200088ba08ed3d18f550000203c03d28f5500008100030b217c0153227ca79ba600028ba26862f81f0002eb ptr=0x558fc9802700
7306517000: CachePort: system.l2.mem_side: Scheduling send event at 7306527500
7306517000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306517500
7306517000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306517000 to 7306517500
7306517000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306517000
7306517000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306517000
7306509000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+80    :   b.cs   <memblock_is_map_memory+28> : IntAlu :   FetchSeq=13255152  CPSeq=11776645  flags=(IsControl|IsDirectControl|IsCondControl)
7306510000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+28    :   ldr   x8, [x6, #8]       : MemRead :  D=0x0000000010000000 A=0xffffff8008a8c578  FetchSeq=13255153  CPSeq=11776646  flags=(IsInteger|IsMemRef|IsLoad)
7306510000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+32    :   add   w4, w1, #1         : IntAlu :  D=0x0000000000000001  FetchSeq=13255154  CPSeq=11776647  flags=(IsInteger)
7306510000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+36    :   add   x2, x2, x8         : IntAlu :  D=0x0000000090000000  FetchSeq=13255155  CPSeq=11776648  flags=(IsInteger)
7306517000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306517500
7306517000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306517000
7306517000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306517500
7306517500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306517500
7306517500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306517500
7306517500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306517500
7306517500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306518000
7306517500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306517500
7306517500: Cache: system.cpu0.icache: access for ReadReq [8009b380:8009b3bf] IF D=4094d6d18f5500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e740000000000000000000000000000000000 ptr=0x558fd070fc80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20026 set: 0xce way: 0x1
7306517500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306518500
7306517500: Cache: system.cpu0.dcache: access for ReadReq [8d847dd0:8d847dd7] D=782f6acf8f550000 ptr=0x558fc9802780 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306517500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306518500
7306517500: Cache: system.cpu0.dcache: access for ReadReq [8d847db0:8d847dbf] D=b0f267d08f5500000000000000000000 ptr=0x558fc9802600 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f6 way: 0
7306510000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+40    :   subs   x0, x2            : IntAlu :  D=0x0000000000000000  FetchSeq=13255156  CPSeq=11776649  flags=(IsInteger)
7306517500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306518000
7306518000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306518000
7306518000: Cache: system.cpu0.dcache: access for ReadReq [80934b00:80934b07] D=30326acf8f550000 ptr=0x558fc9802c00 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x10126 set: 0x12c way: 0x1
7306518000: Cache: system.cpu0.dcache: access for ReadReq [8d847dc0:8d847dcf] D=b0f267d08f5500000000000000000000 ptr=0x558fc9824100 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306510000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+44    :   b.cc   <memblock_is_map_memory+104> : IntAlu :   FetchSeq=13255157  CPSeq=11776650  flags=(IsControl|IsDirectControl|IsCondControl)
7306511000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+104    :   ldr   x0, [x6, #16]      : MemRead :  D=0x0000000000000000 A=0xffffff8008a8c580  FetchSeq=13255158  CPSeq=11776651  flags=(IsInteger|IsMemRef|IsLoad)
7306511000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+108    :   ubfm   x0, x0, #2, #63   : IntAlu :  D=0x0000000000000000  FetchSeq=13255159  CPSeq=11776652  flags=(IsInteger)
7306511000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+112    :   eor   x0, x0, #1         : IntAlu :  D=0x0000000000000001  FetchSeq=13255160  CPSeq=11776653  flags=(IsInteger)
7306518000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306518500
7306518000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306518000
7306518000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306518500
7306518500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306518500
7306518500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306518501
7306518500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306518500
7306518500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306518500
7306518500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306519000
7306518500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306518500
7306518500: Cache: system.cpu0.icache: access for ReadReq [8009b3c0:8009b3ff] IF D=8089d6d18f5500006573706f6e644576656e7428293a20534022d6d18f550000806474d08f5500006865642069747320726561647954696d650a009000003d91 ptr=0x558fd070fc80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20026 set: 0xcf way: 0x1
7306518500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306519500
7306511000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+116    :   and   w0, w0, #1         : IntAlu :  D=0x0000000000000001  FetchSeq=13255161  CPSeq=11776654  flags=(IsInteger)
7306511000: ExecEnable: system.cpu0: A0 T0 : @memblock_is_map_memory+120    :   ret                      : IntAlu :   FetchSeq=13255162  CPSeq=11776655  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306518500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306519000
7306518501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306518501
7306518501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306519000
7306519000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306519000
7306519000: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306519001
7306519000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306519000
7306512000: ExecEnable: system.cpu0: A0 T0 : @pfn_valid+16    :   and   w0, w0, #255       : IntAlu :  D=0x0000000000000001  FetchSeq=13255163  CPSeq=11776656  flags=(IsInteger)
7306512000: ExecEnable: system.cpu0: A0 T0 : @pfn_valid+20    : ldp
7306512000: ExecEnable: system.cpu0: A0 T0 : @pfn_valid+20. 0 :   ldp_uop   x29, x30, [sp] : MemRead :  D=0xffffff800809b82c A=0xffffff8008043da0  FetchSeq=13255164  CPSeq=11776657  flags=(IsInteger|IsMemRef|IsLoad|IsMicroop|IsDelayedCommit|IsFirstMicroop)
7306512000: ExecEnable: system.cpu0: A0 T0 : @pfn_valid+20. 1 :   addxi_uop   sp, sp, #16  : IntAlu :  D=0xffffff8008043db0  FetchSeq=13255165  CPSeq=11776658  flags=(IsInteger|IsMicroop|IsLastMicroop)
7306513000: ExecEnable: system.cpu0: A0 T0 : @pfn_valid+24    :   ret                      : IntAlu :   FetchSeq=13255166  CPSeq=11776659  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306519000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306519500
7306519000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306519000
7306519000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306519500
7306519001: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306519001
7306519500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306519500
7306519500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306519500
7306519500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=c034d4d18f5500000091d6d18f550000c441ca0000000000000000000000ffff0000000020373330f0a8eac88f550000d0b3eac88f55000010d8e9cd8f550000 ptr=0x558fc8fb7d00
7306519500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=801f80c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070fc80
7306519500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=801f80c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070fc80
7306519500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=801f80c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070fc80 SF size: 0 lat: 1
7306519500: CoherentXBar: system.membus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=801f80c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070fc80
7306519500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x80737180 size 64
7306519500: DRAM: system.mem_ctrls: Read queue limit 32, current size 5, entries needed 1
7306519500: DRAM: system.mem_ctrls: Address: 0x737180 Rank 1 Bank 3 Row 57
7306519500: DRAM: system.mem_ctrls: Read queue limit 32, current size 5, entries needed 1
7306519500: DRAM: system.mem_ctrls: Adding to read queue
7306519500: DRAM: system.mem_ctrls: Request scheduled immediately
7306519500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306519500
7306519500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306521000
7306519500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306519500 to 7306521000
7306519500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306523500
7306519500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306519500
7306519500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306519500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306519500: DRAM: system.mem_ctrls: Timing access to addr 0x737180, rank/bank/row 1 3 57
7306519500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306532000
7306519500: DRAM: system.mem_ctrls: Access to 0x737180, ready at 7306550750 next burst at 7306537000.
7306519500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306519500
7306519500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306519500
7306519500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306519500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306519500
7306519500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306520000
7306519500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306519500
7306519500: Cache: system.cpu0.icache: access for ReadReq [80093300:8009333f] IF D=803dd4d18f550000c0bcacd38f550000f841ca0000000000000000000000ffff000000008f55000098b2eac88f55000080afeac88f550000c0035fd6e04000f0 ptr=0x558fd070fe80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20024 set: 0xcc way: 0x1
7306519500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306520500
7306519500: Cache: system.cpu0.dcache: access for ReadReq [80934b10:80934b17] D=902d6acf8f550000 ptr=0x558fc9802a00 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x10126 set: 0x12c way: 0x1
7306519500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306520500
7306514000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+36    :   cbnz   w0, <ioremap_cache+124> : IntAlu :   FetchSeq=13255167  CPSeq=11776660  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+124    :   adrp   x0, #9015296      : IntAlu :  D=0xffffff8008934000  FetchSeq=13255168  CPSeq=11776661  flags=(IsInteger)
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+128    :   ldr   x21, [sp, #32]     : MemRead :  D=0xffffff8008a08724 A=0xffffff8008043dd0  FetchSeq=13255169  CPSeq=11776662  flags=(IsInteger|IsMemRef|IsLoad)
7306519500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306520000
7306520000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306520000
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+132    :   ldr   x0, [x0, #2816]    : MemRead :  D=0x0000000080000000 A=0xffffff8008934b00  FetchSeq=13255170  CPSeq=11776663  flags=(IsInteger|IsMemRef|IsLoad)
7306520000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306520500
7306520000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306520000
7306520000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306520500
7306520500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306520500
7306520500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306520500
7306520500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306520500
7306520500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306521000
7306520500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306520500
7306520500: Cache: system.cpu0.icache: access for ReadReq [8009b7c0:8009b7ff] IF D=00bcacd38f55000000dd82c98f5500000142ca0000000000000000001500ffff000000002f62616eb8b9eac88f55000060baeac88f5500000000000000000000 ptr=0x558fd070fe80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20026 set: 0xdf way: 0x1
7306520500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306521500
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+136    :   sub   x0, x19, x0        : IntAlu :  D=0x000000000000fff8  FetchSeq=13255171  CPSeq=11776664  flags=(IsInteger)
7306520500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306521000
7306521000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306521000
7306521000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306521000
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+140    :   orr   x0, x0, #18446743798831644672 : IntAlu :  D=0xffffffc00000fff8  FetchSeq=13255172  CPSeq=11776665  flags=(IsInteger)
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+144    : ldp
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+144. 0 :   addxi_uop   ureg0, sp, #16 : IntAlu :  D=0xffffff8008043dc0  FetchSeq=13255173  CPSeq=11776666  flags=(IsInteger|IsMicroop|IsDelayedCommit|IsFirstMicroop)
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+144. 1 :   ldp_uop   x19, x20, [ureg0] : MemRead :  D=0xffffff80089e9018 A=0xffffff8008043dc0  FetchSeq=13255174  CPSeq=11776667  flags=(IsInteger|IsMemRef|IsLoad|IsMicroop|IsLastMicroop)
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+148    : ldp
7306515000: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+148. 0 :   ldp_uop   x29, x30, [sp] : MemRead :  D=0xffffff80080932e4 A=0xffffff8008043db0  FetchSeq=13255175  CPSeq=11776668  flags=(IsInteger|IsMemRef|IsLoad|IsMicroop|IsDelayedCommit|IsFirstMicroop)
7306515500: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+148. 1 :   addxi_uop   sp, sp, #48  : IntAlu :  D=0xffffff8008043de0  FetchSeq=13255176  CPSeq=11776669  flags=(IsInteger|IsMicroop|IsLastMicroop)
7306515500: ExecEnable: system.cpu0: A0 T0 : @ioremap_cache+152    :   ret                      : IntAlu :   FetchSeq=13255177  CPSeq=11776670  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306521000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306521500
7306521000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306521000
7306521000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306521500
7306521500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306521500
7306521500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306521500
7306521500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306521500
7306521500: Cache: system.cpu0.icache: access for ReadReq [80093300:8009333f] IF D=40d282c98f5500006374696f6e5772617070656420343232009bd3d18f550000203c03d28f550000363531343530300a007c74d08f550000009bd3d18f550000 ptr=0x558fd070fe80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20024 set: 0xcc way: 0x1
7306521500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306522500
7306516500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+36    :   orr   x19, xzr, x0       : IntAlu :  D=0xffffffc00000fff8  FetchSeq=13255178  CPSeq=11776671  flags=(IsInteger)
7306516500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+40    :   cbz   x0, <smp_spin_table_cpu_prepare+112> : IntAlu :   FetchSeq=13255179  CPSeq=11776672  flags=(IsInteger|IsControl|IsDirectControl|IsCondControl)
7306516500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+44    :   adrp   x2, #9048064      : IntAlu :  D=0xffffff8008934000  FetchSeq=13255180  CPSeq=11776673  flags=(IsInteger)
7306516500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+48    :   adrp   x1, #6963200      : IntAlu :  D=0xffffff8008737000  FetchSeq=13255181  CPSeq=11776674  flags=(IsInteger)
7306516500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+52    :   add   x1, x1, #416       : IntAlu :  D=0xffffff80087371a0  FetchSeq=13255182  CPSeq=11776675  flags=(IsInteger)
7306516500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+56    :   ldr   x2, [x2, #2832]    : MemRead :  D=0xffffff7f88000000 A=0xffffff8008934b10  FetchSeq=13255183  CPSeq=11776676  flags=(IsInteger|IsMemRef|IsLoad)
7306521500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306522000
7306522000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306522000
7306516500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+60    :   sub   x1, x1, x2         : IntAlu :  D=0x00000000807371a0  FetchSeq=13255184  CPSeq=11776677  flags=(IsInteger)
7306522000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306522500
7306522500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306522500
7306522500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306522500
7306522500: Cache: system.cpu0.icache: access for ReadReq [80993fc0:80993fff] IF D=c0b6acd38f5500006374696f6e5772617070656420323734c0c6d1d18f550000208185c98f550000363531363530300a00012bcd8f5500000000000000000000 ptr=0x558fd070fe80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20264 set: 0xff way: 0
7306522500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306523500
7306517500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+64    :   str   x1, [x0]           : MemWrite :  D=0x00000000807371a0 A=0xffffffc00000fff8  FetchSeq=13255185  CPSeq=11776678  flags=(IsInteger|IsMemRef|IsStore)
7306517500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+68    :   movz   x1, #8, #0        : IntAlu :  D=0x0000000000000008  FetchSeq=13255186  CPSeq=11776679  flags=(IsInteger)
7306517500: ExecEnable: system.cpu0: A0 T0 : @smp_spin_table_cpu_prepare+72    :   bl   <__flush_dcache_area> : IntAlu :  D=0xffffff800809330c  FetchSeq=13255187  CPSeq=11776680  flags=(IsInteger|IsControl|IsDirectControl|IsUncondControl|IsCall)
7306522500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306523000
7306523000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306523000
7306523000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306523500
7306523500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306523500
7306523500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306523500
7306523500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c020d4d18f5500000012d1d18f550000e741ca0000000000000000000300ffff000000002037333000b7eac88f55000030b1eac88f5500000000018ac31900d0 ptr=0x558fd070fd00
7306523500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=00b7acd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070fe80
7306523500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=00b7acd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070fe80
7306523500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=00b7acd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070fe80 SF size: 0 lat: 1
7306523500: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=00b7acd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070fe80
7306523500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306523500: DRAM: system.mem_ctrls: Read queue limit 32, current size 6, entries needed 1
7306523500: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306523500: DRAM: system.mem_ctrls: Read queue limit 32, current size 6, entries needed 1
7306523500: DRAM: system.mem_ctrls: Adding to read queue
7306523500: DRAM: system.mem_ctrls: Request scheduled immediately
7306523500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306523500
7306523500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306525000
7306523500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306523500 to 7306525000
7306523500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306527500
7306523500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306523500
7306523500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306523500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306523500: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306523500: DRAM: system.mem_ctrls: Removing burstTick for 7306520000
7306523500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306537000
7306523500: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306555750 next burst at 7306542000.
7306523500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306523500
7306523500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306523500
7306523500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306523500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306523500
7306523500: Cache: system.cpu0.icache: access for ReadReq [80712540:8071257f] IF D=8089d6d18f550000602febc88f5500001342ca0000000000000000002100ffff000000008f55000088aaeac88f55000050a9eac88f550000a04503d28f550000 ptr=0x558fc9802a00 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x201c4 set: 0x95 way: 0
7306523500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306524500
7306523500: Cache: system.cpu0.dcache: access for WriteReq [8000fff8:8000ffff] D=a071738000000000 ptr=0x558fc9802600 miss
7306523500: CachePort: system.cpu0.dcache.mem_side: Scheduling send event at 7306524500
7306523500: Event: system.cpu0.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 55 scheduled @ 7306524500
7306523500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306524000
7306524000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306524000
7306524000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306524500
7306524500: Event: system.cpu0.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 55 executed @ 7306524500
7306524500: Cache: system.cpu0.dcache: sendMSHRQueuePacket: MSHR WriteReq [8000fff8:8000ffff] D=a071738000000000 ptr=0x558fc9802600
7306524500: Cache: system.cpu0.dcache: createMissPacket: created ReadExReq [8000ffc0:8000ffff] D=808cd6d18f55000000b7acd38f550000aa00000000000000e070d4d18f55000080f6d2d18f55000030432acd8f55000030432acd8f550000a500209105c018d5 ptr=0x558fc9824100 from WriteReq [8000fff8:8000ffff] D=a071738000000000 ptr=0x558fc9802600
7306524500: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[1] packet ReadExReq [8000ffc0:8000ffff] D=808cd6d18f55000000b7acd38f550000aa00000000000000e070d4d18f55000080f6d2d18f55000030432acd8f55000030432acd8f550000a500209105c018d5 ptr=0x558fc9824100
7306524500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[1] packet ReadExReq [8000ffc0:8000ffff] D=808cd6d18f55000000b7acd38f550000aa00000000000000e070d4d18f55000080f6d2d18f55000030432acd8f55000030432acd8f550000a500209105c018d5 ptr=0x558fc9824100
7306524500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306524500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306524500: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[1] packet ReadExReq [8000ffc0:8000ffff] D=808cd6d18f55000000b7acd38f550000aa00000000000000e070d4d18f55000080f6d2d18f55000030432acd8f55000030432acd8f550000a500209105c018d5 ptr=0x558fc9824100 SF size: 0 lat: 0
7306524500: CoherentXBar: system.tol2bus: forwardTiming for ReadExReq [8000ffc0:8000ffff] D=808cd6d18f55000000b7acd38f550000aa00000000000000e070d4d18f55000080f6d2d18f55000030432acd8f55000030432acd8f550000a500209105c018d5 ptr=0x558fc9824100
7306524500: Cache: system.l2: access for ReadExReq [8000ffc0:8000ffff] D=808cd6d18f55000000b7acd38f550000aa00000000000000e070d4d18f55000080f6d2d18f55000030432acd8f55000030432acd8f550000a500209105c018d5 ptr=0x558fc9824100 miss
7306524500: CachePort: system.l2.mem_side: Scheduling send event at 7306535000
7306524500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306525000
7306524500: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306524500 to 7306525000
7306524500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306524500
7306524500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306524500
7306524500: Cache: system.cpu0.icache: access for ReadReq [80712580:807125bf] IF D=8090d6d18f5500004059d2d18f5500000e42ca0000000000000000000100ffff000000002037333008b8eac88f55000098b5eac88f550000c2ffff3520008052 ptr=0x558fc9802a00 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x201c4 set: 0x96 way: 0
7306524500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306525500
7306524500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306525000
7306525000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306525000
7306525000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306525000
7306525000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306525000
7306525000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306525500
7306525500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306525500
7306525500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306525500
7306525500: Cache: system.cpu0.icache: access for ReadReq [80994000:8099403f] IF D=0095d6d18f5500006f6c326275732e7265714c61796572308084d0d18f550000403d03d28f5500006e5f6576656e7400363531333030300a0000000000000000 ptr=0x558fc9802a00 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20265 set: 0 way: 0x1
7306525500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306526500
7306525500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306526000
7306525750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306525750
7306525750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306525750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 6
7306525750: DRAM: system.mem_ctrls: Responding to Address 0x807371c0
7306525750: DRAM: system.mem_ctrls: Done: ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802500
7306525750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306530750
7306526000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306526000
7306526000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306526500
7306526500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306526500
7306526500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306526500
7306526500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306527000
7306527000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306527000
7306527000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306527500
7306527500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306527500
7306527500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=808fd6d18f55000008000014c80440f9240400114200088ba08ed3d18f550000203c03d28f5500008100030b217c0153227ca79ba600028ba26862f81f0002eb ptr=0x558fc9802700
7306527500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=0095d6d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802a00
7306527500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=0095d6d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802a00
7306527500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=0095d6d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802a00 SF size: 0 lat: 1
7306527500: CoherentXBar: system.membus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=0095d6d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802a00
7306527500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x80737180 size 64
7306527500: DRAM: system.mem_ctrls: Read queue limit 32, current size 6, entries needed 1
7306527500: DRAM: system.mem_ctrls: Address: 0x737180 Rank 1 Bank 3 Row 57
7306527500: DRAM: system.mem_ctrls: Read queue limit 32, current size 6, entries needed 1
7306527500: DRAM: system.mem_ctrls: Adding to read queue
7306527500: DRAM: system.mem_ctrls: Request scheduled immediately
7306527500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306527500
7306527500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306529000
7306527500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306527500 to 7306529000
7306527500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306535000
7306527500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306527500
7306527500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306527500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306527500: DRAM: system.mem_ctrls: Timing access to addr 0x737180, rank/bank/row 1 3 57
7306527500: DRAM: system.mem_ctrls: Removing burstTick for 7306525000
7306527500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306542000
7306527500: DRAM: system.mem_ctrls: Access to 0x737180, ready at 7306560750 next burst at 7306547000.
7306527500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306527500
7306527500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306527500
7306527500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306527500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306527500
7306527500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306528000
7306527750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306527750
7306527750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f280
7306527750: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f280
7306527750: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306530000
7306527750: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306533000
7306527750: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306527750 to 7306533000
7306527750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306533250
7306528000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306528000
7306528000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306528500
7306528500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306528500
7306528500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306529000
7306529000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306529000
7306529000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306529000
7306529000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306529500
7306529500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306529500
7306529500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306530000
7306530000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306530000
7306530000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f280
7306530000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306544000
7306530000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f280
7306530000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306530000
7306530000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306530500
7306530500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306530500
7306530500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306531000
7306530750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306530750
7306530750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306530750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 6
7306530750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306530750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400
7306530750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306535750
7306531000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306531000
7306531000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306531500
7306531500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306531500
7306531500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306532000
7306532000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306532000
7306532000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306532500
7306532500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306532500
7306532500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306533000
7306533000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306533000
7306533000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306533000
7306533000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306533500
7306533250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306533250
7306533250: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f580
7306533250: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f580
7306533250: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306536000
7306533250: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306539000
7306533250: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306533250 to 7306539000
7306533250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306538250
7306533500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306533500
7306533500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306534000
7306534000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306534000
7306534000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306534500
7306534500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306534500
7306534500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306535000
7306535000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306535000
7306535000: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadExReq [8000ffc0:8000ffff] D=808cd6d18f55000000b7acd38f550000aa00000000000000e070d4d18f55000080f6d2d18f55000030432acd8f55000030432acd8f550000a500209105c018d5 ptr=0x558fc9824100
7306535000: Cache: system.l2: createMissPacket: created ReadExReq [8000ffc0:8000ffff] D=c04bd2d18f550000f09cc7cd8f550000609dc7cd8f550000d09dc7cd8f550000409ec7cd8f550000b09ec7cd8f550000209fc7cd8f550000909fc7cd8f550000 ptr=0x558fd070f280 from ReadExReq [8000ffc0:8000ffff] D=808cd6d18f55000000b7acd38f550000aa00000000000000e070d4d18f55000080f6d2d18f55000030432acd8f55000030432acd8f550000a500209105c018d5 ptr=0x558fc9824100
7306535000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadExReq [8000ffc0:8000ffff] D=c04bd2d18f550000f09cc7cd8f550000609dc7cd8f550000d09dc7cd8f550000409ec7cd8f550000b09ec7cd8f550000209fc7cd8f550000909fc7cd8f550000 ptr=0x558fd070f280
7306535000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadExReq [8000ffc0:8000ffff] D=c04bd2d18f550000f09cc7cd8f550000609dc7cd8f550000d09dc7cd8f550000409ec7cd8f550000b09ec7cd8f550000209fc7cd8f550000909fc7cd8f550000 ptr=0x558fd070f280
7306535000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306535000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306535000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadExReq [8000ffc0:8000ffff] D=c04bd2d18f550000f09cc7cd8f550000609dc7cd8f550000d09dc7cd8f550000409ec7cd8f550000b09ec7cd8f550000209fc7cd8f550000909fc7cd8f550000 ptr=0x558fd070f280 SF size: 0 lat: 1
7306535000: CoherentXBar: system.membus: forwardTiming for ReadExReq [8000ffc0:8000ffff] D=c04bd2d18f550000f09cc7cd8f550000609dc7cd8f550000d09dc7cd8f550000409ec7cd8f550000b09ec7cd8f550000209fc7cd8f550000909fc7cd8f550000 ptr=0x558fd070f280
7306535000: DRAM: system.mem_ctrls: recvTimingReq: request ReadExReq addr 0x8000ffc0 size 64
7306535000: DRAM: system.mem_ctrls: Read queue limit 32, current size 6, entries needed 1
7306535000: DRAM: system.mem_ctrls: Read to addr 0xffc0 with size 64 serviced by write queue
7306535000: DRAM: system.mem_ctrls: Responding to Address 0x8000ffc0
7306535000: DRAM: system.mem_ctrls: Done: ReadExResp [8000ffc0:8000ffff] D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fd070f280
7306535000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306536000
7306535000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306535000 to 7306536000
7306535000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306535000
7306535000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306535500
7306535500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306535500
7306535500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306536000
7306535750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306535750
7306535750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306535750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 5
7306535750: DRAM: system.mem_ctrls: Responding to Address 0x807371c0
7306535750: DRAM: system.mem_ctrls: Done: ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f800
7306535750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306540750
7306536000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306536000
7306536000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306536000
7306536000: Cache: system.l2: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f580
7306536000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f580
7306536000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306536000
7306536000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306536500
7306536500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306536500
7306536500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306537000
7306537000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306537000
7306537000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306537500
7306537500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306537500
7306537500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306538000
7306538000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306538000
7306538000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306538500
7306538250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306538250
7306538250: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802200 BUSY
7306538500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306538500
7306538500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306539000
7306539000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306539000
7306539000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802200
7306539000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802200
7306539000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306541000
7306539000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306544000
7306539000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306539000 to 7306544000
7306539000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306542750
7306539000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306539000
7306539000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306539500
7306539500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306539500
7306539500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306540000
7306540000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306540000
7306540000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306540500
7306540500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306540500
7306540500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306541000
7306540750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306540750
7306540750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306540750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 4
7306540750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306540750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824080
7306540750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306545750
7306541000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306541000
7306541000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802200
7306541000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802200
7306541000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306541000
7306541000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306541500
7306541500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306541500
7306541500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306542000
7306542000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306542000
7306542000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306542500
7306542500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306542500
7306542500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306543000
7306542750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306542750
7306542750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824000 BUSY
7306543000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306543000
7306543000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306543500
7306543500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306543500
7306543500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306544000
7306544000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306544000
7306544000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824000
7306544000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824000
7306544000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306546000
7306544000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306549000
7306544000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306544000 to 7306549000
7306544000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306553000
7306544000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306544000
7306544000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00
7306544000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[24] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00
7306544000: Event: system.tol2bus.slave[24]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1335 scheduled @ 7306544500
7306544000: Event: system.tol2bus.respLayer24.wrapped_function_event: EventFunctionWrapped 1336 scheduled @ 7306545500
7306544000: BaseXBar: system.tol2bus.respLayer24: The crossbar layer is now busy from tick 7306544000 to 7306545500
7306544000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306550000
7306544000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306544000
7306544000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306544500
7306544500: Event: system.tol2bus.slave[24]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1335 executed @ 7306544500
7306544500: Cache: system.cpu6.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00
7306544500: Event: system.cpu6.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 336 scheduled @ 7306546500
7306544500: CacheVerbose: system.cpu6.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00
7306544500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306544500
7306544500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306545000
7306545000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306545000
7306545000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306545500
7306545500: Event: system.tol2bus.respLayer24.wrapped_function_event: EventFunctionWrapped 1336 executed @ 7306545500
7306545500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306545500
7306545500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306546000
7306545750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306545750
7306545750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306545750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 3
7306545750: DRAM: system.mem_ctrls: Responding to Address 0x807371c0
7306545750: DRAM: system.mem_ctrls: Done: ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070ff80
7306545750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306550750
7306546000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306546000
7306546000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824000
7306546000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824000
7306546000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306546000
7306546000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306546500
7306546500: Event: system.cpu6.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 336 executed @ 7306546500
7306546500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306546500
7306546500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306546500
7306546500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306547000
7306546500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306546500
7306546500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306547000
7306547000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306547000
7306547000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306547500
7306547000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306547000
7306547000: Cache: system.cpu6.icache: access for ReadReq [807371c0:807371ff] IF UC D=00c582c98f55000080abaed38f5500000642ca0000000000000000001000ffff000000008f55000000b4eac88f550000d0bceac88f55000090dbe9cd8f550000 ptr=0x558fc8fb7e00
7306547000: CachePort: system.cpu6.icache.mem_side: Scheduling send event at 7306548000
7306547000: Event: system.cpu6.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 338 scheduled @ 7306548000
7306547000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306547500
7306547500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306547500
7306547500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306548000
7306547500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306547500
7306547500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306548000
7306548000: Event: system.cpu6.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 338 executed @ 7306548000
7306548000: Cache: system.cpu6.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=00c582c98f55000080abaed38f5500000642ca0000000000000000001000ffff000000008f55000000b4eac88f550000d0bceac88f55000090dbe9cd8f550000 ptr=0x558fc8fb7e00
7306548000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[24] packet ReadReq [807371c0:807371ff] IF UC D=c00880c98f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363534383030300a00bfeac88f5500000000018ac31900d0 ptr=0x558fc9824000
7306548000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[24] packet ReadReq [807371c0:807371ff] IF UC D=c00880c98f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363534383030300a00bfeac88f5500000000018ac31900d0 ptr=0x558fc9824000
7306548000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[24] packet ReadReq [807371c0:807371ff] IF UC D=c00880c98f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363534383030300a00bfeac88f5500000000018ac31900d0 ptr=0x558fc9824000 SF size: 0 lat: 0
7306548000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=c00880c98f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363534383030300a00bfeac88f5500000000018ac31900d0 ptr=0x558fc9824000
7306548000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=c00880c98f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363534383030300a00bfeac88f5500000000018ac31900d0 ptr=0x558fc9824000
7306548000: CachePort: system.l2.mem_side: Scheduling send event at 7306558500
7306548000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306558500
7306548000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306548500
7306548000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306548000 to 7306548500
7306548000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306548000
7306548000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306548500
7306548000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306548000
7306548000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306548500
7306548500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306548500
7306548500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306548500
7306548500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306549000
7306548500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306548500
7306548500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306549000
7306549000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306549000
7306549000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306549000
7306549000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306549500
7306549000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306549000
7306549000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306549500
7306549500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306549500
7306549500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306550000
7306549500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306549500
7306549500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306550000
7306550000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306550000
7306550000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802100
7306550000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[4] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802100
7306550000: Event: system.tol2bus.slave[4]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1295 scheduled @ 7306550500
7306550000: Event: system.tol2bus.respLayer4.wrapped_function_event: EventFunctionWrapped 1296 scheduled @ 7306551500
7306550000: BaseXBar: system.tol2bus.respLayer4: The crossbar layer is now busy from tick 7306550000 to 7306551500
7306550000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306555000
7306550000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306550000
7306550000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306550500
7306550000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306550000
7306550000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306550500
7306550500: Event: system.tol2bus.slave[4]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1295 executed @ 7306550500
7306550500: Cache: system.cpu1.icache: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802100
7306550500: Event: system.cpu1.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 111 scheduled @ 7306552500
7306550500: CacheVerbose: system.cpu1.icache: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802100
7306550500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306550500
7306546500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306546500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306546500: ExecEnable: system.cpu6: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306550500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306551000
7306550500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306550500
7306550500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306551000
7306550750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306550750
7306550750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306550750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 2
7306550750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306550750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fc80
7306550750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306555750
7306551000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306551000
7306551000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306551500
7306551000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306551000
7306551000: Cache: system.cpu6.icache: access for ReadReq [80737180:807371bf] IF UC D=4001d1d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00cd8f550000 ptr=0x558fc9802100
7306551000: CachePort: system.cpu6.icache.mem_side: Scheduling send event at 7306552000
7306551000: Event: system.cpu6.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 338 scheduled @ 7306552000
7306551000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306551500
7306551500: Event: system.tol2bus.respLayer4.wrapped_function_event: EventFunctionWrapped 1296 executed @ 7306551500
7306551500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306551500
7306551500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306552000
7306551500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306551500
7306551500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306552000
7306552000: Event: system.cpu6.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 338 executed @ 7306552000
7306552000: Cache: system.cpu6.icache: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=4001d1d18f5500006573706f6e644576656e7428293a20536f6d65207265712068617320726561636865642069747320726561647954696d650a00cd8f550000 ptr=0x558fc9802100
7306552000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[24] packet ReadReq [80737180:807371bf] IF UC D=4097d6d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363535323030300a001fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00
7306552000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[24] packet ReadReq [80737180:807371bf] IF UC D=4097d6d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363535323030300a001fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00
7306552000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[24] packet ReadReq [80737180:807371bf] IF UC D=4097d6d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363535323030300a001fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00 SF size: 0 lat: 0
7306552000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=4097d6d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363535323030300a001fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00
7306552000: Cache: system.l2: access for ReadReq [80737180:807371bf] IF UC D=4097d6d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363535323030300a001fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00
7306552000: CachePort: system.l2.mem_side: Scheduling send event at 7306562500
7306552000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306552500
7306552000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306552000 to 7306552500
7306552000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306552000
7306552000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306552500
7306552000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306552000
7306552000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306552500
7306552500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306552500
7306552500: Event: system.cpu1.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 111 executed @ 7306552500
7306552500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306552500
7306552500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306553000
7306552500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306552500
7306552500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306553000
7306553000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306553000
7306553000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadExResp [8000ffc0:8000ffff] D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fd070f280
7306553000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadExResp [8000ffc0:8000ffff] D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fd070f280
7306553000: SnoopFilter: system.membus.snoop_filter: updateResponse:   old SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306553000: SnoopFilter: system.membus.snoop_filter: updateResponse:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306553000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306555000
7306553000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306558000
7306553000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306553000 to 7306558000
7306553000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306553750
7306553000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306553000
7306553000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306553500
7306553000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306553000
7306553000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306553500
7306553500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306553500
7306553500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306554000
7306553500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306553500
7306553500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306554000
7306553750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306553750
7306553750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802500 BUSY
7306554000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306554000
7306554000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306554500
7306554000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306554000
7306554000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306554500
7306554500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306554500
7306554500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306555000
7306554500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306554500
7306554500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306555000
7306555000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306555000
7306555000: Cache: system.l2: recvTimingResp: Handling response ReadExResp [8000ffc0:8000ffff] D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fd070f280
7306555000: Cache: system.l2: Block for addr 0x8000ffc0 being updated in Cache
7306555000: CacheRepl: system.l2: Replacement victim: state: 0 (I) valid: 0 writable: 0 readable: 0 dirty: 0 | tag: 0xffffffffffffffff set: 0x3ff way: 0x1
7306555000: Cache: system.l2: Block addr 0x8000ffc0 (ns) moving from state 0 (I) to state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x2000 set: 0x3ff way: 0x1
7306555000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadExResp [8000ffc0:8000ffff] D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fd070f280
7306555000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306555000
7306555000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80
7306555000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[4] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80
7306555000: Event: system.tol2bus.slave[4]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1295 scheduled @ 7306555500
7306555000: Event: system.tol2bus.respLayer4.wrapped_function_event: EventFunctionWrapped 1296 scheduled @ 7306556500
7306555000: BaseXBar: system.tol2bus.respLayer4: The crossbar layer is now busy from tick 7306555000 to 7306556500
7306555000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306560000
7306555000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306555000
7306555000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306555500
7306555000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306555000
7306555000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306555500
7306555500: Event: system.tol2bus.slave[4]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1295 executed @ 7306555500
7306555500: Cache: system.cpu1.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80
7306555500: Event: system.cpu1.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 111 scheduled @ 7306557500
7306555500: CacheVerbose: system.cpu1.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802b80
7306555500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306555500
7306555500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306556000
7306555500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306555500
7306555500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306556000
7306555750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306555750
7306555750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306555750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 1
7306555750: DRAM: system.mem_ctrls: Responding to Address 0x807371c0
7306555750: DRAM: system.mem_ctrls: Done: ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fe80
7306555750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306560750
7306556000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306556000
7306556000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306556500
7306556000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306556000
7306556000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 scheduled @ 7306556500
7306556500: Event: system.tol2bus.respLayer4.wrapped_function_event: EventFunctionWrapped 1296 executed @ 7306556500
7306556500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 319 executed @ 7306556500
7306556500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306556500
7306556500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306557000
7306557000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306557000
7306557000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306557500
7306557500: Event: system.cpu1.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 111 executed @ 7306557500
7306557500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306557500
7306557500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306557500
7306557500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306558000
7306557500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306557500
7306557500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306558000
7306558000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306558000
7306558000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802500
7306558000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802500
7306558000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306560000
7306558000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306563000
7306558000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306558000 to 7306563000
7306558000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306559250
7306558000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306558000
7306558000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306558500
7306558000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306558000
7306558000: Cache: system.cpu1.icache: access for ReadReq [807371c0:807371ff] IF UC D=803cd4d18f5500006374696f6e577261707065642031323835207363686564756c6564204020373330363535323530300a0052cd8f55000090dbe9cd8f550000 ptr=0x558fd070f980
7306558000: CachePort: system.cpu1.icache.mem_side: Scheduling send event at 7306559000
7306558000: Event: system.cpu1.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 113 scheduled @ 7306559000
7306558000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306558500
7306558500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306558500
7306558500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c00880c98f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363534383030300a00bfeac88f5500000000018ac31900d0 ptr=0x558fc9824000
7306558500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=400080c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802b80
7306558500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=400080c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802b80
7306558500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=400080c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802b80 SF size: 0 lat: 1
7306558500: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=400080c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802b80
7306558500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306558500: DRAM: system.mem_ctrls: Read queue limit 32, current size 1, entries needed 1
7306558500: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306558500: DRAM: system.mem_ctrls: Read queue limit 32, current size 1, entries needed 1
7306558500: DRAM: system.mem_ctrls: Adding to read queue
7306558500: DRAM: system.mem_ctrls: Request scheduled immediately
7306558500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306558500
7306558500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306560000
7306558500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306558500 to 7306560000
7306558500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306562500
7306558500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306558500
7306558500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306558500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306558500: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306558500: DRAM: system.mem_ctrls: Removing burstTick for 7306540000
7306558500: DRAM: system.mem_ctrls: Removing burstTick for 7306535000
7306558500: DRAM: system.mem_ctrls: Removing burstTick for 7306530000
7306558500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306558500
7306558500: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306577250 next burst at 7306563500.
7306558500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306558500
7306558500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306558500
7306558500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306558500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306558500
7306558500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306559000
7306558500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306558500
7306558500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306559000
7306559000: Event: system.cpu1.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 113 executed @ 7306559000
7306559000: Cache: system.cpu1.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=803cd4d18f5500006374696f6e577261707065642031323835207363686564756c6564204020373330363535323530300a0052cd8f55000090dbe9cd8f550000 ptr=0x558fd070f980
7306559000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[4] packet ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500007565206c696d69742033322c206375720050aad38f5500006520312c20656e7472696573206e656564656420310a00000000000000000000 ptr=0x558fd070f280
7306559000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[4] packet ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500007565206c696d69742033322c206375720050aad38f5500006520312c20656e7472696573206e656564656420310a00000000000000000000 ptr=0x558fd070f280
7306559000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[4] packet ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500007565206c696d69742033322c206375720050aad38f5500006520312c20656e7472696573206e656564656420310a00000000000000000000 ptr=0x558fd070f280 SF size: 0 lat: 0
7306559000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500007565206c696d69742033322c206375720050aad38f5500006520312c20656e7472696573206e656564656420310a00000000000000000000 ptr=0x558fd070f280
7306559000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500007565206c696d69742033322c206375720050aad38f5500006520312c20656e7472696573206e656564656420310a00000000000000000000 ptr=0x558fd070f280
7306559000: CachePort: system.l2.mem_side: Scheduling send event at 7306569500
7306559000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306559500
7306559000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306559000 to 7306559500
7306559000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306559000
7306559000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306559500
7306559000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306559000
7306559000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306559500
7306559250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306559250
7306559250: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400 BUSY
7306559500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306559500
7306559500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306559500
7306559500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306560000
7306559500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306559500
7306559500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306560000
7306560000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306560000
7306560000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306560000
7306560000: Cache: system.l2: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802500
7306560000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802500
7306560000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306560000
7306560000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f480
7306560000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[28] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f480
7306560000: Event: system.tol2bus.slave[28]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1343 scheduled @ 7306560500
7306560000: Event: system.tol2bus.respLayer28.wrapped_function_event: EventFunctionWrapped 1344 scheduled @ 7306561500
7306560000: BaseXBar: system.tol2bus.respLayer28: The crossbar layer is now busy from tick 7306560000 to 7306561500
7306560000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306565000
7306560000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306560000
7306560000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306560500
7306560000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306560000
7306560000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306560500
7306560500: Event: system.tol2bus.slave[28]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1343 executed @ 7306560500
7306560500: Cache: system.cpu7.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f480
7306560500: Event: system.cpu7.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 381 scheduled @ 7306562500
7306560500: CacheVerbose: system.cpu7.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f480
7306560500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306560500
7306560500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306561000
7306560500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306560500
7306560500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306561000
7306560750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306560750
7306560750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306560750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 1
7306560750: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306560750: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802a00
7306560750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306577250
7306561000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306561000
7306561000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306561500
7306561000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306561000
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306561000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306561500
7306561500: Event: system.tol2bus.respLayer28.wrapped_function_event: EventFunctionWrapped 1344 executed @ 7306561500
7306561500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306561500
7306561500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306562000
7306561500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306561500
7306561500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306562000
7306562000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306562000
7306562000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306562500
7306562000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306562000
7306562000: Cache: system.cpu1.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306562000: CachePort: system.cpu1.dcache.mem_side: Scheduling send event at 7306563000
7306562000: Event: system.cpu1.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 100 scheduled @ 7306563000
7306562000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306562500
7306562500: Event: system.cpu7.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 381 executed @ 7306562500
7306562500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306562500
7306562500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306562500
7306562500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=4097d6d18f5500006374696f6e5772617070656420333139207363686564756c6564204020373330363535323030300a001fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fa00
7306562500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c0cf82c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802800
7306562500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c0cf82c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802800
7306562500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=c0cf82c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802800 SF size: 0 lat: 1
7306562500: CoherentXBar: system.membus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=c0cf82c98f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fc9802800
7306562500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x80737180 size 64
7306562500: DRAM: system.mem_ctrls: Read queue limit 32, current size 1, entries needed 1
7306562500: DRAM: system.mem_ctrls: Address: 0x737180 Rank 1 Bank 3 Row 57
7306562500: DRAM: system.mem_ctrls: Read queue limit 32, current size 1, entries needed 1
7306562500: DRAM: system.mem_ctrls: Adding to read queue
7306562500: DRAM: system.mem_ctrls: Request scheduled immediately
7306562500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306562500
7306562500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306564000
7306562500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306562500 to 7306564000
7306562500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306569500
7306562500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306562500
7306562500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306562500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306562500: DRAM: system.mem_ctrls: Timing access to addr 0x737180, rank/bank/row 1 3 57
7306562500: DRAM: system.mem_ctrls: Removing burstTick for 7306555000
7306562500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306563500
7306562500: DRAM: system.mem_ctrls: Access to 0x737180, ready at 7306582250 next burst at 7306568500.
7306562500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306562500
7306562500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306562500
7306562500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306562500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306562500
7306562500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306563000
7306562500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306562500
7306562500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306563000
7306562500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306562500
7306562500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306563000
7306563000: Event: system.cpu1.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 100 executed @ 7306563000
7306563000: Cache: system.cpu1.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306563000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[5] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306563000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[5] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306563000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[5] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480 SF size: 0 lat: 0
7306563000: CoherentXBar: system.tol2bus: forwardTiming for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306563000: Cache: system.l2: access for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306563000: Cache: system.l2: Create CleanEvict CleanEvict [80a70800:80a7083f] D= ptr=0x558fc9802500
7306563000: CoherentXBar: system.tol2bus: recvTimingSnoopReq: src system.tol2bus.master[0] packet CleanEvict [80a70800:80a7083f] ES D= ptr=0x7ffdd53f73a0
7306563000: SnoopFilter: system.tol2bus.snoop_filter: lookupSnoop: packet CleanEvict [80a70800:80a7083f] ES D= ptr=0x7ffdd53f73a0
7306563000: CoherentXBar: system.tol2bus: recvTimingSnoopReq: src system.tol2bus.master[0] packet CleanEvict [80a70800:80a7083f] ES D= ptr=0x7ffdd53f73a0 SF size: 0 lat: 0
7306563000: CoherentXBar: system.tol2bus: forwardTiming for CleanEvict [80a70800:80a7083f] ES D= ptr=0x7ffdd53f73a0
7306563000: CachePort: system.l2.mem_side: Scheduling send event at 7306583000
7306563000: Cache: system.l2: Potential to merge writeback WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306563000: CachePort: system.l2.mem_side: Scheduling send event at 7306573500
7306563000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306564000
7306563000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306563000 to 7306564000
7306563000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306563000
7306563000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400
7306563000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400
7306563000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306565000
7306563000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306568000
7306563000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306563000 to 7306568000
7306563000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306563750
7306563000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306563000
7306563000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306563500
7306563000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306563000
7306563000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306563500
7306563000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306563000
7306563000: Cache: system.cpu7.icache: access for ReadReq [807371c0:807371ff] IF UC D=4008d1d18f5500006374696f6e577261707065642031323835206578656375746564204020373330363534383530300a0000eac88f5500000400805207038052 ptr=0x558fc9802480
7306563000: CachePort: system.cpu7.icache.mem_side: Scheduling send event at 7306564000
7306563000: Event: system.cpu7.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 383 scheduled @ 7306564000
7306563000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306563500
7306563500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306563500
7306563500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306564000
7306563500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306563500
7306563500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306564000
7306563500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306563500
7306563500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306564000
7306563750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306563750
7306563750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f800 BUSY
7306564000: Event: system.cpu7.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 383 executed @ 7306564000
7306564000: Cache: system.cpu7.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=4008d1d18f5500006374696f6e577261707065642031323835206578656375746564204020373330363534383530300a0000eac88f5500000400805207038052 ptr=0x558fc9802480
7306564000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[28] packet ReadReq [807371c0:807371ff] IF UC D=800880c98f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363536343030300a00bbeac88f5500000000000000000000 ptr=0x558fc9802200 BUSY
7306564000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306564000
7306564000: Cache: system.cpu7.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=4008d1d18f5500006374696f6e577261707065642031323835206578656375746564204020373330363534383530300a0000eac88f5500000400805207038052 ptr=0x558fc9802480
7306564000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[28] packet ReadReq [807371c0:807371ff] IF UC D=800880c98f5500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e740000bbeac88f5500000000000000000000 ptr=0x558fc9802200
7306564000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[28] packet ReadReq [807371c0:807371ff] IF UC D=800880c98f5500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e740000bbeac88f5500000000000000000000 ptr=0x558fc9802200
7306564000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[28] packet ReadReq [807371c0:807371ff] IF UC D=800880c98f5500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e740000bbeac88f5500000000000000000000 ptr=0x558fc9802200 SF size: 0 lat: 0
7306564000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=800880c98f5500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e740000bbeac88f5500000000000000000000 ptr=0x558fc9802200
7306564000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=800880c98f5500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e740000bbeac88f5500000000000000000000 ptr=0x558fc9802200
7306564000: CachePort: system.l2.mem_side: Scheduling send event at 7306574500
7306564000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306564500
7306564000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306564000 to 7306564500
7306564000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306564000
7306564000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306564000
7306564000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306564500
7306564000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306564000
7306564000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306564500
7306564000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306564000
7306564000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306564500
7306564500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306564500
7306564500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306564500
7306564500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306565000
7306564500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306564500
7306564500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306565000
7306564500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306564500
7306564500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306565000
7306565000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306565000
7306565000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400
7306565000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802400
7306565000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306565000
7306565000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadExResp [8000ffc0:8000ffff] D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9824100
7306565000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[1] packet ReadExResp [8000ffc0:8000ffff] D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9824100
7306565000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse:   old SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306565000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306565000: Event: system.tol2bus.slave[1]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1289 scheduled @ 7306565500
7306565000: Event: system.tol2bus.respLayer1.wrapped_function_event: EventFunctionWrapped 1290 scheduled @ 7306566500
7306565000: BaseXBar: system.tol2bus.respLayer1: The crossbar layer is now busy from tick 7306565000 to 7306566500
7306565000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306574000
7306565000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306565000
7306565000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306565500
7306565000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306565000
7306565000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306565500
7306565000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306565000
7306565000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306565500
7306565500: Event: system.tol2bus.slave[1]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1289 executed @ 7306565500
7306565500: Cache: system.cpu0.dcache: recvTimingResp: Handling response ReadExResp [8000ffc0:8000ffff] D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9824100
7306565500: Cache: system.cpu0.dcache: Block for addr 0x8000ffc0 being updated in Cache
7306565500: CacheRepl: system.cpu0.dcache: Replacement victim: state: 0 (I) valid: 0 writable: 0 readable: 0 dirty: 0 | tag: 0xffffffffffffffff set: 0x1ff way: 0
7306565500: Cache: system.cpu0.dcache: Block addr 0x8000ffc0 (ns) moving from state 0 (I) to state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x10001 set: 0x1ff way: 0
7306565500: CacheVerbose: system.cpu0.dcache: satisfyRequest for WriteReq [8000fff8:8000ffff] D=a071738000000000 ptr=0x558fc9802600 (write)
7306565500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306566500
7306565500: CacheVerbose: system.cpu0.dcache: recvTimingResp: Leaving with ReadExResp [8000ffc0:8000ffff] D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9824100
7306565500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306565500
7306565500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306566000
7306565500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306565500
7306565500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306566000
7306565500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306565500
7306565500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306566000
7306566000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306566000
7306566000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306566500
7306566000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306566000
7306566000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306566500
7306566000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306566000
7306566000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306566500
7306566500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306566500
7306566500: Event: system.tol2bus.respLayer1.wrapped_function_event: EventFunctionWrapped 1290 executed @ 7306566500
7306566500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306566500
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375168    :   add   x1, x1, #2048      : IntAlu :  D=0x0000000080a70800  FetchSeq=169  CPSeq=35  flags=(IsInteger)
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375172    :   subs   w0, #3602         : IntAlu :  D=0x0000000000000000  FetchSeq=170  CPSeq=36  flags=(IsInteger)
7306562500: ExecEnable: system.cpu7: A0 T0 : @_kernel_size_le_lo32+2144375176    :   b.ne   <_kernel_size_le_lo32+2144375184> : IntAlu :   FetchSeq=171  CPSeq=37  flags=(IsControl|IsDirectControl|IsCondControl)
7306566500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306567000
7306566500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306566500
7306566500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306567000
7306566500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306566500
7306566500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306567000
7306567000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306567000
7306567000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306567500
7306567000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306567000
7306567000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306567500
7306567000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306567000
7306567000: Cache: system.cpu7.icache: access for ReadReq [80737180:807371bf] IF UC D=40db82c98f5500006374696f6e577261707065642031313180f602d28f5500006564204020373330363535323530300a0000656e740000000400805207038052 ptr=0x558fc9802600
7306567000: CachePort: system.cpu7.icache.mem_side: Scheduling send event at 7306568000
7306567000: Event: system.cpu7.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 383 scheduled @ 7306568000
7306567000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306567500
7306567500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306567500
7306567500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306568000
7306567500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306567500
7306567500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306568000
7306567500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306567500
7306567500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306568000
7306568000: Event: system.cpu7.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 383 executed @ 7306568000
7306568000: Cache: system.cpu7.icache: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=40db82c98f5500006374696f6e577261707065642031313180f602d28f5500006564204020373330363535323530300a0000656e740000000400805207038052 ptr=0x558fc9802600
7306568000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[28] packet ReadReq [80737180:807371bf] IF UC D=c00f80c98f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363536383030300a00656420310a000030663438300000d0 ptr=0x558fc9824100
7306568000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[28] packet ReadReq [80737180:807371bf] IF UC D=c00f80c98f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363536383030300a00656420310a000030663438300000d0 ptr=0x558fc9824100
7306568000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[28] packet ReadReq [80737180:807371bf] IF UC D=c00f80c98f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363536383030300a00656420310a000030663438300000d0 ptr=0x558fc9824100 SF size: 0 lat: 0
7306568000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=c00f80c98f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363536383030300a00656420310a000030663438300000d0 ptr=0x558fc9824100
7306568000: Cache: system.l2: access for ReadReq [80737180:807371bf] IF UC D=c00f80c98f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363536383030300a00656420310a000030663438300000d0 ptr=0x558fc9824100
7306568000: CachePort: system.l2.mem_side: Scheduling send event at 7306578500
7306568000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306568500
7306568000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306568000 to 7306568500
7306568000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306568000
7306568000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f800
7306568000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f800
7306568000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306570000
7306568000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306573000
7306568000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306568000 to 7306573000
7306568000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306569250
7306568000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306568000
7306568000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306568500
7306568000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306568000
7306568000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306568500
7306568000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306568000
7306568000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306568500
7306568500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306568500
7306568500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306568500
7306568500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306569000
7306568500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306568500
7306568500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306569000
7306568500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306568500
7306568500: Cache: system.cpu0.icache: access for ReadReq [80993f80:80993fbf] IF D=c094d6d18f5500006374696f6e5772617070656420343232403d03d28f5500006564204020373330363536393530300a00000000000000000000000000000000 ptr=0x558fc9802400 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x20264 set: 0xfe way: 0
7306568500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306569500
7306568500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306569000
7306569000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306569000
7306569000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306569500
7306569000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306569000
7306569000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306569500
7306569000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306569000
7306569000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306569500
7306569250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306569250
7306569250: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824080 BUSY
7306569500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306569500
7306569500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306569500
7306569500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=8009d1d18f5500007565206c696d69742033322c206375720050aad38f5500006520312c20656e7472696573206e656564656420310a00000000000000000000 ptr=0x558fd070f280
7306569500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=809ad6d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802400
7306569500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=809ad6d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802400
7306569500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=809ad6d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802400 SF size: 0 lat: 1
7306569500: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=809ad6d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802400
7306569500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306569500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306569500: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306569500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306569500: DRAM: system.mem_ctrls: Adding to read queue
7306569500: DRAM: system.mem_ctrls: Request scheduled immediately
7306569500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306569500
7306569500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306571000
7306569500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306569500 to 7306571000
7306569500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306573500
7306569500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306569500
7306569500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306569500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306569500: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306569500: DRAM: system.mem_ctrls: Removing burstTick for 7306560000
7306569500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306569500
7306569500: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306588250 next burst at 7306574500.
7306569500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306569500
7306569500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306569500
7306569500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306569500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306569500
7306569500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306570000
7306569500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306569500
7306569500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306570000
7306569500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306569500
7306569500: Cache: system.cpu0.icache: access for ReadReq [80714980:807149bf] IF D=8089d6d18f5500006374696f6e577261707065642031323930206578656375746564204020373330363536363530300a0000000000000000a071738000000000 ptr=0x558fd070f580 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x201c5 set: 0x26 way: 0x1
7306569500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306570500
7306518500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area    :   mrs   x3, ctr_el0        : IntAlu :  D=0x000000008444c004  FetchSeq=13255188  CPSeq=11776681  flags=(IsInteger|IsSerializeBefore)
7306518500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+4    :   nop                      : IntAlu :   FetchSeq=13255189  CPSeq=11776681  flags=(IsNop)
7306569500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306570000
7306570000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306570000
7306570000: Cache: system.l2: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f800
7306570000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070f800
7306570000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306570000
7306518500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+8    :   ubfm   x3, x3, #16, #19  : IntAlu :  D=0x0000000000000004  FetchSeq=13255190  CPSeq=11776682  flags=(IsInteger)
7306518500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+12    :   movz   x2, #4, #0        : IntAlu :  D=0x0000000000000004  FetchSeq=13255191  CPSeq=11776683  flags=(IsInteger)
7306570000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306570500
7306570000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306570000
7306570000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306570500
7306570000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306570000
7306570000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306570500
7306570500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306570500
7306570500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306570500
7306570500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306571000
7306570500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306570500
7306570500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306571000
7306570500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306570500
7306518500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+16    :   lslv   x2, x2, x3        : IntAlu :  D=0x0000000000000040  FetchSeq=13255192  CPSeq=11776684  flags=(IsInteger)
7306518500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+20    :   add   x1, x0, x1         : IntAlu :  D=0xffffffc000010000  FetchSeq=13255193  CPSeq=11776685  flags=(IsInteger)
7306570500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306571000
7306571000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306571000
7306571000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306571000
7306571000: Cache: system.cpu0.icache: access for ReadReq [803378c0:803378ff] IF D=c032d4d18f5500000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f580 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x200cd set: 0xe3 way: 0
7306571000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306572000
7306518500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+24    :   sub   x3, x2, #1         : IntAlu :  D=0x000000000000003f  FetchSeq=13255194  CPSeq=11776686  flags=(IsInteger)
7306571000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306571500
7306571000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306571000
7306571000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306571500
7306571000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306571000
7306571000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306571500
7306571500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306571500
7306571500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306572000
7306571500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306571500
7306571500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306572000
7306571500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306571500
7306518500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+28    :   bic   x0, x0, x3         : IntAlu :  D=0xffffffc00000ffc0  FetchSeq=13255195  CPSeq=11776687  flags=(IsInteger)
7306571500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306572000
7306572000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306572000
7306572000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306572000
7306519500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+32    :   dc civac   , x0          : MemWrite :  A=0xffffffc00000ffc0  FetchSeq=13255196  CPSeq=11776688  flags=(IsInteger|IsMemRef|IsStore)
7306519500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+36    :   add   x0, x0, x2         : IntAlu :  D=0xffffffc000010000  FetchSeq=13255197  CPSeq=11776689  flags=(IsInteger)
7306572000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306572500
7306572000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306572000
7306572000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306572500
7306572000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306572000
7306572000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 scheduled @ 7306572500
7306572500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 364 executed @ 7306572500
7306572500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306572500
7306572500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306573000
7306572500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306572500
7306519500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+40    :   subs   x0, x1            : IntAlu :  D=0x0000000000000001  FetchSeq=13255198  CPSeq=11776690  flags=(IsInteger)
7306572500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306573000
7306573000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306573000
7306573000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824080
7306573000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824080
7306573000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306575000
7306573000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306578000
7306573000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306573000 to 7306578000
7306573000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306573750
7306573000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306573000
7306573000: Cache: system.cpu0.dcache: access for CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f580 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x10001 set: 0x1ff way: 0
7306573000: CachePort: system.cpu0.dcache.mem_side: Scheduling send event at 7306574000
7306573000: Event: system.cpu0.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 55 scheduled @ 7306574000
7306519500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+44    :   b.cc   <__flush_dcache_area+32> : IntAlu :   FetchSeq=13255199  CPSeq=11776691  flags=(IsControl|IsDirectControl|IsCondControl)
7306573000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306573500
7306573000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306573000
7306573000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306573500
7306573500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306573500
7306573500: Cache: system.l2: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306573500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306573500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306573500: SnoopFilter: system.membus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306573500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480 SF size: 0 lat: 1
7306573500: CoherentXBar: system.membus: forwardTiming for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306573500: DRAM: system.mem_ctrls: recvTimingReq: request WriteReq addr 0x80a70800 size 4
7306573500: DRAM: system.mem_ctrls: Write queue limit 64, current size 25, entries needed 1
7306573500: DRAM: system.mem_ctrls: Address: 0xa70800 Rank 1 Bank 0 Row 83
7306573500: DRAM: system.mem_ctrls: Adding to write queue
7306573500: DRAM: system.mem_ctrls: Responding to Address 0x80a70800
7306573500: DRAM: system.mem_ctrls: Done: WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306573500: DRAM: system.mem_ctrls: Request scheduled immediately
7306573500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306573500
7306573500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306576000
7306573500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306573500 to 7306576000
7306573500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306574500
7306573500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306573500
7306573500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306573500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306573500
7306573500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306574000
7306573500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306573500
7306573500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306574000
7306573750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306573750
7306573750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070ff80 BUSY
7306574000: Event: system.cpu0.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 55 executed @ 7306574000
7306574000: Cache: system.cpu0.dcache: sendMSHRQueuePacket: MSHR CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f580
7306574000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[1] packet CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800
7306574000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[1] packet CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800
7306574000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306574000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306574000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[1] packet CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800 SF size: 0 lat: 0
7306574000: CoherentXBar: system.tol2bus: forwardTiming for CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800
7306574000: Cache: system.l2: access for CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800 hit state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: 0 | tag: 0x2000 set: 0x3ff way: 0x1
7306574000: CachePort: system.l2.mem_side: Scheduling send event at 7306584500
7306574000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306574500
7306574000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306574000 to 7306574500
7306574000: CacheVerbose: system.cpu0.dcache: sendMSHRQueuePacket: packet CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800 found block: state: b (M) valid: 1 writable: 1 readable: 0 dirty: 1 | tag: 0x10001 set: 0x1ff way: 0
7306574000: Cache: system.cpu0.dcache: Create WriteClean [8000ffc0:8000ffff] PoC D= ptr=0x558fc9802c00 writable: 1, dirty: 1
7306574000: CachePort: system.cpu0.dcache.mem_side: Scheduling send event at 0
7306574000: Event: system.cpu0.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 55 scheduled @ 7306574001
7306574000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306574000
7306574000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802d00
7306574000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[8] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802d00
7306574000: Event: system.tol2bus.slave[8]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1303 scheduled @ 7306574500
7306574000: Event: system.tol2bus.respLayer8.wrapped_function_event: EventFunctionWrapped 1304 scheduled @ 7306575500
7306574000: BaseXBar: system.tol2bus.respLayer8: The crossbar layer is now busy from tick 7306574000 to 7306575500
7306574000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306579000
7306574000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306574000
7306574000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306574500
7306574000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306574000
7306574000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306574500
7306574001: Event: system.cpu0.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 55 executed @ 7306574001
7306574001: Cache: system.cpu0.dcache: sendWriteQueuePacket: write WriteClean [8000ffc0:8000ffff] PoC D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9802c00
7306574001: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[1] packet WriteClean [8000ffc0:8000ffff] PoC D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9802c00 BUSY
7306574500: Event: system.tol2bus.slave[8]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1303 executed @ 7306574500
7306574500: Cache: system.cpu2.icache: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802d00
7306574500: Event: system.cpu2.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 156 scheduled @ 7306576500
7306574500: CacheVerbose: system.cpu2.icache: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802d00
7306574500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306574500
7306574500: Cache: system.cpu0.dcache: sendWriteQueuePacket: write WriteClean [8000ffc0:8000ffff] PoC D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9802c00
7306574500: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[1] packet WriteClean [8000ffc0:8000ffff] PoC D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9802c00
7306574500: Cache: system.l2: access for WriteClean [8000ffc0:8000ffff] PoC D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9802c00 hit state: 3 (E) valid: 1 writable: 1 readable: 0 dirty: 0 | tag: 0x2000 set: 0x3ff way: 0x1
7306574500: Cache: system.l2: access new state is state: 3 (E) valid: 1 writable: 1 readable: 0 dirty: 0 | tag: 0x2000 set: 0x3ff way: 0x1
7306574500: CachePort: system.l2.mem_side: Scheduling send event at 7306585000
7306574500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306576000
7306574500: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306574500 to 7306576000
7306574500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306574500
7306574500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=800880c98f5500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e740000bbeac88f5500000000000000000000 ptr=0x558fc9802200
7306574500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=401b80c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802d00 BUSY
7306574500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306574500
7306574500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306575000
7306574500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306574500
7306574500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306575000
7306575000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306575000
7306575000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824080
7306575000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9824080
7306575000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306575000
7306575000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306575500
7306575000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306575000
7306575000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306575500
7306575500: Event: system.tol2bus.respLayer8.wrapped_function_event: EventFunctionWrapped 1304 executed @ 7306575500
7306575500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306575500
7306575500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306576000
7306575500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306575500
7306575500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306576000
7306576000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306576000
7306576000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306576000
7306576000: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=800880c98f5500006f6c326275732e7265714c61796572302e777261707065645f66756e6374696f6e5f6576656e740000bbeac88f5500000000000000000000 ptr=0x558fc9802200
7306576000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=0033d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9824080
7306576000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=0033d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9824080
7306576000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=0033d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9824080 SF size: 0 lat: 1
7306576000: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=0033d4d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9824080
7306576000: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306576000: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306576000: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306576000: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306576000: DRAM: system.mem_ctrls: Adding to read queue
7306576000: DRAM: system.mem_ctrls: Request scheduled immediately
7306576000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306576000
7306576000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306577000
7306576000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306576000 to 7306577000
7306576000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306578500
7306576000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306576000
7306576000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306576000: DRAM: system.mem_ctrls: Single request, going to a free rank
7306576000: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306576000: DRAM: system.mem_ctrls: Removing burstTick for 7306565000
7306576000: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306576000
7306576000: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306594750 next burst at 7306581000.
7306576000: DRAM: system.mem_ctrls: Precharging bank 3, rank 1 at tick 7306583500, now got 4 active
7306576000: Event: system.mem_ctrls_1.wrapped_function_event: EventFunctionWrapped 20 scheduled @ 7306597250
7306576000: DRAM: system.mem_ctrls: Auto-precharged bank: 11
7306576000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306576000
7306576000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306576000
7306576000: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306576000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306576000
7306576000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306576500
7306576000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306576000
7306576000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306576500
7306576500: Event: system.cpu2.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 156 executed @ 7306576500
7306576500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306576500
7306576500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306577000
7306576500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306576500
7306576500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306577000
7306577000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306577000
7306577000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306577000
7306577000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306577500
7306577000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306577000
7306577000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306577500
7306577250: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306577250
7306577250: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306577250: DRAM: system.mem_ctrls: number of read entries for rank 1 is 3
7306577250: DRAM: system.mem_ctrls: Responding to Address 0x807371c0
7306577250: DRAM: system.mem_ctrls: Done: ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802b80
7306577250: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306582250
7306577500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306577500
7306577500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306578000
7306577500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306577500
7306577500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306578000
7306578000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306578000
7306578000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070ff80
7306578000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070ff80
7306578000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306580000
7306578000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306583000
7306578000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306578000 to 7306583000
7306578000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306579250
7306578000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306578000
7306578000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306578500
7306578000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306578000
7306578000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306578500
7306578500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306578500
7306578500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [80737180:807371bf] IF UC D=c00f80c98f5500006374696f6e5772617070656420333634207363686564756c6564204020373330363536383030300a00656420310a000030663438300000d0 ptr=0x558fc9824100
7306578500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=0033d4d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070f880
7306578500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=0033d4d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070f880
7306578500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [80737180:807371bf] IF UC D=0033d4d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070f880 SF size: 0 lat: 1
7306578500: CoherentXBar: system.membus: forwardTiming for ReadReq [80737180:807371bf] IF UC D=0033d4d18f55000070d5e9cd8f550000e0d5e9cd8f55000050d6e9cd8f550000c0d6e9cd8f55000030d7e9cd8f550000a0d7e9cd8f55000010d8e9cd8f550000 ptr=0x558fd070f880
7306578500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x80737180 size 64
7306578500: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306578500: DRAM: system.mem_ctrls: Address: 0x737180 Rank 1 Bank 3 Row 57
7306578500: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306578500: DRAM: system.mem_ctrls: Adding to read queue
7306578500: DRAM: system.mem_ctrls: Request scheduled immediately
7306578500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306578500
7306578500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306580000
7306578500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306578500 to 7306580000
7306578500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306583000
7306578500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306578500
7306578500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306578500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306578500: DRAM: system.mem_ctrls: Timing access to addr 0x737180, rank/bank/row 1 3 57
7306578500: DRAM: system.mem_ctrls: Removing burstTick for 7306575000
7306578500: DRAM: system.mem_ctrls: Activate at tick 7306597250
7306578500: DRAM: system.mem_ctrls: Activate bank 3, rank 1 at tick 7306597250, now got 5 active
7306578500: Event: system.mem_ctrls_1.wrapped_function_event: EventFunctionWrapped 19 scheduled @ 7306597250
7306578500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306611000
7306578500: DRAM: system.mem_ctrls: Access to 0x737180, ready at 7306629750 next burst at 7306616000.
7306578500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306588500
7306578500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306578500
7306578500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306579000
7306578500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306578500
7306578500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306579000
7306579000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306579000
7306579000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600
7306579000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[8] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600
7306579000: Event: system.tol2bus.slave[8]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1303 scheduled @ 7306579500
7306579000: Event: system.tol2bus.respLayer8.wrapped_function_event: EventFunctionWrapped 1304 scheduled @ 7306580500
7306579000: BaseXBar: system.tol2bus.respLayer8: The crossbar layer is now busy from tick 7306579000 to 7306580500
7306579000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306584000
7306579000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306579000
7306579000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306579500
7306579000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306579000
7306579000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306579500
7306579250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306579250
7306579250: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fc80 BUSY
7306579500: Event: system.tol2bus.slave[8]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1303 executed @ 7306579500
7306579500: Cache: system.cpu2.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600
7306579500: Event: system.cpu2.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 156 scheduled @ 7306581500
7306579500: CacheVerbose: system.cpu2.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070f600
7306579500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306579500
7306579500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306580000
7306579500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306579500
7306579500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306580000
7306580000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306580000
7306580000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306580000
7306580000: Cache: system.l2: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070ff80
7306580000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070ff80
7306580000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306580000
7306580000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306580500
7306580000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306580000
7306580000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306580500
7306580500: Event: system.tol2bus.respLayer8.wrapped_function_event: EventFunctionWrapped 1304 executed @ 7306580500
7306580500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306580500
7306580500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306581000
7306580500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306580500
7306580500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306581000
7306581000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306581000
7306581000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306581500
7306581000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306581000
7306581000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306581500
7306581500: Event: system.cpu2.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 156 executed @ 7306581500
7306581500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306581500
7306581500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306581500
7306581500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306582000
7306581500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306581500
7306581500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306582000
7306581500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306581500
7306581500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306582000
7306582000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306582000
7306582000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306582500
7306582000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306582000
7306582000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306582500
7306582000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306582000
7306582000: Cache: system.cpu2.icache: access for ReadReq [807371c0:807371ff] IF UC D=c02dd4d18f5500006374696f6e5772617070656420313536207363686564756c6564204020373330363537363530300a0000eac88f55000060ded1d18f550000 ptr=0x558fc9802b00
7306582000: CachePort: system.cpu2.icache.mem_side: Scheduling send event at 7306583000
7306582000: Event: system.cpu2.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 158 scheduled @ 7306583000
7306582000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306582500
7306582250: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306582250
7306582250: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306582250: DRAM: system.mem_ctrls: number of read entries for rank 1 is 3
7306582250: DRAM: system.mem_ctrls: Responding to Address 0x80737180
7306582250: DRAM: system.mem_ctrls: Done: ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802800
7306582250: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306588250
7306582500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306582500
7306582500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306583000
7306582500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306582500
7306582500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306583000
7306582500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306582500
7306582500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306583000
7306583000: Event: system.cpu2.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 158 executed @ 7306583000
7306583000: Cache: system.cpu2.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c02dd4d18f5500006374696f6e5772617070656420313536207363686564756c6564204020373330363537363530300a0000eac88f55000060ded1d18f550000 ptr=0x558fc9802b00
7306583000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[8] packet ReadReq [807371c0:807371ff] IF UC D=80b7acd38f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363538333030300a006561647954696d650a000000000000 ptr=0x558fd070ff80
7306583000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[8] packet ReadReq [807371c0:807371ff] IF UC D=80b7acd38f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363538333030300a006561647954696d650a000000000000 ptr=0x558fd070ff80
7306583000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[8] packet ReadReq [807371c0:807371ff] IF UC D=80b7acd38f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363538333030300a006561647954696d650a000000000000 ptr=0x558fd070ff80 SF size: 0 lat: 0
7306583000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=80b7acd38f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363538333030300a006561647954696d650a000000000000 ptr=0x558fd070ff80
7306583000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=80b7acd38f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363538333030300a006561647954696d650a000000000000 ptr=0x558fd070ff80
7306583000: CachePort: system.l2.mem_side: Scheduling send event at 7306593500
7306583000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306583500
7306583000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306583000 to 7306583500
7306583000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306583000
7306583000: Cache: system.l2: sendWriteQueuePacket: write CleanEvict [80a70800:80a7083f] D= ptr=0x558fc9802500
7306583000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet CleanEvict [80a70800:80a7083f] D= ptr=0x558fc9802500
7306583000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet CleanEvict [80a70800:80a7083f] D= ptr=0x558fc9802500
7306583000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306583000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306583000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet CleanEvict [80a70800:80a7083f] D= ptr=0x558fc9802500 SF size: 0 lat: 1
7306583000: CoherentXBar: system.membus: recvTimingReq: Not forwarding CleanEvict [80a70800:80a7083f] D= ptr=0x558fc9802500
7306583000: SnoopFilter: system.membus.snoop_filter: eraseIfNullEntry:   Removed SF entry.
7306583000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306584000
7306583000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306583000 to 7306584000
7306583000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306584500
7306583000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306583000
7306583000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fc80
7306583000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fc80
7306583000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306585000
7306583000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306588000
7306583000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306583000 to 7306588000
7306583000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306584250
7306583000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306583000
7306583000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306583500
7306583000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306583000
7306583000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306583500
7306583000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306583000
7306583000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306583500
7306583500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306583500
7306583500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306583500
7306583500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306584000
7306583500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306583500
7306583500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306584000
7306583500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306583500
7306583500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306584000
7306584000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306584000
7306584000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306584000
7306584000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9824180
7306584000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[12] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9824180
7306584000: Event: system.tol2bus.slave[12]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1311 scheduled @ 7306584500
7306584000: Event: system.tol2bus.respLayer12.wrapped_function_event: EventFunctionWrapped 1312 scheduled @ 7306585500
7306584000: BaseXBar: system.tol2bus.respLayer12: The crossbar layer is now busy from tick 7306584000 to 7306585500
7306584000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306589000
7306584000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306584000
7306584000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306584500
7306584000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306584000
7306584000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306584500
7306584000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306584000
7306584000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306584500
7306584250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306584250
7306584250: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fe80 BUSY
7306584500: Event: system.tol2bus.slave[12]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1311 executed @ 7306584500
7306584500: Cache: system.cpu3.icache: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9824180
7306584500: Event: system.cpu3.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 201 scheduled @ 7306586500
7306584500: CacheVerbose: system.cpu3.icache: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9824180
7306584500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306584500
7306584500: Cache: system.l2: sendWriteQueuePacket: write WriteClean [8000ffc0:8000ffff] PoC D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9802c00
7306584500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WriteClean [8000ffc0:8000ffff] PoC D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9802c00
7306584500: DRAM: system.mem_ctrls: recvTimingReq: request WriteClean addr 0x8000ffc0 size 64
7306584500: DRAM: system.mem_ctrls: Write queue limit 64, current size 26, entries needed 1
7306584500: DRAM: system.mem_ctrls: Merging write burst with existing queue entry
7306584500: DRAM: system.mem_ctrls: Responding to Address 0x8000ffc0
7306584500: DRAM: system.mem_ctrls: Done: WriteClean [8000ffc0:8000ffff] PoC D=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a071738000000000 ptr=0x558fc9802c00
7306584500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306590000
7306584500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306584500 to 7306590000
7306584500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306584501
7306584500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306584500
7306584500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306585000
7306584500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306584500
7306584500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306585000
7306584500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306584500
7306584500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306585000
7306584501: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306584501
7306584501: Cache: system.l2: sendMSHRQueuePacket: MSHR CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800
7306584501: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f300 BUSY
7306585000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306585000
7306585000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fc80
7306585000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fd070fc80
7306585000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306585000
7306585000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306585500
7306585000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306585000
7306585000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306585500
7306585000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306585000
7306581500: ExecEnable: system.cpu2: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306585000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306585500
7306585500: Event: system.tol2bus.respLayer12.wrapped_function_event: EventFunctionWrapped 1312 executed @ 7306585500
7306585500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306585500
7306585500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306586000
7306585500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306585500
7306585500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306586000
7306585500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306585500
7306585500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306586000
7306586000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306586000
7306586000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306586500
7306586000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306586000
7306586000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306586500
7306586000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306586000
7306586000: Cache: system.cpu2.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306586000: CachePort: system.cpu2.dcache.mem_side: Scheduling send event at 7306587000
7306586000: Event: system.cpu2.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 145 scheduled @ 7306587000
7306586000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306586500
7306586500: Event: system.cpu3.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 201 executed @ 7306586500
7306586500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306586500
7306586500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306587000
7306586500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306586500
7306586500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306587000
7306586500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306586500
7306586500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306587000
7306587000: Event: system.cpu2.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 145 executed @ 7306587000
7306587000: Cache: system.cpu2.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306587000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[9] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306587000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[9] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306587000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[9] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80 SF size: 0 lat: 0
7306587000: CoherentXBar: system.tol2bus: forwardTiming for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306587000: Cache: system.l2: access for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306587000: CachePort: system.l2.mem_side: Scheduling send event at 7306597500
7306587000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306588000
7306587000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306587000 to 7306588000
7306587000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306587000
7306587000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306587500
7306587000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306587000
7306587000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306587500
7306587000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306587000
7306587000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306587500
7306587500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306587500
7306587500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306588000
7306587500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306587500
7306587500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306588000
7306587500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306587500
7306587500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306588000
7306588000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306588000
7306588000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306588000
7306588000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fe80
7306588000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fe80
7306588000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306590000
7306588000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306593000
7306588000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306588000 to 7306593000
7306588000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306589250
7306588000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306588000
7306588000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306588500
7306588000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306588000
7306588000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306588500
7306588000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306588000
7306588000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306588500
7306588250: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306588250
7306588250: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306588250: DRAM: system.mem_ctrls: number of read entries for rank 1 is 2
7306588250: DRAM: system.mem_ctrls: Responding to Address 0x807371c0
7306588250: DRAM: system.mem_ctrls: Done: ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802400
7306588250: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306594750
7306588500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306588500
7306588500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306588500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306588500
7306588500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306589000
7306588500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306588500
7306588500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306589000
7306588500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306588500
7306588500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306589000
7306589000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306589000
7306589000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc8fb7f80
7306589000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[12] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc8fb7f80
7306589000: Event: system.tol2bus.slave[12]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1311 scheduled @ 7306589500
7306589000: Event: system.tol2bus.respLayer12.wrapped_function_event: EventFunctionWrapped 1312 scheduled @ 7306590500
7306589000: BaseXBar: system.tol2bus.respLayer12: The crossbar layer is now busy from tick 7306589000 to 7306590500
7306589000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306594000
7306589000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306589000
7306589000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306589500
7306589000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306589000
7306589000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306589500
7306589000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306589000
7306589000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306589500
7306589250: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306589250
7306589250: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802a00 BUSY
7306589500: Event: system.tol2bus.slave[12]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1311 executed @ 7306589500
7306589500: Cache: system.cpu3.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc8fb7f80
7306589500: Event: system.cpu3.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 201 scheduled @ 7306591500
7306589500: CacheVerbose: system.cpu3.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc8fb7f80
7306589500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306589500
7306589500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306590000
7306589500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306589500
7306589500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306590000
7306589500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306589500
7306589500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306590000
7306590000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306590000
7306590000: Cache: system.l2: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fe80
7306590000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fe80
7306590000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306590000
7306590000: Cache: system.l2: sendMSHRQueuePacket: MSHR CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800
7306590000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fe80
7306590000: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fe80
7306590000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306590000: SnoopFilter: system.membus.snoop_filter: lookupRequest:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306590000: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fe80 SF size: 0 lat: 1
7306590000: CoherentXBar: system.membus: forwardTiming for CleanInvalidReq [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fe80
7306590000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306591000
7306590000: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306590000 to 7306591000
7306590000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet CleanInvalidResp [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fe80
7306590000: SnoopFilter: system.membus.snoop_filter: updateResponse:   old SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306590000: SnoopFilter: system.membus.snoop_filter: eraseIfNullEntry:   Removed SF entry.
7306590000: SnoopFilter: system.membus.snoop_filter: updateResponse:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306590000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306598000
7306590000: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306593500
7306590000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306590000
7306590000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306590500
7306590000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306590000
7306590000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306590500
7306590000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306590000
7306590000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306590500
7306590500: Event: system.tol2bus.respLayer12.wrapped_function_event: EventFunctionWrapped 1312 executed @ 7306590500
7306590500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306590500
7306590500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306591000
7306590500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306590500
7306590500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306591000
7306590500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306590500
7306590500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306591000
7306591000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306591000
7306591000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306591000
7306591000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306591500
7306591000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306591000
7306591000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306591500
7306591000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306591000
7306591000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306591500
7306591500: Event: system.cpu3.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 201 executed @ 7306591500
7306591500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306591500
7306591500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306591500
7306591500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306592000
7306591500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306591500
7306591500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306592000
7306591500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306591500
7306591500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306592000
7306591500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306591500
7306591500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306592000
7306592000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306592000
7306592000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306592500
7306592000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306592000
7306592000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306592500
7306592000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306592000
7306592000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306592500
7306592000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306592000
7306592000: Cache: system.cpu3.icache: access for ReadReq [807371c0:807371ff] IF UC D=c046d2d18f550000d07a3fd5fd7f0000b85380b301000000a05780b3010000001800000000000000002980c98f5500000000000000010000a544865a467c0653 ptr=0x558fc8fb7c80
7306592000: CachePort: system.cpu3.icache.mem_side: Scheduling send event at 7306593000
7306592000: Event: system.cpu3.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 203 scheduled @ 7306593000
7306592000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306592500
7306592500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306592500
7306592500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306593000
7306592500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306592500
7306592500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306593000
7306592500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306592500
7306592500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306593000
7306592500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306592500
7306592500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306593000
7306593000: Event: system.cpu3.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 203 executed @ 7306593000
7306593000: Cache: system.cpu3.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c046d2d18f550000d07a3fd5fd7f0000b85380b301000000a05780b3010000001800000000000000002980c98f5500000000000000010000a544865a467c0653 ptr=0x558fc8fb7c80
7306593000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[12] packet ReadReq [807371c0:807371ff] IF UC D=4010d1d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363539333030300a0000c39a0100018b430400d10000238a ptr=0x558fc8fb7f80
7306593000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[12] packet ReadReq [807371c0:807371ff] IF UC D=4010d1d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363539333030300a0000c39a0100018b430400d10000238a ptr=0x558fc8fb7f80
7306593000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[12] packet ReadReq [807371c0:807371ff] IF UC D=4010d1d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363539333030300a0000c39a0100018b430400d10000238a ptr=0x558fc8fb7f80 SF size: 0 lat: 0
7306593000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=4010d1d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363539333030300a0000c39a0100018b430400d10000238a ptr=0x558fc8fb7f80
7306593000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=4010d1d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363539333030300a0000c39a0100018b430400d10000238a ptr=0x558fc8fb7f80
7306593000: CachePort: system.l2.mem_side: Scheduling send event at 7306603500
7306593000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306593500
7306593000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306593000 to 7306593500
7306593000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306593000
7306593000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802a00
7306593000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802a00
7306593000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 rescheduled @ 7306595000
7306593000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306598000
7306593000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306593000 to 7306598000
7306593000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306593001
7306593000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306593000
7306593000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306593500
7306593000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306593000
7306593000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306593500
7306593000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306593000
7306593000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306593500
7306593000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306593000
7306593000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306593500
7306593001: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306593001
7306593001: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480 BUSY
7306593500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306593500
7306593500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306593500
7306593500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=80b7acd38f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363538333030300a006561647954696d650a000000000000 ptr=0x558fd070ff80
7306593500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=40d882c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802900
7306593500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=40d882c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802900
7306593500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=40d882c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802900 SF size: 0 lat: 1
7306593500: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=40d882c98f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802900
7306593500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306593500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306593500: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306593500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306593500: DRAM: system.mem_ctrls: Adding to read queue
7306593500: DRAM: system.mem_ctrls: Request scheduled immediately
7306593500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306593500
7306593500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306595000
7306593500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306593500 to 7306595000
7306593500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306597500
7306593500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306593500
7306593500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306593500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306593500: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306593500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306616000
7306593500: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306634750 next burst at 7306621000.
7306593500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306593500
7306593500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306593500
7306593500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306593500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306593500
7306593500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306594000
7306593500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306593500
7306593500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306594000
7306593500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306593500
7306593500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306594000
7306593500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306593500
7306593500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306594000
7306594000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306594000
7306594000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802180
7306594000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[16] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802180
7306594000: Event: system.tol2bus.slave[16]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1319 scheduled @ 7306594500
7306594000: Event: system.tol2bus.respLayer16.wrapped_function_event: EventFunctionWrapped 1320 scheduled @ 7306595500
7306594000: BaseXBar: system.tol2bus.respLayer16: The crossbar layer is now busy from tick 7306594000 to 7306595500
7306594000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306599000
7306594000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306594000
7306594000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306594500
7306594000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306594000
7306594000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306594500
7306594000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306594000
7306594000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306594500
7306594000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306594000
7306594000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306594500
7306594500: Event: system.tol2bus.slave[16]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1319 executed @ 7306594500
7306594500: Cache: system.cpu4.icache: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802180
7306594500: Event: system.cpu4.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 246 scheduled @ 7306596500
7306594500: CacheVerbose: system.cpu4.icache: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802180
7306594500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306594500
7306594500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306595000
7306594500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306594500
7306594500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306595000
7306594500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306594500
7306594500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306595000
7306594500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306594500
7306594500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306595000
7306594750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 executed @ 7306594750
7306594750: DRAM: system.mem_ctrls: processRespondEvent(): Some req has reached its readyTime
7306594750: DRAM: system.mem_ctrls: number of read entries for rank 1 is 2
7306594750: DRAM: system.mem_ctrls: Responding to Address 0x807371c0
7306594750: DRAM: system.mem_ctrls: Done: ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9824080
7306594750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 11 scheduled @ 7306629750
7306595000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306595000
7306595000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306595000
7306595000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802a00
7306595000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802a00
7306595000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306598000
7306595000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306595000
7306595000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306595500
7306595000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306595000
7306595000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306595500
7306595000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306595000
7306595000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306595500
7306595000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306595000
7306591500: ExecEnable: system.cpu3: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306595000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306595500
7306595500: Event: system.tol2bus.respLayer16.wrapped_function_event: EventFunctionWrapped 1320 executed @ 7306595500
7306595500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306595500
7306595500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306596000
7306595500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306595500
7306595500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306596000
7306595500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306595500
7306595500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306596000
7306595500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306595500
7306595500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306596000
7306596000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306596000
7306596000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306596500
7306596000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306596000
7306596000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306596500
7306596000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306596000
7306596000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306596500
7306596000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306596000
7306596000: Cache: system.cpu3.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306596000: CachePort: system.cpu3.dcache.mem_side: Scheduling send event at 7306597000
7306596000: Event: system.cpu3.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 190 scheduled @ 7306597000
7306596000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306596500
7306596500: Event: system.cpu4.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 246 executed @ 7306596500
7306596500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306596500
7306596500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306597000
7306596500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306596500
7306596500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306597000
7306596500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306596500
7306596500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306597000
7306596500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306596500
7306596500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306597000
7306597000: Event: system.cpu3.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 190 executed @ 7306597000
7306597000: Cache: system.cpu3.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306597000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[13] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306597000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[13] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306597000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[13] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00 SF size: 0 lat: 0
7306597000: CoherentXBar: system.tol2bus: forwardTiming for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306597000: Cache: system.l2: access for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306597000: CachePort: system.l2.mem_side: Scheduling send event at 7306607500
7306597000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306598000
7306597000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306597000 to 7306598000
7306597000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306597000
7306597000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306597500
7306597000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306597000
7306597000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306597500
7306597000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306597000
7306597000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306597500
7306597000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306597000
7306597000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306597500
7306597250: Event: system.mem_ctrls_1.wrapped_function_event: EventFunctionWrapped 19 executed @ 7306597250
7306597250: Event: system.mem_ctrls_1.wrapped_function_event: EventFunctionWrapped 20 executed @ 7306597250
7306597500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306597500
7306597500: Cache: system.l2: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306597500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306597500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306597500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80 SF size: 0 lat: 1
7306597500: CoherentXBar: system.membus: forwardTiming for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306597500: DRAM: system.mem_ctrls: recvTimingReq: request WriteReq addr 0x80a70800 size 4
7306597500: DRAM: system.mem_ctrls: Write queue limit 64, current size 26, entries needed 1
7306597500: DRAM: system.mem_ctrls: Merging write burst with existing queue entry
7306597500: DRAM: system.mem_ctrls: Responding to Address 0x80a70800
7306597500: DRAM: system.mem_ctrls: Done: WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80
7306597500: DRAM: system.mem_ctrls: Request scheduled immediately
7306597500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306597500
7306597500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306600000
7306597500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306597500 to 7306600000
7306597500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306603500
7306597500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306597500
7306597500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306597500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306597500
7306597500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306598000
7306597500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306597500
7306597500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306598000
7306597500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306597500
7306597500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306598000
7306597500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306597500
7306597500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306598000
7306598000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306598000
7306598000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306598000
7306598000: Cache: system.l2: recvTimingResp: Handling response CleanInvalidResp [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fe80
7306598000: CacheVerbose: system.l2: recvTimingResp: Leaving with CleanInvalidResp [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fe80
7306598000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306598000
7306598000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306598000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306598000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306600000
7306598000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306599000
7306598000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306598000 to 7306599000
7306598000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306605750
7306598000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306598000
7306598000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306598500
7306598000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306598000
7306598000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306598500
7306598000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306598000
7306598000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306598500
7306598000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306598000
7306598000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306598500
7306598500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306598500
7306598500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306599000
7306598500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306598500
7306598500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306599000
7306598500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306598500
7306598500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306599000
7306598500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306598500
7306598500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306599000
7306599000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306599000
7306599000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306599000
7306599000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc8fb7d00
7306599000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[16] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc8fb7d00
7306599000: Event: system.tol2bus.slave[16]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1319 scheduled @ 7306599500
7306599000: Event: system.tol2bus.respLayer16.wrapped_function_event: EventFunctionWrapped 1320 scheduled @ 7306600500
7306599000: BaseXBar: system.tol2bus.respLayer16: The crossbar layer is now busy from tick 7306599000 to 7306600500
7306599000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306604000
7306599000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306599000
7306599000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306599500
7306599000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306599000
7306599000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306599500
7306599000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306599000
7306599000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306599500
7306599000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306599000
7306599000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306599500
7306599500: Event: system.tol2bus.slave[16]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1319 executed @ 7306599500
7306599500: Cache: system.cpu4.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc8fb7d00
7306599500: Event: system.cpu4.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 246 scheduled @ 7306601500
7306599500: CacheVerbose: system.cpu4.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc8fb7d00
7306599500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306599500
7306599500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306600000
7306599500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306599500
7306599500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306600000
7306599500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306599500
7306599500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306600000
7306599500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306599500
7306599500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306600000
7306600000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306600000
7306600000: Cache: system.l2: recvTimingResp: Handling response WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306600000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306600000
7306600000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306600000
7306600000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306600500
7306600000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306600000
7306600000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306600500
7306600000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306600000
7306600000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306600500
7306600000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306600000
7306600000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306600500
7306600500: Event: system.tol2bus.respLayer16.wrapped_function_event: EventFunctionWrapped 1320 executed @ 7306600500
7306600500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306600500
7306600500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306601000
7306600500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306600500
7306600500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306601000
7306600500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306600500
7306600500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306601000
7306600500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306600500
7306600500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306601000
7306601000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306601000
7306601000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306601500
7306601000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306601000
7306601000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306601500
7306601000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306601000
7306601000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306601500
7306601000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306601000
7306601000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306601500
7306601500: Event: system.cpu4.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 246 executed @ 7306601500
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306601500
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306601500
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306602000
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306601500
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306602000
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306601500
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306602000
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306601500
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306602000
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306601500
7306601500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306602000
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306602000
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306602500
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306602000
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306602500
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306602000
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306602500
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306602000
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306602500
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306602000
7306602000: Cache: system.cpu4.icache: access for ReadReq [807371c0:807371ff] IF UC D=c032d4d18f5500006374696f6e5772617070656420323436207363686564756c6564204020373330363539363530300a000035370a00000090d4e9cd8f550000 ptr=0x558fd070f500
7306602000: CachePort: system.cpu4.icache.mem_side: Scheduling send event at 7306603000
7306602000: Event: system.cpu4.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 248 scheduled @ 7306603000
7306602000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306602500
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306602500
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306603000
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306602500
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306603000
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306602500
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306603000
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306602500
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306603000
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306602500
7306602500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306603000
7306603000: Event: system.cpu4.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 248 executed @ 7306603000
7306603000: Cache: system.cpu4.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c032d4d18f5500006374696f6e5772617070656420323436207363686564756c6564204020373330363539363530300a000035370a00000090d4e9cd8f550000 ptr=0x558fd070f500
7306603000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[16] packet ReadReq [807371c0:807371ff] IF UC D=0037d4d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363630333030300a0000b2c98f550000e0039fd6c11900b0 ptr=0x558fc8fb7d00
7306603000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[16] packet ReadReq [807371c0:807371ff] IF UC D=0037d4d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363630333030300a0000b2c98f550000e0039fd6c11900b0 ptr=0x558fc8fb7d00
7306603000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[16] packet ReadReq [807371c0:807371ff] IF UC D=0037d4d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363630333030300a0000b2c98f550000e0039fd6c11900b0 ptr=0x558fc8fb7d00 SF size: 0 lat: 0
7306603000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=0037d4d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363630333030300a0000b2c98f550000e0039fd6c11900b0 ptr=0x558fc8fb7d00
7306603000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=0037d4d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363630333030300a0000b2c98f550000e0039fd6c11900b0 ptr=0x558fc8fb7d00
7306603000: CachePort: system.l2.mem_side: Scheduling send event at 7306613500
7306603000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306603500
7306603000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306603000 to 7306603500
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306603000
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306603500
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306603000
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306603500
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306603000
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306603500
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306603000
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306603500
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306603000
7306603000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306603500
7306603500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306603500
7306603500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306603500
7306603500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=4010d1d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363539333030300a0000c39a0100018b430400d10000238a ptr=0x558fc8fb7f80
7306603500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=40bcacd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070fe80
7306603500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=40bcacd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070fe80
7306603500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=40bcacd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070fe80 SF size: 0 lat: 1
7306603500: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=40bcacd38f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fd070fe80
7306603500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306603500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306603500: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306603500: DRAM: system.mem_ctrls: Read queue limit 32, current size 2, entries needed 1
7306603500: DRAM: system.mem_ctrls: Adding to read queue
7306603500: DRAM: system.mem_ctrls: Request scheduled immediately
7306603500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306603500
7306603500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306605000
7306603500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306603500 to 7306605000
7306603500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306607500
7306603500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306603500
7306603500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306603500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306603500: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306603500: DRAM: system.mem_ctrls: Removing burstTick for 7306595000
7306603500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306621000
7306603500: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306639750 next burst at 7306626000.
7306603500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306603500
7306603500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306603500
7306603500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306603500
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306604000
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306603500
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306604000
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306603500
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306604000
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306603500
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306604000
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306603500
7306603500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306604000
7306604000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306604000
7306604000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fd00
7306604000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[20] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fd00
7306604000: Event: system.tol2bus.slave[20]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1327 scheduled @ 7306604500
7306604000: Event: system.tol2bus.respLayer20.wrapped_function_event: EventFunctionWrapped 1328 scheduled @ 7306605500
7306604000: BaseXBar: system.tol2bus.respLayer20: The crossbar layer is now busy from tick 7306604000 to 7306605500
7306604000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306608000
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306604000
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306604500
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306604000
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306604500
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306604000
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306604500
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306604000
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306604500
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306604000
7306604000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306604500
7306604500: Event: system.tol2bus.slave[20]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1327 executed @ 7306604500
7306604500: Cache: system.cpu5.icache: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fd00
7306604500: Event: system.cpu5.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 291 scheduled @ 7306606500
7306604500: CacheVerbose: system.cpu5.icache: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fd070fd00
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306604500
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306605000
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306604500
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306605000
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306604500
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306605000
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306604500
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306605000
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306604500
7306604500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306605000
7306605000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306605000
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306605000
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306605500
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306605000
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306605500
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306605000
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306605500
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306605000
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306605500
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306605000
7306601500: ExecEnable: system.cpu4: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306605000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306605500
7306605500: Event: system.tol2bus.respLayer20.wrapped_function_event: EventFunctionWrapped 1328 executed @ 7306605500
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306605500
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306606000
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306605500
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306606000
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306605500
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306606000
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306605500
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306606000
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306605500
7306605500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306606000
7306605750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306605750
7306605750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802b80
7306605750: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802b80
7306605750: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306608000
7306605750: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306611000
7306605750: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306605750 to 7306611000
7306605750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306610750
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306606000
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306606500
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306606000
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306606500
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306606000
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306606500
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306606000
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306606500
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306606000
7306606000: Cache: system.cpu4.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fd00
7306606000: CachePort: system.cpu4.dcache.mem_side: Scheduling send event at 7306607000
7306606000: Event: system.cpu4.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 235 scheduled @ 7306607000
7306606000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306606500
7306606500: Event: system.cpu5.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 291 executed @ 7306606500
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306606500
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306607000
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306606500
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306607000
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306606500
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306607000
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306606500
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306607000
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306606500
7306606500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306607000
7306607000: Event: system.cpu4.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 235 executed @ 7306607000
7306607000: Cache: system.cpu4.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fd00
7306607000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[17] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fd00
7306607000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[17] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fd00
7306607000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[17] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fd00 SF size: 0 lat: 0
7306607000: CoherentXBar: system.tol2bus: forwardTiming for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fd00
7306607000: Cache: system.l2: access for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fd00
7306607000: CachePort: system.l2.mem_side: Scheduling send event at 7306617500
7306607000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306608000
7306607000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306607000 to 7306608000
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306607000
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306607500
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306607000
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306607500
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306607000
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306607500
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306607000
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306607500
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306607000
7306607000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306607500
7306607500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306607500
7306607500: Cache: system.l2: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306607500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306607500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306607500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00 SF size: 0 lat: 1
7306607500: CoherentXBar: system.membus: forwardTiming for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306607500: DRAM: system.mem_ctrls: recvTimingReq: request WriteReq addr 0x80a70800 size 4
7306607500: DRAM: system.mem_ctrls: Write queue limit 64, current size 26, entries needed 1
7306607500: DRAM: system.mem_ctrls: Merging write burst with existing queue entry
7306607500: DRAM: system.mem_ctrls: Responding to Address 0x80a70800
7306607500: DRAM: system.mem_ctrls: Done: WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fc9802a00
7306607500: DRAM: system.mem_ctrls: Request scheduled immediately
7306607500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306607500
7306607500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306610000
7306607500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306607500 to 7306610000
7306607500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306613500
7306607500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306607500
7306607500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306607500
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306608000
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306607500
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306608000
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306607500
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306608000
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306607500
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306608000
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306607500
7306607500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306608000
7306608000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306608000
7306608000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306608000
7306608000: Cache: system.l2: recvTimingResp: Handling response ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802b80
7306608000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802b80
7306608000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306608000
7306608000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet CleanInvalidResp [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800
7306608000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[1] packet CleanInvalidResp [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800
7306608000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse:   old SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
7306608000: SnoopFilter: system.tol2bus.snoop_filter: eraseIfNullEntry:   Removed SF entry.
7306608000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306608000: Event: system.tol2bus.slave[1]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1289 scheduled @ 7306608500
7306608000: Event: system.tol2bus.respLayer1.wrapped_function_event: EventFunctionWrapped 1290 scheduled @ 7306608500
7306608000: BaseXBar: system.tol2bus.respLayer1: The crossbar layer is now busy from tick 7306608000 to 7306608500
7306608000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306609000
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306608000
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306608500
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306608000
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306608500
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306608000
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306608500
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306608000
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306608500
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306608000
7306608000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306608500
7306608500: Event: system.tol2bus.respLayer1.wrapped_function_event: EventFunctionWrapped 1290 executed @ 7306608500
7306608500: Event: system.tol2bus.slave[1]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1289 executed @ 7306608500
7306608500: Cache: system.cpu0.dcache: recvTimingResp: Handling response CleanInvalidResp [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800
7306608500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306609500
7306608500: CacheVerbose: system.cpu0.dcache: recvTimingResp: Leaving with CleanInvalidResp [8000ffc0:8000ffff] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f800
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306608500
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306609000
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306608500
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306609000
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306608500
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306609000
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306608500
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306609000
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306608500
7306608500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306609000
7306609000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306609000
7306609000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802700
7306609000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[20] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802700
7306609000: Event: system.tol2bus.slave[20]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1327 scheduled @ 7306609500
7306609000: Event: system.tol2bus.respLayer20.wrapped_function_event: EventFunctionWrapped 1328 scheduled @ 7306610500
7306609000: BaseXBar: system.tol2bus.respLayer20: The crossbar layer is now busy from tick 7306609000 to 7306610500
7306609000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306610000
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306609000
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306609500
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306609000
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306609500
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306609000
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306609500
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306609000
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306609500
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306609000
7306609000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306609500
7306609500: Event: system.tol2bus.slave[20]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1327 executed @ 7306609500
7306609500: Cache: system.cpu5.icache: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802700
7306609500: Event: system.cpu5.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 291 scheduled @ 7306611500
7306609500: CacheVerbose: system.cpu5.icache: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802700
7306609500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306609500
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306609500
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306610000
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306609500
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306610000
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306609500
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306610000
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306609500
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306610000
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306609500
7306609500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306610000
7306610000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 executed @ 7306610000
7306610000: CoherentXBar: system.tol2bus: recvTimingResp: src system.tol2bus.master[0] packet WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306610000: SnoopFilter: system.tol2bus.snoop_filter: updateResponse: src system.tol2bus.slave[5] packet WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306610000: Event: system.tol2bus.slave[5]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1297 scheduled @ 7306610500
7306610000: Event: system.tol2bus.respLayer5.wrapped_function_event: EventFunctionWrapped 1298 scheduled @ 7306610500
7306610000: BaseXBar: system.tol2bus.respLayer5: The crossbar layer is now busy from tick 7306610000 to 7306610500
7306610000: Event: system.l2.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 420 scheduled @ 7306622000
7306610000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306610000
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306610000
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306610500
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306610000
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306610500
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306610000
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306610500
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306610000
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306610500
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306610000
7306610000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306610500
7306610500: Event: system.tol2bus.respLayer5.wrapped_function_event: EventFunctionWrapped 1298 executed @ 7306610500
7306610500: Event: system.tol2bus.slave[5]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 1297 executed @ 7306610500
7306610500: Cache: system.cpu1.dcache: recvTimingResp: Handling response WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070f480
7306610500: Event: system.cpu1.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 98 scheduled @ 7306611500
7306610500: Event: system.tol2bus.respLayer20.wrapped_function_event: EventFunctionWrapped 1328 executed @ 7306610500
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306610500
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306611000
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306610500
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306611000
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306610500
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306611000
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306610500
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306611000
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306610500
7306610500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306611000
7306610750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306610750
7306610750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802800 BUSY
7306611000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306611000
7306611000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802800
7306611000: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802800
7306611000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306613000
7306611000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306616000
7306611000: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306611000 to 7306616000
7306611000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306616750
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306611000
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306611500
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306611000
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306611500
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306611000
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306611500
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306611000
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306611500
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306611000
7306611000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306611500
7306611500: Event: system.cpu1.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 98 executed @ 7306611500
7306611500: Event: system.cpu5.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 291 executed @ 7306611500
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306611500
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306611500
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306612000
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306611500
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306612000
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306611500
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306612000
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306611500
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306612000
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306611500
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306612000
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306611500
7306611500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306612000
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306612000
7306519500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+48    :   dsb                      : IntAlu :   FetchSeq=13255200  CPSeq=11776692  flags=(IsSerializeAfter|IsMemBarrier)
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306612500
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306612000
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306612500
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306612000
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306612500
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306612000
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306612500
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306612000
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306612500
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306612000
7306612000: Cache: system.cpu5.icache: access for ReadReq [807371c0:807371ff] IF UC D=c03cd4d18f5500006374696f6e577261707065642031323835206578656375746564204020373330363630383030300a000035386664303730666430300018d5 ptr=0x558fc9802000
7306612000: CachePort: system.cpu5.icache.mem_side: Scheduling send event at 7306613000
7306612000: Event: system.cpu5.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 293 scheduled @ 7306613000
7306612000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306612500
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306612500
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306613000
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306612500
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306613000
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306612500
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306613000
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306612500
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306613000
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306612500
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306613000
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306612500
7306612500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306613000
7306613000: Event: system.cpu5.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 293 executed @ 7306613000
7306613000: Cache: system.cpu5.icache: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=c03cd4d18f5500006374696f6e577261707065642031323835206578656375746564204020373330363630383030300a000035386664303730666430300018d5 ptr=0x558fc9802000
7306613000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[20] packet ReadReq [807371c0:807371ff] IF UC D=0051d2d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363631333030300a00000000000000000000000000000000 ptr=0x558fd070f480
7306613000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[20] packet ReadReq [807371c0:807371ff] IF UC D=0051d2d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363631333030300a00000000000000000000000000000000 ptr=0x558fd070f480
7306613000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[20] packet ReadReq [807371c0:807371ff] IF UC D=0051d2d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363631333030300a00000000000000000000000000000000 ptr=0x558fd070f480 SF size: 0 lat: 0
7306613000: CoherentXBar: system.tol2bus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=0051d2d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363631333030300a00000000000000000000000000000000 ptr=0x558fd070f480
7306613000: Cache: system.l2: access for ReadReq [807371c0:807371ff] IF UC D=0051d2d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363631333030300a00000000000000000000000000000000 ptr=0x558fd070f480
7306613000: CachePort: system.l2.mem_side: Scheduling send event at 7306623500
7306613000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306613500
7306613000: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306613000 to 7306613500
7306613000: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 executed @ 7306613000
7306613000: Cache: system.l2: recvTimingResp: Handling response ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802800
7306613000: CacheVerbose: system.l2: recvTimingResp: Leaving with ReadResp [80737180:807371bf] IF UC D=210020911f4838714100005421100091200000b9bf3f03d5217608d5c0035fd69affff97f6ffff97a00038d5e11fc0d2e11fa0f2e1ff9ff20000018ac31900d0 ptr=0x558fc9802800
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306613000
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306613500
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306613000
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306613500
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306613000
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306613500
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306613000
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306613500
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306613000
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306613500
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306613000
7306613000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306613500
7306613500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306613500
7306613500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 executed @ 7306613500
7306613500: Cache: system.l2: sendMSHRQueuePacket: MSHR ReadReq [807371c0:807371ff] IF UC D=0037d4d18f5500006374696f6e5772617070656420313339207363686564756c6564204020373330363630333030300a0000b2c98f550000e0039fd6c11900b0 ptr=0x558fc8fb7d00
7306613500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=4097d6d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802800
7306613500: SnoopFilter: system.membus.snoop_filter: lookupRequest: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=4097d6d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802800
7306613500: CoherentXBar: system.membus: recvTimingReq: src system.membus.slave[3] packet ReadReq [807371c0:807371ff] IF UC D=4097d6d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802800 SF size: 0 lat: 1
7306613500: CoherentXBar: system.membus: forwardTiming for ReadReq [807371c0:807371ff] IF UC D=4097d6d18f550000f0d8e9cd8f55000060d9e9cd8f550000d0d9e9cd8f55000040dae9cd8f550000b0dae9cd8f55000020dbe9cd8f55000090dbe9cd8f550000 ptr=0x558fc9802800
7306613500: DRAM: system.mem_ctrls: recvTimingReq: request ReadReq addr 0x807371c0 size 64
7306613500: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306613500: DRAM: system.mem_ctrls: Address: 0x7371c0 Rank 1 Bank 3 Row 57
7306613500: DRAM: system.mem_ctrls: Read queue limit 32, current size 3, entries needed 1
7306613500: DRAM: system.mem_ctrls: Adding to read queue
7306613500: DRAM: system.mem_ctrls: Request scheduled immediately
7306613500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306613500
7306613500: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 scheduled @ 7306615000
7306613500: BaseXBar: system.membus.reqLayer13: The crossbar layer is now busy from tick 7306613500 to 7306615000
7306613500: Event: system.l2.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 422 scheduled @ 7306617500
7306613500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306613500
7306613500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306613500: DRAM: system.mem_ctrls: Single request, going to a free rank
7306613500: DRAM: system.mem_ctrls: Timing access to addr 0x7371c0, rank/bank/row 1 3 57
7306613500: DRAM: system.mem_ctrls: Removing burstTick for 7306610000
7306613500: DRAM: system.mem_ctrls: Schedule RD/WR burst at tick 7306626000
7306613500: DRAM: system.mem_ctrls: Access to 0x7371c0, ready at 7306644750 next burst at 7306631000.
7306613500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 7306613500
7306613500: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 7306613500
7306613500: DRAM: system.mem_ctrls: QoS Turnarounds selected state READ
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306613500
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306614000
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306613500
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306614000
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306613500
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306614000
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306613500
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306614000
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306613500
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306614000
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306613500
7306613500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306614000
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306614000
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306614500
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306614000
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375188    :   dmb                      : IntAlu :   FetchSeq=184  CPSeq=39  flags=(IsMemBarrier)
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306614500
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306614000
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306614500
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306614000
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306614500
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306614000
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306614500
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306614000
7306614000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306614500
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306614500
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306615000
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306614500
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306615000
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306614500
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306615000
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306614500
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306615000
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306614500
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375192    :   dc ivac   , x1           : MemWrite :  A=0x80a70800  FetchSeq=185  CPSeq=40  flags=(IsInteger|IsMemRef|IsStore)
7306557500: ExecEnable: system.cpu1: A0 T0 : @_kernel_size_le_lo32+2144375196    :   ret                      : IntAlu :   FetchSeq=186  CPSeq=41  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306615000
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306614500
7306614500: Cache: system.cpu0.icache: access for ReadReq [80337900:8033793f] IF D=c097d6d18f550000400b80c98f5500005141ca0000000000e07974d08f5500000000000000000000901ab2c98f5500009833b2c98f5500000000000000000000 ptr=0x558fd070f580 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x200cd set: 0xe4 way: 0
7306614500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306615500
7306614500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306615000
7306615000: Event: system.membus.reqLayer13.wrapped_function_event: EventFunctionWrapped 451 executed @ 7306615000
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306615000
7306519500: ExecEnable: system.cpu0: A0 T0 : @__flush_dcache_area+52    :   ret                      : IntAlu :   FetchSeq=13255201  CPSeq=11776693  flags=(IsInteger|IsControl|IsIndirectControl|IsUncondControl|IsReturn)
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306615500
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306615000
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306615500
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306615000
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306615500
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306615000
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306615500
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306615000
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306615500
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306615000
7306611500: ExecEnable: system.cpu5: A0 T0 : @_kernel_size_le_lo32+2144375184    :   str   x0, [x1]           : MemWrite :  D=0x0000000000000e11 A=0x80a70800  FetchSeq=183  CPSeq=38  flags=(IsInteger|IsMemRef|IsStore)
7306615000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306615500
7306615500: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 executed @ 7306615500
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306615500
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306616000
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306615500
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306616000
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306615500
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306616000
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306615500
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306616000
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306615500
7306615500: Cache: system.cpu1.dcache: access for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f580 miss
7306615500: CachePort: system.cpu1.dcache.mem_side: Scheduling send event at 7306616500
7306615500: Event: system.cpu1.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 100 scheduled @ 7306616500
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306616000
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306615500
7306615500: Cache: system.cpu0.dcache: access for ReadReq [8d847df0:8d847df7] D=482e6acf8f550000 ptr=0x558fc9802700 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306615500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306616500
7306615500: Cache: system.cpu0.dcache: access for ReadReq [8d847de0:8d847def] D=30c116d28f5500002024ebc88f550000 ptr=0x558fd070f800 hit state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 | tag: 0x11b08 set: 0x1f7 way: 0x1
7306615500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306616000
7306616000: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 executed @ 7306616000
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306616000
7306616000: Cache: system.cpu0.icache: access for ReadReq [80337940:8033797f] IF D=c04fd2d18f550000602febc88f550000733eca0000000000000000000100ffff000000008f550000a0adeac88f55000050beeac88f55000090adb9cd8f550000 ptr=0x558fc9802b80 hit state: 5 (S) valid: 1 writable: 0 readable: 1 dirty: 0 | tag: 0x200cd set: 0xe5 way: 0x1
7306616000: Event: system.cpu0.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 7306617000
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306616500
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306616000
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306616500
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306616000
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306616500
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306616000
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306616500
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306616000
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306616500
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306616000
7306616000: Cache: system.cpu5.dcache: access for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fe00
7306616000: CachePort: system.cpu5.dcache.mem_side: Scheduling send event at 7306617000
7306616000: Event: system.cpu5.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 280 scheduled @ 7306617000
7306616000: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306616500
7306616500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306616500
7306616500: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 scheduled @ 7306616501
7306616500: Event: system.cpu1.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 100 executed @ 7306616500
7306616500: Cache: system.cpu1.dcache: sendMSHRQueuePacket: MSHR InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070f580
7306616500: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[5] packet InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fd80
7306616500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[5] packet InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fd80
7306616500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306616500: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest:   new SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306616500: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[5] packet InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fd80 SF size: 0 lat: 0
7306616500: CoherentXBar: system.tol2bus: forwardTiming for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fd80
7306616500: Cache: system.l2: access for InvalidateReq [80a70800:80a7083f] PoC D=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ptr=0x558fd070fd80 miss
7306616500: CachePort: system.l2.mem_side: Scheduling send event at 7306627000
7306616500: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 scheduled @ 7306617000
7306616500: BaseXBar: system.tol2bus.reqLayer0: The crossbar layer is now busy from tick 7306616500 to 7306617000
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 executed @ 7306616500
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 274 scheduled @ 7306617000
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 executed @ 7306616500
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 229 scheduled @ 7306617000
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 executed @ 7306616500
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 184 scheduled @ 7306617000
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 executed @ 7306616500
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 139 scheduled @ 7306617000
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 executed @ 7306616500
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 94 scheduled @ 7306617000
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 executed @ 7306616500
7306616500: Event: FullO3CPU tick.wrapped_function_event: EventFunctionWrapped 49 scheduled @ 7306617000
7306616501: Event: system.cpu0.dcache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped 53 executed @ 7306616501
7306616750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306616750
7306616750: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802400
7306616750: SnoopFilter: system.membus.snoop_filter: updateResponse: src system.membus.slave[3] packet ReadResp [807371c0:807371ff] IF UC D=63000091640040f99f0000ebc00000545f2003d5fcffff178cffff97e8ffff9701000014c7000094100000946806005800011fd645caffd0a500209105c018d5 ptr=0x558fc9802400
7306616750: Event: system.membus.slave[3]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 461 scheduled @ 7306619000
7306616750: Event: system.membus.respLayer3.wrapped_function_event: EventFunctionWrapped 462 scheduled @ 7306622000
7306616750: BaseXBar: system.membus.respLayer3: The crossbar layer is now busy from tick 7306616750 to 7306622000
7306616750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 7306617000
7306617000: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 9 executed @ 7306617000
7306617000: CoherentXBar: system.membus: recvTimingResp: src system.membus.master[13] packet WriteResp [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fc80 BUSY
7306617000: Event: system.tol2bus.reqLayer0.wrapped_function_event: EventFunctionWrapped 1285 executed @ 7306617000
7306617000: Event: system.cpu5.dcache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped 280 executed @ 7306617000
7306617000: Cache: system.cpu5.dcache: sendWriteQueuePacket: write WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fe00
7306617000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[21] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fe00
7306617000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest: src system.tol2bus.slave[21] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fe00
7306617000: SnoopFilter: system.tol2bus.snoop_filter: lookupRequest:   SF value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
7306617000: CoherentXBar: system.tol2bus: recvTimingReq: src system.tol2bus.slave[21] packet WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fe00 SF size: 1 lat: 0
7306617000: CoherentXBar: system.tol2bus: forwardTiming for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fe00
7306617000: CacheVerbose: system.cpu1.dcache: recvTimingSnoopReq: for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fe00
7306617000: Cache: global: handleSnoop for WriteReq [80a70800:80a70803] UC D=110e0000 ptr=0x558fd070fe00