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classilla/no-reg-6502-bf.pl

Last active January 4, 2023 02:07
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Minimal Brainf*ck compiler that turns BF into 6502 assembly but is Turing complete without A, X or Y. http://oldvcr.blogspot.com/2023/01/the-mos-6502-is-mostly-turing-complete.html
Raw
no-reg-6502-bf.pl
#!/usr/bin/perl -s
#
# Takes BF, emits 6502 that only clobbers PC, S, and the N and V flags
# Requires an assembler (I recommend xa65)
#
# Cameron Kaiser
# Public domain
# http://oldvcr.blogspot.com/2023/01/the-mos-6502-is-mostly-turing-complete.html
#
$sa ||= 49152;
$tl ||= "label";
$sl ||= 0;
print STDOUT <<"EOF";
; generated by no-reg-6502-bf.pl
; http://oldvcr.blogspot.com/2023/01/the-mos-6502-is-mostly-turing-complete.html
; this generator assumes a Commodore 64
; starting address in file
; your assembler may use another syntax to indicate a 16-bit word
.word $sa
; starting address in memory
; your assembler may require .org or another syntax
* = $sa
; prologue
dec plus+1
bne *-3
dec minus+1
bne *-3
dec plus+2
bne *-3
dec minus+2
bne *-3
inc plus+2
inc plus+2
inc plus+2
inc plus+2
inc minus+2
inc minus+2
inc minus+2
inc minus+2
EOF
$lsl = $sl;
$ssl = $sl;
$/ = \1; while(<>) {
if ($_ eq '+') {
print "\tjsr plus\n";
} elsif ($_ eq '-') {
print "\tjsr minus\n";
} elsif ($_ eq '[') {
$lsl++ if ($sl == $ssl);
print <<"EOF";
jsr plus
jsr minus
bne *+5
jmp end${tl}${lsl}${sl}
top${tl}${lsl}${sl}:
EOF
$sl++;
} elsif ($_ eq ']') {
$sl--;
print <<"EOF";
jsr plus
jsr minus
bne *+5
jmp end${tl}${lsl}${sl}
jmp top${tl}${lsl}${sl}
end${tl}${lsl}${sl}:
EOF
} elsif ($_ eq '>') {
print <<"EOF";
inc plus+1
bne *+5
inc plus+2
inc minus+1
bne *+5
inc minus+2
EOF
} elsif ($_ eq '<') {
print <<"EOF";
inc plus+1
dec plus+1
bne *+5
dec plus+2
dec plus+1
inc minus+1
dec minus+1
bne *+5
dec minus+2
dec minus+1
EOF
}
}
die("unbalanced [ ]\n") if ($sl != $ssl);
print STDOUT <<'EOF';
; epilogue
rts
plus inc $0400
rts
minus dec $0400
rts
EOF
Raw
test.bf
[-]>[-]>[-]>[-]>[-]>[-]
<<<<<
++++++++>
+++++>
++++++++++++>
++++++++++++>
+++++++++++++++>
++++++++++++++++++++++++++++++++
Raw
test.s
; generated by no-reg-6502-bf.pl
; http://oldvcr.blogspot.com/2023/01/the-mos-6502-is-mostly-turing-complete.html
; this generator assumes a Commodore 64
; starting address in file
; your assembler may use another syntax to indicate a 16-bit word
.word 49152
; starting address in memory
; your assembler may require .org or another syntax
* = 49152
; prologue
dec plus+1
bne *-3
dec minus+1
bne *-3
dec plus+2
bne *-3
dec minus+2
bne *-3
inc plus+2
inc plus+2
inc plus+2
inc plus+2
inc minus+2
inc minus+2
inc minus+2
inc minus+2
jsr plus
jsr minus
bne *+5
jmp endlabel10
toplabel10:
jsr minus
jsr plus
jsr minus
bne *+5
jmp endlabel10
jmp toplabel10
endlabel10:
inc plus+1
bne *+5
inc plus+2
inc minus+1
bne *+5
inc minus+2
jsr plus
jsr minus
bne *+5
jmp endlabel20
toplabel20:
jsr minus
jsr plus
jsr minus
bne *+5
jmp endlabel20
jmp toplabel20
endlabel20:
inc plus+1
bne *+5
inc plus+2
inc minus+1
bne *+5
inc minus+2
jsr plus
jsr minus
bne *+5
jmp endlabel30
toplabel30:
jsr minus
jsr plus
jsr minus
bne *+5
jmp endlabel30
jmp toplabel30
endlabel30:
inc plus+1
bne *+5
inc plus+2
inc minus+1
bne *+5
inc minus+2
jsr plus
jsr minus
bne *+5
jmp endlabel40
toplabel40:
jsr minus
jsr plus
jsr minus
bne *+5
jmp endlabel40
jmp toplabel40
endlabel40:
inc plus+1
bne *+5
inc plus+2
inc minus+1
bne *+5
inc minus+2
jsr plus
jsr minus
bne *+5
jmp endlabel50
toplabel50:
jsr minus
jsr plus
jsr minus
bne *+5
jmp endlabel50
jmp toplabel50
endlabel50:
inc plus+1
bne *+5
inc plus+2
inc minus+1
bne *+5
inc minus+2
jsr plus
jsr minus
bne *+5
jmp endlabel60
toplabel60:
jsr minus
jsr plus
jsr minus
bne *+5
jmp endlabel60
jmp toplabel60
endlabel60:
inc plus+1
dec plus+1
bne *+5
dec plus+2
dec plus+1
inc minus+1
dec minus+1
bne *+5
dec minus+2
dec minus+1
inc plus+1
dec plus+1
bne *+5
dec plus+2
dec plus+1
inc minus+1
dec minus+1
bne *+5
dec minus+2
dec minus+1
inc plus+1
dec plus+1
bne *+5
dec plus+2
dec plus+1
inc minus+1
dec minus+1
bne *+5
dec minus+2
dec minus+1
inc plus+1
dec plus+1
bne *+5
dec plus+2
dec plus+1
inc minus+1
dec minus+1
bne *+5
dec minus+2
dec minus+1
inc plus+1
dec plus+1
bne *+5
dec plus+2
dec plus+1
inc minus+1
dec minus+1
bne *+5
dec minus+2
dec minus+1
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
inc plus+1
bne *+5
inc plus+2
inc minus+1
bne *+5
inc minus+2
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
inc plus+1
bne *+5
inc plus+2
inc minus+1
bne *+5
inc minus+2
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
inc plus+1
bne *+5
inc plus+2
inc minus+1
bne *+5
inc minus+2
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
inc plus+1
bne *+5
inc plus+2
inc minus+1
bne *+5
inc minus+2
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
inc plus+1
bne *+5
inc plus+2
inc minus+1
bne *+5
inc minus+2
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
jsr plus
; epilogue
rts
plus inc $0400
rts
minus dec $0400
rts
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