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root/ # cpuinfo | |
Basic CPU information: | |
Architecture: ARM | |
Vendor: ARM | |
Microarchitecture: Cortex-A9 | |
CPU ISA extensions: | |
ARMv4 instruction set: Yes | |
ARMv5 instruction set: Yes | |
ARMv5 DSP instructions: Yes | |
ARMv6 instruction set: Yes | |
ARMv6 Multiprocessing extensions: Yes | |
ARMv7 instruction set: Yes | |
ARMv7 Multiprocessing extensions: Yes | |
Thumb mode: Yes | |
Thumb-2 mode: Yes | |
Thumb EE mode: Yes | |
Jazelle extension: No | |
FPA instruction set: No | |
VFP instruction set: Yes | |
VFPv2 instruction set: Yes | |
VFPv3 instruction set: Yes | |
VFP with 32 DP registers: Yes | |
VFPv3 half-precision extension: Yes | |
VFPv4 instruction set: No | |
SDIV and UDIV instructions: No | |
Marvell Armada instruction extensions: No | |
CPU SIMD extensions: | |
XScale instructions: No | |
Wireless MMX instruction set: No | |
Wireless MMX 2 instruction set: No | |
NEON (Advanced SIMD) instruction set: Yes | |
NEON (Advanced SIMD) half-precision extension: Yes | |
NEON (Advanced SIMD) v2 instruction set: No | |
Non-ISA CPU and system features: | |
CPU cycle counter: Yes | |
64-bit CPU cycle counter: Yes | |
64-bit address space: No | |
64-bit general-purpose registers: No | |
Misaligned memory access: Yes | |
Single hardware thread: No | |
Hardware VFP vector mode: No | |
FPA registers: No | |
WMMX registers: No | |
32 VFP S registers: Yes | |
32 VFP D registers: Yes | |
root/ # cpuinfoex | |
Processor: ARM Cortex-A9 based | |
Logical cores: 2 | |
L1I: 32768 | |
L1D: 32768 | |
L2: 1048576 | |
L3: 0 |
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