qca,qca8k.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/qca,qca8k.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Atheros QCA83xx switch family

allOf:
  - $ref: dsa.yaml#

maintainers:
  - John Crispin <john@phrozen.org>

description:
  If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
  describing a port needs to have a valid phandle referencing the internal PHY
  it is connected to. This is because there is no N:N mapping of port and PHY
  ID. To declare the internal mdio-bus configuration, declare an MDIO node in
  the switch node and declare the phandle for the port, referencing the internal
  PHY it is connected to. In this config, an internal mdio-bus is registered and
  the MDIO master is used for communication. Mixed external and internal
  mdio-bus configurations are not supported by the hardware.

properties:
  compatible:
    oneOf:
      - enum:
          - qca,qca8327
          - qca,qca8328
          - qca,qca8334
          - qca,qca8337

  reg:
    maxItems: 1

  reset-gpios:
    description:
      GPIO to be used to reset the whole device
    maxItems: 1

  qca,sgmii-rxclk-falling-edge:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Set the receive clock phase to falling edge. Mostly commonly used on
      the QCA8327 with CPU port 0 set to SGMII.

  qca,sgmii-txclk-falling-edge:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Set the transmit clock phase to falling edge.

  qca,sgmii-enable-pll:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      For SGMII CPU port, explicitly enable PLL, TX and RX chain along with
      Signal Detection. On the QCA8327 this should not be enabled, otherwise
      the SGMII port will not initialize. When used on the QCA8337, revision 3
      or greater, a warning will be displayed. When the CPU port is set to
      SGMII on the QCA8337, it is advised to set this unless a communication
      issue is observed.

  qca,ignore-power-on-sel:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Ignore power-on pin strapping to configure LED open-drain or EEPROM
      presence. This is needed for devices with incorrect configuration or when
      the OEM has decided not to use pin strapping and falls back to SW regs.

  qca,led-open-drain:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to
      be set, otherwise the driver will fail at probe. This is required if the
      OEM does not use pin strapping to set this mode and prefers to set it
      using SW regs. The pin strappings related to LED open-drain mode are
      B68 on the QCA832x and B49 on the QCA833x.

  mdios:
    type: object

    properties:
      '#address-cells':
        const: 1
      '#size-cells':
        const: 0

    patternProperties:
      "^mdio@[0-1]$":
        type: object

        allOf:
          - $ref: "http://devicetree.org/schemas/net/mdio.yaml#"

        properties:
          '#address-cells':
            const: 1
          '#size-cells':
            const: 0

        patternProperties:
          "^(ethernet-)?switch(@.*)?$"
#            type: object
#
#            allOf:
#              -
#        pattern: "^(ethernet-)?switch(@.*)?$"


required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    &mdio0 {
        phy_port1: phy@0 {
            reg = <0>;
        };

        phy_port2: phy@1 {
            reg = <1>;
        };

        phy_port3: phy@2 {
            reg = <2>;
        };

        phy_port4: phy@3 {
            reg = <3>;
        };

        phy_port5: phy@4 {
            reg = <4>;
        };

        switch@10 {
            compatible = "qca,qca8337";
            #address-cells = <1>;
            #size-cells = <0>;

            reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
            reg = <0x10>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;
                port@0 {
                    reg = <0>;
                    label = "cpu";
                    ethernet = <&gmac1>;
                    phy-mode = "rgmii";
                    fixed-link {
                        speed = 1000;
                        full-duplex;
                    };
                };

                port@1 {
                    reg = <1>;
                    label = "lan1";
                    phy-handle = <&phy_port1>;
                };

                port@2 {
                    reg = <2>;
                    label = "lan2";
                    phy-handle = <&phy_port2>;
                };

                port@3 {
                    reg = <3>;
                    label = "lan3";
                    phy-handle = <&phy_port3>;
                };

                port@4 {
                    reg = <4>;
                    label = "lan4";
                    phy-handle = <&phy_port4>;
                };

                port@5 {
                    reg = <5>;
                    label = "wan";
                    phy-handle = <&phy_port5>;
                };
            };
        };
    };
  - |
    &mdio0 {
        switch@10 {
            compatible = "qca,qca8337";
            #address-cells = <1>;
            #size-cells = <0>;

            reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
            reg = <0x10>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    label = "cpu";
                    ethernet = <&gmac1>;
                    phy-mode = "rgmii";
                    fixed-link {
                        speed = 1000;
                        full-duplex;
                    };
                };

                port@1 {
                    reg = <1>;
                    label = "lan1";
                    phy-mode = "internal";
                    phy-handle = <&phy_port1>;
                };

                port@2 {
                    reg = <2>;
                    label = "lan2";
                    phy-mode = "internal";
                    phy-handle = <&phy_port2>;
                };

                port@3 {
                    reg = <3>;
                    label = "lan3";
                    phy-mode = "internal";
                    phy-handle = <&phy_port3>;
                };

                port@4 {
                    reg = <4>;
                    label = "lan4";
                    phy-mode = "internal";
                    phy-handle = <&phy_port4>;
                };

                port@5 {
                    reg = <5>;
                    label = "wan";
                    phy-mode = "internal";
                    phy-handle = <&phy_port5>;
                };
            };

            mdio {
                #address-cells = <1>;
                #size-cells = <0>;

                phy_port1: phy@0 {
                    reg = <0>;
                };

                phy_port2: phy@1 {
                    reg = <1>;
                };

                phy_port3: phy@2 {
                    reg = <2>;
                };

                phy_port4: phy@3 {
                    reg = <3>;
                };

                phy_port5: phy@4 {
                    reg = <4>;
                };
            };
        };
    };