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@cleverca22
Created April 26, 2024 04:05
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/dts-v1/;
/ {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "riscv-minimal-nommu";
model = "riscv-minimal-nommu,qemu";
interrupt-parent = <&intc>;
chosen {
bootargs = "earlycon=uart8250,mmio,0x10000000,1000000 console=ttyS0";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x3ffc000>;
};
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
timebase-frequency = <0xf4240>;
cpu@0 {
phandle = <0x01>;
device_type = "cpu";
reg = <0x00>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv32ima";
mmu-type = "riscv,none";
intc: interrupt-controller {
#interrupt-cells = <0x01>;
interrupt-controller;
compatible = "riscv,cpu-intc";
phandle = <0x02>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <0x01>;
};
};
};
};
soc {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "simple-bus";
ranges;
uart@10000000 {
clock-frequency = <0x1000000>;
reg = <0x10000000 0x100>;
compatible = "ns16850";
};
poweroff {
value = <0x5555>;
offset = <0x00>;
regmap = <0x04>;
compatible = "syscon-poweroff";
};
reboot {
value = <0x7777>;
offset = <0x00>;
regmap = <0x04>;
compatible = "syscon-reboot";
};
syscon@11100000 {
phandle = <0x04>;
reg = <0x11100000 0x1000>;
compatible = "syscon";
};
clint@11000000 {
interrupts = <0x03 0x07>;
reg = <0x11000000 0x10000>;
compatible = "sifive,clint0", "riscv,clint0";
};
virtio_input {
compatible = "virtio,mmio";
status = "disabled";
interrupts = <8>;
};
};
};
static const uint32_t virtio_base = 0x10010000;
if (true) {
int soc = fdt_path_offset(v_fdt, "/soc");
int virtio = fdt_path_offset(v_fdt, "/soc/virtio_input");
fdt_appendprop_addrrange(v_fdt, soc, virtio, "reg", virtio_base, 0x100);
fdt_setprop_string(v_fdt, virtio, "status", "okay");
}
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