rcc_struct.c

const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
	[RCC_CLOCK_CONFIG_LSI_32KHZ] = {
		/* 32khz from lsi, scale2, 0ws */
		.sysclock_source = RCC_LSI,
		.hpre = RCC_CFGR_HPRE_NODIV,
		.ppre = RCC_CFGR_PPRE_NODIV,
		.flash_waitstates = FLASH_ACR_LATENCY_0WS,
		.voltage_scale = PWR_SCALE2,
		.ahb_frequency = 32000,
		.apb_frequency = 32000,
	},
	[RCC_CLOCK_CONFIG_HSI_4MHZ] = {
		/* 4mhz from hsi/4, scale2, 0ws */
		.sysclock_source = RCC_HSI,
		.hsisys_div = RCC_CR_HSIDIV_DIV4,
		.hpre = RCC_CFGR_HPRE_NODIV,
		.ppre = RCC_CFGR_PPRE_NODIV,
		.flash_waitstates = FLASH_ACR_LATENCY_0WS,
		.voltage_scale = PWR_SCALE2,
		.ahb_frequency = 4000000,
		.apb_frequency = 4000000,
	},
	[RCC_CLOCK_CONFIG_HSI_16MHZ] = {
		/* 16mhz from hsi, scale2, 0ws */
		.sysclock_source = RCC_HSI,
		.hsisys_div = RCC_CR_HSIDIV_DIV1,
		.hpre = RCC_CFGR_HPRE_NODIV,
		.ppre = RCC_CFGR_PPRE_NODIV,
		.flash_waitstates = FLASH_ACR_LATENCY_0WS,
		.voltage_scale = PWR_SCALE2,
		.ahb_frequency = 16000000,
		.apb_frequency = 16000000,
	},
	[RCC_CLOCK_CONFIG_HSI_PLL_32MHZ] = {
		/* 32mhz from hsi via pll @ 128mhz / 4, scale1, 1ws */
		.sysclock_source = RCC_PLL,
		.pll_source = RCC_PLLCFGR_PLLSRC_HSI16,
		.pll_div = RCC_PLLCFGR_PLLM_DIV(1),
		.pll_mul = RCC_PLLCFGR_PLLN_MUL(8),
		.pllp_div = RCC_PLLCFGR_PLLP_DIV(4),
		.pllq_div = RCC_PLLCFGR_PLLQ_DIV(4),
		.pllr_div = RCC_PLLCFGR_PLLR_DIV(4),
		.hpre = RCC_CFGR_HPRE_NODIV,
		.ppre = RCC_CFGR_PPRE_NODIV,
		.flash_waitstates = FLASH_ACR_LATENCY_1WS,
		.voltage_scale = PWR_SCALE1,
		.ahb_frequency = 32000000,
		.apb_frequency = 32000000,
	},
	[RCC_CLOCK_CONFIG_HSI_PLL_64MHZ] = {
		/* 64mhz from hsi via pll @ 128mhz / 2, scale1, 2ws */
		.sysclock_source = RCC_PLL,
		.pll_source = RCC_PLLCFGR_PLLSRC_HSI16,
		.pll_div = RCC_PLLCFGR_PLLM_DIV(1),
		.pll_mul = RCC_PLLCFGR_PLLN_MUL(8),
		.pllp_div = RCC_PLLCFGR_PLLP_DIV(2),
		.pllq_div = RCC_PLLCFGR_PLLQ_DIV(2),
		.pllr_div = RCC_PLLCFGR_PLLR_DIV(2),
		.hpre = RCC_CFGR_HPRE_NODIV,
		.ppre = RCC_CFGR_PPRE_NODIV,
		.flash_waitstates = FLASH_ACR_LATENCY_2WS,
		.voltage_scale = PWR_SCALE1,
		.ahb_frequency = 64000000,
		.apb_frequency = 64000000,
	},
	[RCC_CLOCK_CONFIG_HSE_12MHZ_PLL_64MHZ] = {
		/* 64mhz from hse@12mhz via pll @ 128mhz / 2, scale1, 2ws */
		.sysclock_source = RCC_PLL,
		.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
		.pll_div = RCC_PLLCFGR_PLLM_DIV(3),
		.pll_mul = RCC_PLLCFGR_PLLN_MUL(32),
		.pllp_div = RCC_PLLCFGR_PLLP_DIV(2),
		.pllq_div = RCC_PLLCFGR_PLLQ_DIV(2),
		.pllr_div = RCC_PLLCFGR_PLLR_DIV(2),
		.hpre = RCC_CFGR_HPRE_NODIV,
		.ppre = RCC_CFGR_PPRE_NODIV,
		.flash_waitstates = FLASH_ACR_LATENCY_2WS,
		.voltage_scale = PWR_SCALE1,
		.ahb_frequency = 64000000,
		.apb_frequency = 64000000,
	},
};