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Simulation of RAM0 using Verilog
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all: ram0 | |
./ram0 | |
clean: | |
-rm -f ram0 | |
.SUFFIXES: .v | |
.v: | |
iverilog -Wall -DSIM -o $@ $< |
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`define OPZ 4'b1111 | |
`define OPA 4'b0001 | |
`define OPL 4'b0010 | |
`define OPN 4'b0100 | |
`define OPS 4'b1000 | |
`define BIT 15 | |
`define SIZE (2 ** `BIT) | |
module ram0 (clk, op, led); | |
input clk; | |
input [3:0] op; | |
output [7:0] led; | |
reg [`BIT - 1:0] ram [0:`SIZE - 1]; | |
reg [`BIT - 1:0] n, z; | |
assign led = z[7:0]; | |
always @(posedge clk) begin | |
case (op) | |
`OPZ: z = 0; | |
`OPA: z = z + 1; | |
`OPL: z = ram[z]; | |
`OPN: n = z; | |
`OPS: ram[n] = z; | |
endcase | |
end | |
endmodule | |
`ifdef SIM | |
module sim; | |
reg clk = 0; | |
reg [3:0] op; | |
wire [7:0] led; | |
ram0 core(clk, op, led); | |
integer ch; | |
always begin | |
ch = $fgetc(32'h8000_0000); | |
case (ch) | |
"z", "Z": op = `OPZ; | |
"a", "A": op = `OPA; | |
"l", "L": op = `OPL; | |
"n", "N": op = `OPN; | |
"s", "S": op = `OPS; | |
-1: $finish; | |
default: op = 0; | |
endcase | |
if (op) begin | |
#1 clk = ~clk; | |
#1 clk = ~clk; | |
$displayb(led); | |
end | |
end | |
endmodule | |
`endif |
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