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Brain-like logic using Verilog
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module brain (clk, sensor, effect); | |
parameter nbit = 12; | |
parameter size = 2 ** nbit; | |
input clk; | |
input [7:0] sensor; | |
output [7:0] effect; | |
reg sig [0:size - 1]; | |
reg trace [0:size - 1]; | |
reg [nbit - 1:0] ram [0:size - 1]; | |
assign effect[3:0] = {sig[3], sig[2], sig[1], sig[0]}; | |
assign effect[7:4] = {sig[7], sig[6], sig[5], sig[4]}; | |
integer i; | |
initial for (i = 0; i < size; i = i + 1) begin | |
trace[i] = 0; | |
sig[i] = 0; | |
ram[i] = i; | |
end | |
always @(posedge clk) begin | |
for (i = 0; i < 8; i = i + 1) | |
sig[ram[i]] <= sensor[i]; | |
for (i = 0; i < size; i = i + 1) begin | |
case ({trace[i], sig[ram[i]]}) | |
2'b00: ram[i] <= ram[i] + 1; | |
2'b01: sig[i] <= 1; | |
2'b10: sig[i] <= 0; | |
2'b11: ram[i] <= ram[i] - 1; | |
endcase | |
trace[i] <= sig[ram[i]]; | |
end | |
end | |
endmodule | |
`ifdef SIM | |
module sim; | |
reg clk = 0; | |
reg [7:0] key; | |
wire [7:0] led; | |
brain core(clk, key, led); | |
integer c; | |
always begin | |
c = $fgetc(32'h8000_0000); | |
if (-1 == c) | |
$finish; | |
key = c[7:0]; | |
#1 clk = ~clk; | |
#1 clk = ~clk; | |
$displayb(led); | |
end | |
endmodule | |
`endif |
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all: brain | |
base64 /dev/urandom | head | ./brain | |
clean: | |
-rm -f brain | |
.SUFFIXES: .v | |
.v: | |
iverilog -Wall -DSIM -o $@ $< |
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