resume

Kritik Ashok Bhimani
bhimanikritik@gmail.com ● +91 9819901417 ● Open-Source Hardware Enthusiast ● github.com/codelec

EDUCATION 
Birla Institute of Technology and Science PILANI Goa , INDIA August 2014 – December 2017
B.E. (Hons) Electrical and Electronics Cum. GPA: 9.2 / 10.0

INTERESTS Computer Architecture • Algorithms

EXPERIENCE 
SemiFive Bengaluru , INDIA January 2022- Present
• PCIe Gen 5 Verification
• Testbench Generator
• IP+VIP Onboarding Platform
• Metastability and Gate Level Simulation
• Toolchain support for the team
SiFive Bengaluru , INDIA February 2019- December 2021
• Help team ramp up on IP Onboarding Flow
• Onboard 3rd Party IPs for Brioche
• Conduct Chisel HDL Bootcamp in Hubli and Trivandrum
• Design Low Power DMA Controller
• Design DMA Generator (spyglass clean)
• Integrate Zipline for Sesame and 100GE with SDMA
• Wake based IP Delivery flow
• Wake based GLS flow for Sesame
• Work on FireSim based Cloud Hardware Emulation Flow
• Toolchain support for the team

INTERNSHIPS 
XILINX July 2017 – December 2017
Technical Intern
• System-Level Validation of Intellectual Property developed by Ethernet and Interlaken Solutions Group
Google Summer of Code 2017 - FOSSi Foundation May 2017 – August 2017
Central Electronics Engineering Research Institute, Pilani , Rajasthan , INDIA May 2016 – July 2016
Communication between ZC706 and host motherboard with Intel i7-5960x via PCIe
• The project involved making an appropriate Vivado Block Diagram, device driver for Intel Host running Ubuntu 16.04 with Linux kernel 4.6.0 and a userspace application
• Achieved a read speed(w.r.t. host) of 500MiB/s and write speed(w.r.t. host) of 100MiB/s
PROJECT RVC support for RISCV-BOOM June 2018 – July 2018
Created a Proof-Of-Concept to demonstrate ~22% increase in Dhrystones/s after adding support to execute RISC-V Compressed Instructions in riscv-boom using Chisel3 as HDL. Design was created without any PPA constraints. https://github.com/codelec/riscv-boom/tree/rvc-dev
Linux XIA May 2015 – July 2015
Implementing perfect hashing for mapping XID types to loaded principals
Implement hash function which used Jenkin’s Lookup3 as the hash generating function and Hopscotch based collision resolution mechanism
• The algorithm ensured that within fixed ”n” lookups, the existence of key would be determined
• Used only masking and shifting to increase speed
• Achieved a performance of 2000 operations/ms where 1 operation can be either lookup (2400/ms), insertion (800/ms) and deletion (2000/ms) (test were carried on an i5 - 4210 )

SKILLS Programming
C • Scala • Assembly x86/ARM/RISC-V • SV/Verilog • Chisel • Shell

Tools
Vivado • VCS • Linux Internals