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Created September 7, 2023 04:07
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CHECK: Lines should not end with a '('
ERROR: Macros with complex values should be enclosed in parentheses
==========
checkpatch - FAILED
ERROR: Macros with complex values should be enclosed in parentheses
#148: FILE: arch/riscv/include/asm/errata_list.h:172:
+#define ALT_SBI_PMU_OVF_CLEAR_PENDING(__irq_num) \
+asm volatile(ALTERNATIVE( \
+ "csrc " __stringify(CSR_IP) ", %0\n\t", \
+ "csrc " __stringify(ANDES_CSR_SLIP) ", %0\n\t", \
+ ANDES_VENDOR_ID, ERRATA_ANDES_PMU, \
+ CONFIG_ERRATA_ANDES_PMU) \
+ : : "r"(BIT(__irq_num)) \
+ : "memory")
ERROR: Macros with complex values should be enclosed in parentheses
#157: FILE: arch/riscv/include/asm/errata_list.h:181:
+#define ALT_SBI_PMU_OVF_DISABLE(__irq_num) \
+asm volatile(ALTERNATIVE( \
+ "csrc " __stringify(CSR_IE) ", %0\n\t", \
+ "csrc " __stringify(ANDES_CSR_SLIE) ", %0\n\t", \
+ ANDES_VENDOR_ID, ERRATA_ANDES_PMU, \
+ CONFIG_ERRATA_ANDES_PMU) \
+ : : "r"(BIT(__irq_num)) \
+ : "memory")
ERROR: Macros with complex values should be enclosed in parentheses
#166: FILE: arch/riscv/include/asm/errata_list.h:190:
+#define ALT_SBI_PMU_OVF_ENABLE(__irq_num) \
+asm volatile(ALTERNATIVE( \
+ "csrs " __stringify(CSR_IE) ", %0\n\t", \
+ "csrs " __stringify(ANDES_CSR_SLIE) ", %0\n\t", \
+ ANDES_VENDOR_ID, ERRATA_ANDES_PMU, \
+ CONFIG_ERRATA_ANDES_PMU) \
+ : : "r"(BIT(__irq_num)) \
+ : "memory")
CHECK: Lines should not end with a '('
#237: FILE: drivers/perf/riscv_pmu_sbi.c:829:
+ riscv_pmu_irq = irq_create_mapping(
total: 3 errors, 0 warnings, 1 checks, 192 lines checked
NOTE: For some of the reported defects, checkpatch may be able to
mechanically convert to the typical style using --fix or --fix-inplace.
Commit ca7d05580b2a ("riscv: errata: Add Andes PMU errata") has style problems, please review.
NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF
NOTE: If any of the errors are false positives, please report
them to the maintainer, see CHECKPATCH in MAINTAINERS.
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