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%% Image frequencies

clear all
close all
clc

nSamples = 10;
f0 = 1;

% Angle generate

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/**
  Module name: decimate_x4_v1_0
  Author: P Trujillo (pablo@controlpaths.com)
  Date: Nov 2020
  Description: Module to decimate by 4 increasing 1 bit resolution.
  Revision: 1.0 Module created.
**/

module decimate_x4_v1_0 #(
  parameter pw_input_width = 14

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/* Project FFT through DMA */

/* DMA libraries */
#include "xaxidma.h"
#include "xparameters.h"
#include "xdebug.h"

/* Math library */
#include "math.h"

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/**
  Module name:  mv_avg_filter_8_v1_0
  Author: P Trujillo (pablo@controlpaths.com)
  Date: Aug 2020
  Description: 8th order moving average filter
  Revision: 1.0 Module created.
**/

module mv_avg_filter_8_v1_0 (
  input clk,

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## Buck model
clc
close all
clear all

pkg load control

s = tf('s');

fs = 1e6;

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from pynq import Overlay
import numpy as np
from scipy import signal
import matplotlib.pyplot as plt
from pynq import MMIO

# Configure the overlay
overlay = Overlay("ultra96_bd_fir.bit")

# Define the IP addresses and definition

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/* Clock forwarding for DAC. Single anded clock */
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
)ODDR_CLKDAC(
.Q(o_dac_clkout),
.C(clk100mhz),
.CE(1'b1),
.D1(1'b0),

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## Shared memory between microblaze and hdl for share parameters.
## Digital tav

set projectDir ../project

## Delete log and journal
file delete {*}[glob vivado*.backup.jou]
file delete {*}[glob vivado*.backup.log]
file delete -force .Xil/